CN110544626B - 碳化硅衬底上的电接触 - Google Patents

碳化硅衬底上的电接触 Download PDF

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Publication number
CN110544626B
CN110544626B CN201910450618.0A CN201910450618A CN110544626B CN 110544626 B CN110544626 B CN 110544626B CN 201910450618 A CN201910450618 A CN 201910450618A CN 110544626 B CN110544626 B CN 110544626B
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layer
metal layer
cleaning process
nickel
chemical cleaning
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CN110544626A (zh
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S.克里韦克
R.柯恩
S.克拉姆普
G.兰格
H.温克勒
S.韦勒特
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及碳化硅衬底上的电接触。一种用于在碳化硅衬底（105）上制造具有第一金属层（111）和至少一个第二金属层（121‑123）的电接触（106）的方法包括：执行化学清洁工艺（300），以去除碳残留物（302）的至少一部分，用于清洁第一金属层（111）。第一金属层（111）和/或第二金属层（121‑123）可以通过溅射沉积来产生。

Description

碳化硅衬底上的电接触
技术领域
本发明的各种实例涉及与碳化硅（SiC）衬底的电接触（Kontaktierung）有关联的技术。尤其是，各种实例涉及技术，以便快速地和可靠地在SiC衬底上制造高质量的电接触。
背景技术
功率半导体器件有与高电压和／或高电流的切换有关联的特别的能力。功率半导体器件因此在各种领域中被采用，诸如在比方说离岸风力涡轮机、智能电网部件的高电压直流传输中被采用，或者在有轨车辆的驱动中被采用，等等。
功率半导体器件常常构造在碳化硅（SiC）中。SiC是具有比较大的带隙的半导体材料。这要求与高电压和／或高电流的切换有关联的特别的能力。
目前采用的针对SiC半导体器件的生产技术的缺点是比较复杂的电接触生产。为了提供SiC衬底的稳健的（robust）电接触，根据参考实施方式可能需要费事的工艺步骤。这可能是昂贵的和耗时的。
发明内容
一种用于在碳化硅衬底上制造具有第一金属层和至少一个第二金属层的电接触的方法包括：在碳化硅衬底上沉积第一金属层，和使第一金属层退火，由此形成碳残留物。该方法也包括：执行化学清洁工艺，以去除碳残留物的至少一部分，用于清洁第一金属层。该方法也包括：在已清洁的第一金属层的表面上沉积至少一个第二金属层。
芯片包括碳化硅衬底以及在碳化硅衬底上的所溅射的第一金属层。芯片也包括在第一金属层上的至少一个所溅射的第二金属层，其中第一金属层和至少一个第二金属层构造电接触。
芯片包括碳化硅衬底、在碳化硅衬底上的第一金属层和在碳化硅衬底上的至少一个第二金属层。在此，第一金属层可以包括镍硅层，其中所述至少一个第二金属层包括层序列，所述层序列具有钛层、含镍的层和利用金和锡或者利用银形成的层。
上面陈述的特征和随后描述的特征不仅可以以相对应的明确陈述的组合来使用，而且可以以其他组合或者单独地来使用，而不离开本发明的保护范围。
附图说明
图1示意性地图解说明了根据各种实例的芯片，该芯片具有SiC衬底和在SiC衬底上的电接触。
图2是示例性的方法的流程图。
图3是示例性的方法的流程图，其中图3图解说明了根据各种实例的化学清洁工艺的细节。
图4示意性图解说明了根据各种实例的化学清洁工艺的细节。
具体实施方式
结合下列对实施例的描述，本发明的上面所描述的特性、特征和优点以及如何实现这些特性、特征和优点的方式和方法变得更清楚地且更明确地可理解，所述实施例结合附图更详细地予以阐述。
随后，依据实施形式参照附图更详细地阐述本发明。在这些图中，相同的附图标记标明相同的或者类似的元件。这些图是本发明的各种实施形式的示意性表示。在这些图中所示出的元件并不一定比例正确地示出。更确切而言，在这些图中所示出的各种元件被再现为使得：这些元件的功能和通用目的对于本领域技术而言变得可理解。
随后，描述了与半导体器件的制造有关联的技术。半导体器件可以实施为具有两个端子，例如通过二极管来实施。半导体器件也可以实施为具有三个端子，诸如通过场效应晶体管、尤其是金属氧化物场效应晶体管或者带有绝缘栅电极的双极性晶体管或者阻挡层场效应晶体管或者晶闸管来实施。半导体器件也可以具有多于三个的端子。在各种在本发明所描述的实例中，半导体器件可以是功率半导体器件。这意味着：半导体器件可以切换特别高的电压（例如至少250V或者至少600V）和/或特别高的通过电流（Stromfluss）（比方说大于1A的通过电流）。
半导体器件可以是芯片（也称为：半导体芯片或者半导体管芯），或者半导体器件可以集成在芯片上。针对半导体器件和/或针对用于制造半导体器件的方法所公开的所有特征因此对于芯片和/或对于用于制造芯片的方法而言也是公开的，反之亦然。例如，芯片仅仅由半导体材料构建。
随后，例如为了制造功率半导体器件，尤其是描述了与具有大带隙的半导体材料的处理有关联的各种实例。在此，大的带隙的使用一般标明具有至少2eV、例如至少2.5eV的带隙的半导体材料。这种具有大的带隙的半导体材料、诸如SiC（比方说尤其是4H-SiC）或者氮化镓（GaN）有例如至少2.5MV/cm的大击穿场强和高临界雪崩场强。因此，与具有较小带隙的半导体材料相比，可以使用半导体区域的较大的掺杂密度。这又导致在导通状态下的较低的电阻。随后，讨论了各种实例，特别与作为半导体材料的SiC有关联的实例，其中相对应的技术原则上也可以针对另外的类型的半导体材料而被采用。SiC能够实现半导体器件的特别有利的电学特征，尤其是实现功率半导体器件的特别有利的电学特征。
借助SiC衬底实施（即例如构造在SiC衬底中和/或例如基于SiC衬底）的各种半导体器件使用穿过衬底至电接触部（Kontakt）的电通过电流。常常关于相对应的半导体器件在衬底的相对置的侧上布置电接触部。典型地，如下这个侧被称作SiC衬底的正面：在该侧处，构造至少一个半导体器件（例如，所述至少一个半导体器件的功能区、如掺杂区）；并且相对置的侧被称作背面。正面在4H-SiC衬底中常常被称作Si侧，背面被称作C侧。在本上下文中，布置在SiC衬底的背面上的电接触也被称作背面接触。但是，一般而言，在本发明所描述的技术也可以用于构造正面接触。但是随后，出于简洁原因特别描述了关于背面接触的技术；为了实施正面接触，也可以使用这些技术。
电接触可以包括大面积的接触垫，例如至少250µm x 250µm大。电接触可以提供SiC衬底的低欧姆的接触部。尤其是，电接触可以包括第一金属层和至少一个第二金属层。
采用电背面接触的实例涉及将金属氧化物场效应晶体管的漏极端子构造为（功率）半导体器件，或者将二极管的两个端子中的一个端子构造为（功率）半导体器件。
在参考实施方式中，在SiC衬底上制造电接触典型地借助镍基合金来产生。例如，沉积（例如具有11重量%的硅的）薄镍硅金属层可以在SiC衬底的表面上进行。为了构造电接触，接着可以进行合金的热处理（退火），以便触发与SiC衬底的反应：SiC+2Ni→ Ni2Si +C。这通常被称作硅化（Silizidierung）。为此典型地需要至少950℃的温度。在一些实例中，使用激光促成的热加温（英语：laser thermal annealing（激光热退火）；LTA），因为经此可以避免损坏半导体器件。
各种在本发明所描述的用于制造电接触的方法的实施方式基于如下认知：作为这种退火的副产品，在SiC与镍硅之间的过渡部处和/或在未经转变的镍硅的表面处可能形成碳。镍硅的表面在这种情况下背离SiC衬底。已认识到，在未经转变的镍硅的表面处的这种碳残留物可能损害稍后施加的电接触的机械特性。例如已查明的是，至少一个第二金属层在镍硅金属层（尤其是镍硅金属层的表面）上的粘附可能由于形成的碳而被降低。然而可能的是，在SiC衬底与镍硅之间的过渡部处的欧姆接触部通过在那里形成的碳残留物而被改善。
根据各种实例，描述了技术，以便结合在SiC衬底上制造电接触而可靠地去除在表面处的碳的这种残留物。经此，可以提供一种具有经改善的可靠性的电接触，尤其是具有与机械特性（诸如粘附性）有关联的经改善的可靠性的电接触。
根据各种在本发明所描述的技术，可以详细地提供具有特别良好的特性的电接触。可以制造高导电性、即欧姆接触部。此外，可以确保电接触的相对应的金属层在SiC衬底上的稳定粘附。
此外，电接触可以不将过大张力（Verspannung）或者仅将少量的过大张力传递到SiC衬底上。经此，可以避免由于也与半导体器件有关联的机械过大张力而引起的形变。
最后，电接触可以提供一个或者多个接触垫，所述接触垫可以提供焊接连接或者带有晶片接合（Wafer-Bonding）的连接。例如，在各种应用中，具有半导体器件的芯片借助焊接工艺被安置在引线框架（英语：lead frame）处或者在另外的模块之内。在该情况下，接触垫要具有电学的和机械的特性，这些特性能够实现可靠的和稳定的焊接连接。
在各种实例中，为此首先在SiC衬底上沉积第一金属层，例如沉积镍合金和/或含镍的层。接着，使第一金属层退火。经此，尤其是在第一金属层的背离SiC衬底的表面处，形成碳残留物。紧接着，执行化学清洁工艺，由此通过清洁第一金属层来去除碳残留物的至少一部分。接着，在已清洁的第一金属层的表面上沉积至少一个第二金属层。
化学清洁工艺对应于通过一种或者多种化学反应去除碳残留物。化学清洁工艺尤其是可以相对于物理清洁工艺被定界，在（不同于化学清洁工艺的）物理清洁工艺中，没有发生物质的化学转变。在物理清洁工艺中，例如仅仅通过机械作用来进行清洁。
通过化学清洁工艺，可以特别可靠地且快速地去除碳残留物。此外，化学清洁工艺可以具有针对要去除的材料、尤其是针对碳残留物的高选择性。与此相比，在参考实施方式的物理清洁工艺中可能的是，物理清洁工艺导致损伤在碳残留物下的第一金属化部的材料，由此例如使第一金属化部粗糙。化学清洁工艺因此可以例如能够实现提供较光滑的表面。
例如，在参考实施方式中，在沉积至少一个第二金属层之前使用物理清洁工艺，诸如利用氩离子在原位轰击。可能的是，这样的物理清洁工艺具有针对要去除的材料的低选择性。此外可能的是，与物理清洁工艺相比，借助化学清洁工艺可以实现干净的表面。
此外，在一些实施方式中可能的是，物理清洁工艺在用于蒸镀（Aufdampfen）的真空室中（即在原位利用蒸镀工艺）来执行，这招致连接在下游的蒸镀工艺。蒸镀通常是批量（Batch）工艺，在所述批量工艺中同时处理多个晶片。在蒸镀过程期间的工艺缺陷因此对多个晶片产生作用，由此提高成本风险。与此不同，溅射沉积可以作为单个工艺（即针对仅仅唯一的晶片）来执行，由此工艺缺陷只能对其中一个晶片产生作用。相对应地，在使用纯溅射沉积时，可以减小成本风险。
如果要借助溅射沉积将其他金属化部施加到被蒸镀的金属化部上，则通常需要更换设施，并且由此破坏真空。例如，这可能导致污染和/或以其他方式不利地改变露出的表面，在所述露出的表面上要执行溅射沉积。相对应地，可以减小在借助溅射沉积施加的金属化部与借助蒸镀施加的金属化部之间的连接的机械稳定性，并且由此减小整个电接触的机械稳定性。
此外，执行物理清洁工艺可能比较耗时，例如在典型的实施方式中需要大约20分钟的持续时间。这可能成本高昂地设计电接触的制造。此外，在执行物理清洁工艺之后，可能进行碳的重新沉积。所有这种缺点可以通过放弃物理清洁工艺或通过使用化学清洁工艺来避免。
随后尤其是描述了下列实例：
在一实例中，提供了一种用于在碳化硅衬底上制造电接触的方法，所述电接触具有第一金属层和至少一个第二金属层，其中该方法包括：在碳化硅衬底上沉积第一金属层，和使第一金属层退火，由此形成碳残留物，并且执行化学清洁工艺，以将碳残留物的至少一部分去除，用于清洁第一金属层。该方法也包括：在已清洁的第一金属层的表面上沉积至少一个第二金属层。
化学清洁工艺可以将碳残留物例如转化到气相。
化学清洁工艺例如可以包括输送氧等离子体。
化学清洁工艺例如可以包括化学刻蚀。
化学刻蚀例如可以利用氢氟酸来执行。
可能的是，沉积第一金属层包括第一溅射沉积。
可能的是，沉积至少一个第二金属层包括至少一个第二溅射沉积。
在一些实例中，可以沉积多个第二金属层，其中在原位进行多个第二金属层的沉积。
在一实例中，芯片包括碳化硅衬底以及在碳化硅衬底上的所溅射的第一金属层。芯片也包括在第一金属层上的至少一个所溅射的第二金属层，其中第一金属层和至少一个第二金属层构造电接触。
至少一个第二金属层例如可以包括一个或者多个从下列组中选出的层：钛层；铝层；含镍的层（例如镍钒层或者镍硅层）；金锡层；和银层。金锡层和银层可以是彼此的替选物。
对于这里所描述的所有实施例可能的是，金锡层（或者银层）一般通过含锡的层来替换。尤其是，镍锡层是可设想的。
例如会可能的是，至少一个第二金属层包括缓冲层，所述缓冲层设立为，缓冲在第二金属层之内的机械过大张力。
在一实例中，芯片包括碳化硅衬底、在碳化硅衬底上的第一金属层和在碳化硅衬底上的至少一个第二金属层。在此，第一金属层可以包括镍硅层。至少一个第二金属层可以包括层序列。例如，层序列利用钛层和含镍的层形成。此外，层序列可以包括可焊接的层，诸如金锡层或者银层。尤其是，层序列可以包括钛层、含镍的层（例如镍钒层或者镍硅层）和金锡层。可替选地，层序列可以包括钛层、含镍的层（例如镍钒层或者镍硅层）和银层。在含镍的层与银层之间可以存在其他钛层。层序列的层可以以所说明的顺序彼此跟随。
这种芯片例如可以按照上面所描述的方法中的一种方法来制造。
图1图解说明了关于芯片100的方面。芯片100包括SiC衬底105以及布置在SiC衬底105上的电接触106。
图1的图示并不是比例正确的。典型地，SiC衬底105的厚度105A（即在SiC衬底105的正面105-1和背面105-2之间的竖直的伸展）显著地大于电接触106的厚度106A。例如，SiC衬底105的厚度105A典型地在50µm到500µm的范围中；而电接触106的厚度106A典型地在1µm到20µm的范围中。
在图1中示出了，电器件109限定在SiC衬底105中。借助半导体器件109，常常可以控制在正面接触与背面接触106之间的通过电流。接着，通过电流流经SiC衬底105。
在图1的实例中，电接触106包括多个金属层。电接触106尤其是包括第一金属层111，例如通过镍硅层来实施的第一金属层111。电接触106也包括多个第二金属层121-123，在图1的实例中，第二金属层通过层序列120来实施。层序列120可以安置在第一金属层111的背离SiC衬底105的侧处。层序列120可以具有上部的第二金属层121、中间的第二金属层122和下部的第二金属层123。
上部的第二金属层121可以直接与第一金属层111邻接。例如，上部的第二金属层121利用钛形成。上部的第二金属层121可以包含钛层，或者是钛层。在上部的金属层121的背离SiC衬底105的侧处安置中间的金属层122。中间的第二金属层122可以具有唯一的层或者多个层。例如，中间的第二金属层122包含含镍的层（例如镍钒层或者镍硅层），或者由含镍的层制成。附加地，中间的第二金属层122可以在中间的第二金属层122的背离上部的第二金属层121的侧处具有钛层。跟随中间的第二金属层122的是下部的第二金属层123。下部的第二金属层123可以直接与中间的第二金属层122邻接。下部的第二金属层123可以是电接触106的外部金属层。例如，下部的第二金属层123可从外部自由到达和/或是可焊接的。下部的第二金属层123可以具有含锡的层，或者由其制成。例如，下部的第二金属层123包含金锡层或者镍锡层，或者是金锡层或者镍锡层。替选地，下部的第二金属层123可以是银层，或者包含银层。
在一些实施例中，上部的第二金属层121是钛层，中间的第二金属层122是镍钒层，和下部的第二金属层123是金锡层。在另外的实施例中，上部的第二金属层121是钛层，中间的第二金属层122是由镍钒层和钛层构成的层堆叠，并且下部的第二金属层123是银层。在上述的实施例中的两个实施例中可能的是，通过镍硅层替换镍钒层。
已查明的是，电接触106和尤其是层序列120的这种构造具有与电接触106的机械稳健性有关联的特别的优点，以及具有与电接触106的构造（例如针对焊接接触部或者针对晶片接合的）接触垫的能力有关联的特别的优点。接触垫例如可以通过表面106-1来构造。
代替纯的电接触，该接触也可能会通过附加地或者替选地提供机械连接（在下文也称作“机械连接”）的接触而能够实现。针对机械连接的实例是烧结或者粘合。
另一方面，在各种实例中可能的是，改变或者变换层序列120。（i）例如，可能会在上部的第二金属层121与第一金属层111之间设置其他层，以便缓冲机械过大张力。实例会是铝层。（ii）作为其他实例，代替钛层，也可能会将铝层用作上部的第二金属层121。通过将钛层设置为上部的第二金属层121，可以提供第一金属层111的整个面的良好润湿（英语：wetting）。铝也可以具有相对应的特性。（iii）通常可以将不同的合金用作下部的第二金属层123。金锡层具有与通过焊接、尤其是扩散焊接实现的接触有关联的特别良好的特性。具有良好的焊接接触特性的另外的材料系例如包括：镍锡，基于镍的合金、例如镍硅、镍钒等等。（iv）其他可选的层可能会提供氧化防护。这样的层例如可能会利用银（Ag）形成，或者在制造公差的范围中由银制成。所有这种实例（i）-（iv）也可以相互组合，或者应用于绝缘中。
作为通则（allgemeine Regel），可以采用不同的技术用于制造根据图1的实例的芯片100。结合图2描述了示例性的用于制造芯片100的电接触106的方法。
图2是示例性的用于在SiC衬底上制造电接触的方法的流程图。例如，为了根据图1的实例在SiC衬底105上制造电接触106，可能会使用根据图2的方法。
首先，在框1001中，在SiC衬底上沉积第一金属层111（例如图1的实例中的镍硅层111）。例如，在框1001中，第一金属层可能会被沉积在SiC衬底的正面或者背面上。
接着，在框1002中，使所沉积的第一金属层退火。在此，可以进行不同的用于退火的技术，即热激活，以化学转变第一金属层。实例包括LTA（Laser Thermal Anneal（激光热退火））和快速热修复（Ausheilen）。
接着，在框1003中，执行化学清洁工艺。化学清洁工艺用于至少部分地去除由于框1002中的退火形成的残留物。例如，可以完全（即完全在测量精度的范围中）去除碳残留物。尤其是，由于使处于SiC衬底上的第一金属层退火形成的碳残留物可以通过框1003中的执行化学清洁工艺而完全地或者部分地被去除，由此清洁第一金属层。
在执行化学清洁工艺之后，紧接着在框1004中沉积至少一个第二金属层。例如，在框1004中，可能会沉积根据图1的实例的层序列120，该层序列120具有钛层121、镍钒层122以及金锡层123。
随后讨论了与根据图2中的方法的各种工艺步骤1001-1004的可能的实施方式有关联的各种细节。实例尤其是结合图2中的用于制造来自图1的实例的芯片100的电接触106的方法的使用予以阐述，其中一般而言也可能会使用与电接触的另外的实施方式有关联的相对应的技术。
在各种在本发明所描述的实例中，不同的技术是可能的，以便在框1001中沉积第一金属层，或以便在框1004中沉积至少一个第二金属层。可以结合在各种在本发明所描述的实例中的金属层的沉积而应用的技术包括：蒸镀，例如通过坩埚的加热或者通过使用进行加热的电子束来蒸镀；和溅射。
在溅射沉积中，通过利用离子（例如惰性气体离子）轰击，使原子从要沉积的金属（标靶（Target））的储存器（Reservoir）中析出（herausloesen）。原子转到气相，并且紧接着沉淀在要涂层的表面上。储存器在此形成阴极，离子通过加速电压朝该阴极被加速。加速电压以及环境压力限定了临界的工艺参数。此外可能的是，溅射沉积具有（与热蒸发涂覆（Bedampfung）相比）表征性的纳米/微观组织。例如，多孔性、即孔的密度、孔大小和/或孔布局可以是表征性的。尤其是可能的是，通过溅射沉积构造表征性的微晶，即具有特定的大小、形状和/或取向的微晶。粒度大小可以是表征性的。表征性的纹理是可实现的。借助溅射沉积而沉积的金属层因此尤其是可以依据在金属层中的晶体生长而区别于借助另外的方法（譬如借助蒸镀）而施加的金属层。
尤其是，在各种在本发明所描述的实例中可能的是，分别通过相对应的溅射沉积，既产生框1001中的第一金属层（即尤其是镍硅层111），又产生框1004中的至少一个第二金属层（即尤其是层序列120）。
尤其是，在框1004中，可以沉积多个第二金属层，所述第二金属层可以在其材料方面不同。第二金属层可以共同地形成电接触。在框1004中的沉积第二金属层可以在原位进行，即在此期间没有损失或破坏真空的情况下进行。例如可能的是，在原位处理的情况下，工艺室中的在执行两个工艺步骤1003和1004之间的压力在任何时刻都大于1mbar。在原位处理例如可以在相同的工艺室中执行。
通过避免在工艺步骤1004中沉积第二金属层期间破坏真空，可以减小污染电接触106的风险。此外曾观察到，通过避免破坏真空，可以改善通过焊接或者晶片接合电接触106产生的接触的可靠性。例如，可以避免使用氧化防护层（例如由铂或者另外的贵金属制成的氧化防护层）；由此又可以改善结构上的完整性和强度，该强度结合制造焊接连接的能力可能是特别重要的。
此外，由于所使用的清洁工艺可以可能的是，省去蒸镀工艺。典型地，蒸镀工艺与手动地操纵相对应的芯片100相关，这带来破坏、污染或者损害的风险。这种缺点可以通过溅射来避免。
此外，溅射沉积（由于减小的处理时间）可以在单个晶片处执行。与此相反，蒸镀工艺大多数以批量工艺执行。在不良品（Verwurf）的情况下，可以减少在处理单个晶片时的次品（和因此形成的成本）。
此外曾观察到，例如金锡层可以特别良好地且可靠地通过溅射沉积来提供。这通常要求干净的表面，所述干净的表面可以借助这里所描述的化学清洁工艺来保证。尤其是，对于借助溅射沉积而沉积的金锡层的良好粘附可能有利的是，前面的层曾同样借助溅射沉积来沉积，使得在各个工艺步骤之间不需要破坏真空。
作为通则，也可以使用与根据工艺步骤1003的化学清洁工艺有关联的不同技术。工艺步骤1003的示例性的实施方式在图3的方法中示出。
图3是示例性的方法的流程图。在图3中示出了，可以使用两级的化学清洁工艺。
首先，在工艺步骤1011中，可以输送氧等离子体。通过输送氧等离子体可以引起，碳残留物的至少一部分被转化到气相。碳残留物接着可以被抽出。同时（通过氧等离子体）可以构造氧化物残留物。化学清洁工艺可以包括化学刻蚀，以便去除氧化物残留物。例如，可以利用氢氟酸或者硫酸执行化学刻蚀。对于化学清洁工艺300的这种示例性的实施方式的细节也在图4的示意图中示出。
图4示例性地图解说明了与化学清洁工艺300有关联的示例性方面。在图4中示出了，碳残留物302可以存在于金属层111的表面上，以及也部分地（通过扩散）存在于金属层111之内。化学清洁工艺300接着包括：输送氧等离子体301。经此，碳残留物302被转化到气相312，这里通过形成一氧化碳和二氧化碳来示出。氧化物311构造在金属层111的表面上，该氧化物311又可以通过比方说利用氢氟酸进行化学刻蚀来去除（在图4中未示出）。
为了产生氧等离子体，可以应用不同的技术。例如，相对应的基可以在反应器中产生，比方说通过微波发生器产生。在此，使用氧等离子体301来将碳残留物302转化到气相312仅仅是示例性的。在另外的实例中，也可以使用另外的技术来将碳残留物302转化到气相312，例如在使用氢的情况下将碳残留物302转化到气相312。作为通则，代替氧等离子体也可以使用另外的类型的基。实例可能是氮氧化物等离子体。
化学刻蚀可以以各种方式和方法来实施。例如，氢氟酸处理可以通过浸没、在转盘加料器上的刻蚀、蒸化处理等进行。
尤其是与具有在使用氩轰击的情况下的物理清洁工艺的参考实施方式相比，这种化学清洁工艺300具有优点。尤其是，可以避免伤害金属层111的结构。
总之，已描述了上面提到的技术，所述技术能够实现去除在金属层处的碳残留物，该金属层已施加到SiC衬底上。这可以通过化学清洁工艺来进行。由此，可以将碳残留物转化到气相，使得处于气相中的碳残留物可以从反应环境中被去除。可以避免碳残留物的再沉积。经此，实现电接触，而没有显著的碳残留物份额。在各种实例中，比方说通过借助氢氟酸的化学刻蚀，可以去除化学清洁工艺的伴随产物、例如氧化物层。
通过这种技术可能的是，将电接触部的外层（例如金锡层）溅射到润湿层上，其中溅射尤其是可以在原位进行。在原位处理能够实现极大地减小对电接触的污染，由此又能够实现电接触在SiC衬底上和/或电接触的各个层彼此间的经改善的机械附着。
借助在本发明所描述的技术，也可以实现成本减小，因为可以降低用于进行处理的持续时间。
不言而喻地，可以将本发明的事先描述的实施形式和方面的特征相互组合。尤其是，这些特征不仅可以以所描述的组合被使用，而且可以以另外的组合或者独立地被使用，而不离开本发明的范围。
这样，例如可以使用在本发明所描述的技术来既在SiC衬底的正面上又在SiC衬底的背面上制造电接触。
例如，已描述了在上面提到的技术，以便提供确定的层序列，所述确定的层序列包括钛层、镍钒层和金锡层。代替这种实施方式，也可以在已清洁的镍硅层上提供另外的层序列。例如，代替钛也可能会使用铝或者铂。除了钛层，也可能会提供铝，以便能够实现对过大张力的吸收。铂层可能会作为氧化防护来提供，以便能够实现非原位沉积金锡层。

Claims (17)

1.一种用于在碳化硅衬底(105)上制造电接触(106)的方法，所述电接触(106)具有第一金属层(111)和至少一个第二金属层(121-123)，其中所述方法包括：
-在所述碳化硅衬底(105)上沉积所述第一金属层(111)，
-使所述第一金属层(111)退火，由此形成碳残留物(302)，
-执行第一化学清洁工艺(300)，以去除所述碳残留物(302)的至少一部分，用于清洁所述第一金属层(111)，其中在所述第一化学清洁工艺(300)期间在所述第一金属层(111)上形成氧化物残留物，
-执行不同于所述第一化学清洁工艺(300)的第二化学清洁工艺，以去除所述氧化物残留物的至少一部分，用于清洁所述第一金属层(111)，以及
-在所述第一化学清洁工艺(300)和所述第二化学清洁工艺之后，在已清洁的第一金属层(111)的表面上沉积至少一个第二金属层(121-123)。
2.根据权利要求1所述的方法，
其中，所述第一化学清洁工艺(300)将所述碳残留物(302)转化到气相。
3.根据权利要求1或者2所述的方法，
其中，所述第一化学清洁工艺(300)包括输送氧等离子体。
4.根据权利要求1或者2所述的方法，
其中，所述第一化学清洁工艺(300)包括输送氮氧化物等离子体。
5.根据权利要求1所述的方法，
其中，所述第二化学清洁工艺包括化学刻蚀。
6.根据权利要求5所述的方法，
其中，利用氢氟酸执行所述化学刻蚀。
7.根据权利要求5所述的方法，
其中，利用硫酸执行所述化学刻蚀。
8.根据权利要求1所述的方法，
其中，沉积所述第一金属层(111)包括第一溅射沉积，以及
其中，沉积所述至少一个第二金属层(121-123)包括至少一个第二溅射沉积。
9.根据权利要求1所述的方法，
其中，沉积多个第二金属层(121-123)，其中沉积多个第二金属层(121-123)在原位进行。
10.根据权利要求1所述的方法，
其中，所述至少一个第二金属层(121-123)包括一个或者多个从下列组中选出的层：
钛层(121)；铝层；镍硅层；镍钒层；和金锡层。
11.根据权利要求1所述的方法，
其中，所述至少一个第二金属层(121-123)包括一个或者多个从下列组中选出的层：
钛层(121)；铝层；含镍的层；和银层。
12.根据权利要求1所述的方法，
其中，所述至少一个第二金属层(121-123)包括缓冲层，所述缓冲层设立为，缓冲在所述第二金属层之内的机械过大张力。
13.一种芯片(100)，其按照根据权利要求1至12中任一项所述的方法来制造，并且所述芯片(100)包括：
-碳化硅衬底(105)，
-在所述碳化硅衬底(105)上的所溅射的第一金属层，以及
-在所述第一金属层(111)上的所溅射的至少一个第二金属层(121-123)，
其中所述第一金属层(111)和所述至少一个第二金属层(121-123)构造电接触(106)。
14.根据权利要求13所述的芯片(100)，
其中，所述至少一个第二金属层(121-123)包括一个或者多个从下列组中选出的层：
钛层(121)；铝层；镍硅层；镍钒层；和金锡层。
15.根据权利要求13所述的芯片(100)，
其中，所述至少一个第二金属层(121-123)包括一个或者多个从下列组中选出的层：
钛层(121)；铝层；含镍的层；和银层。
16.根据权利要求13至15任一项所述的芯片(100)，
其中，所述至少一个第二金属层(121-123)包括缓冲层，所述缓冲层设立为，缓冲在所述第二金属层之内的机械过大张力。
17.一种芯片(100)，其按照根据权利要求1至12中任一项所述的方法来制造，并且所述芯片(100)包括：
-碳化硅衬底(105)，
-在所述碳化硅衬底(105)上的第一金属层(111)，以及
-在所述碳化硅衬底(105)上的至少一个第二金属层(121-123)，
其中所述第一金属层(111)包括镍硅层，
其中所述至少一个第二金属层(121-123)包括层序列(120)，所述层序列(120)具有钛层(121)、含镍的层(122)和金锡或者银层(123)。
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