CN1105416C - 与并联谐振电路配合工作的平衡集成半导体器件 - Google Patents
与并联谐振电路配合工作的平衡集成半导体器件 Download PDFInfo
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Abstract
一种平衡频率响应电路(9),其电路元件在半导体芯片上形成,其第一和第二芯片上的接触端(12,13)分别接芯片外的接触端(14,15),接触端(12-15)上耦合有由电容部分(C1′,C2′,C3)和电感部分(L1′,L2′)构成的平衡并联谐振电路(20)。电容部分的(C1′)部分在芯片上连接在第一和第二芯片上接触端(12,13)间。电容部分的另一(C2′,C3′)部分和电感部分在芯片外串联连接在对应的芯片外接触端(12,13)间,从而使接触端(12-15)包含在单一谐振环路中。
Description
本发明总的说来涉及集成半导体器件,更具体地说,涉及这样一种集成半导体器件,半导体器件的诸多电路元件形成芯片上的平衡频率响应电路(例如平衡振荡电路),设计得使其与芯片外的并联谐振电路配合工作。频率响应电路可形成诸如射频收发信机、调制器或混频电路之类更大集成电路的一部分。
本发明的上述那一种集成频率响应电路一般利用外部或芯片外的平衡谐振电路将谐振引入电路中。周知的实例是由这样一个平衡振荡电路形成的,平衡振荡电路的有源部分作为芯片上的集成半导体电路设置,芯片外的无源谐振部分通过芯片封装的一个或多个接触端与有源部分连接,凑成完整的振荡电路。
举例说,目前的无线电电信系统设计的工作频带都在超高频(SHF)频带或低端微波频带,即高达10GHz或甚至更高的频率。通常使用的与接触端或插脚、焊片和连接引线一起装在引线框架上且封装起来的集成电路在这些高频下表现为接触端、焊片、连接引线和引线框架的高频内在电容和电感。
本技术领域的行家们都知道,在如此之高的频率下,如上述那样将芯片外的谐振电路耦合到芯片上的频率响应电路时,内在电容和电感对电路频率响应的影响总的说来是很大的。在平衡并联谐振电路的情况下,这个影响的后果不仅会使电路的谐振频率失谐,阻抗发生变化,而且还会产生不必要的寄生振荡频率。因此,举例说,采用芯片外平衡并联谐振电路形成的谐振的振荡电路在各种不同的寄生谐振频率下会产生不希望有的输出信号。
进行射频设计时,通常总是优先采用平衡频率响应电路,因为这些电路的共模抑制比较高,在通过未经控制的通路返回信号地线中实际上没有不必要的射频辐射,也没有整个电路的地电位升高的现象。
本发明的目的是提供这样一种平衡频率响应电路,电路的诸多电路元件在半导体芯片中形成,或作为较大集成电路的一部分形成,与某一平衡并联谐振电路配合工作,而且尽可能避免芯片封装有关的内在电容和电感引起的寄生谐振频率。
本发明的另一个目的是提供这样一种集成半导体器件,集成半导体器件的一些电路元件形成至少一部分的平衡频率响应电路待与芯片外的平衡并联谐振部分配合工作,以便形成的频率响应电路,使其因半导体电路的封装有关的内在电容和电感引起的寄生谐振频率尽可能少。
具体地说,本发明的目的是提供一种包括平衡振荡电路的频率响应电路。
本发明提供的平衡频率响应电路,其包括在半导体芯片上形成的电路元件该半导体芯片具有第一和第二在芯片上的接触端分别与第一和第二芯片外的接触端连接。一个平衡并联谐振电路耦合到各接触端上,并包括电容部分和电感部分。按照本发明,谐振电路一部分的电容部分是在芯片上连接在第一和第二芯片上之间,另一部分电容部分和电感部分则在芯片外串联连接在第一和第二芯片外端之间。这样,连同电容部分在芯片上的连接部分形成的并联谐振电路在单个谐振回路中有多个接触端。
按照本发明,通过将芯片上并联谐振电路电容部分的一部分安置在芯片上各接触端之间将内在封装电容在电气上与芯片上的谐振部分合并,同时将内在电感在电气上与芯片外谐振电路的电容部分和电感部分的串联连接部分合并,形成单一个谐振环路。这样,频率响应电路实质上抑制的是单一的谐振频率。
本发明是根据这样的见解提出的:通过将组件(即内在电容和电感)合并成谐振电路的一个整体部分实质上最大限度地减小了组件电气参数对电路频率响应特性总的影响。
在本发明的一个最佳实施例中,在芯片外连接电容部分的第一部分和电感部分的第一部分串联连接在第一芯片外接触端与电路信号地线之间,芯片外连接的电容部分的第二部分和电感部分的第二部分串联连接在第二芯片外接触端与电路信号地线之间。这些串联接线的结构在电气上对称。
在本实施例的情况下,通过调节芯片外连接的电容部分,可以精确调节谐振电路的谐振频率从而精确调节其阻抗,使其与频率响应电路芯片上部分的阻抗匹配。
谐振电路芯片上连接电容部分可由一个分立的电容器装在半导体基片上形成。然而,由于经常会提出设备小型化的要求,因而按照本发明的另一个实施例,芯片上连接的谐振部分还可以加装与半导体基片形成一个整体的电容。这类集成电容的形成在半导体器件工艺中是公知技术。
本技术领域的行家们知道,芯片外连接的谐振部分可包括分立的常规无源电容器和线圈以及半导体集成电容和电感,后者可在半导体芯片中以电子学的方法产生或按实际情况形成,这是半导体器件制造工艺中的公知技术。
本发明还涉及一种半导体集成电路器件,它包括在本导体芯片中形成的电路元件。各电路元件配置得使其包括至少一部分频率响应电路,它具有第一和第二芯片上的接触端,这些接触端分别与第二芯片外接触端连接。半导体器件用作频率响应电路时,各接触端必须连接一个包括电容部分和电感部分的平衡并联谐振电容。然而,按照本发明,谐振电路电容部分的一部分业已在芯片上连接在半导体器件第一和第二芯片上的接触端之间。
在本发明的一个特殊实施例中,各电路元件配置得使其形成所谓平衡振荡电路。
本发明的频率响应电路可以按周知的外差原理形成更大集成电路的一部分,例如具有混频或调制电路耦合到形成本机振荡器(LO)的频率响应电路的收发信电路。这方面可参看A.Bruce Carlson著的“通信系统”一书的第5章(McGraw-Hill)出版社出版,第二版)。
下面参看附图举例说明本发明的上述和其它特点和优点。
图1是具代表性的现有技术大规模集成电路的示意顶视图,集成电路的封装部分剖开以供举例说明。
图2是集成或芯片上平衡频率响应电路和外部或芯片外谐振电路的具代表性现有技术的接线电路图。
图3是图2所示电路的集总元件等效电路图。
图4示出了图3所示的电路图中可加以区分的一些谐振环路。
图5是本发明集成或芯片上平衡频率响应电路和外部或芯片外谐振电路的电路图。
图6是图5所示的本发明电路的集总等效电路图。
图7a和7b是分别在图2和图5电路的芯片上焊片测出的阻抗与频率的关系曲线图。
图8是本发明集成电路器件的示意顶视图,集成电路的外壳部分剖开以供举例说明。
图9是本发明振荡电路的电路图。
图10是本发明具振荡电路的集成半导体收发信装置的方框图。
现在就一个实施例举例说明本发明的内容但并不因此而限制本发明的内容。附图中,同样的电路元件和部件用同样的编号表示。
图1示出了现有技术的一般大规模集成电路器件1,器件1的塑料封装外壳2封装着半导体集成电路基片或芯片3,器件1的多个接触端4取例如表面安装的触片形式或在印刷电路板(PCB)上通孔连接的触针形式。为了举例说明,封表外壳2以部分剖视的形式示出。
芯3中除其它零部件外还包括频率响应电路5,图中以虚线示出。多个导电通路6将电路5与沿芯片3周边的触片或焊片7连接起来。为将信号和电源加在芯片外线路与芯片上线路之间,芯片上的接触端或焊片7通过连接引线8与芯片外的接触端4连接。
图2示出集成或芯片上的平衡频率响应电路9和外部或芯片外平衡谐振电路10的一般电路图。点划线11表示芯片上线路与芯片外线路之间的分界面。频率响应电路9在图中以方框示出,它可包括任何多个需要另外的谐振电路来控制的平衡电路,例如(但不局限于)平衡射频振荡器、平衡变频器、平衡射频混频电路、平衡滤波电路等。
在本发明说明书的上下文中,“平衡”一词应理解为两信号接触端表示的电气特性相对于系统或网络的信号地线在某种程度上相等或对称的系统或网络,该电气特性的例子有例如阻抗和信号的大小。
频率响应电路9在芯片上的部分有第一和第二芯片上信号接触端12和13分别与第一和第二芯片外接触端14和15连接。参看图1,芯片上的接触端可包括焊片7,芯片外的接触端可包括接触端4。
谐振电路10的电容部分由电容C1和电容C2及C3组成,电容C1连接在芯片外接触端14和15之间。电容C2及C3的一端分别连接芯片外的接触端14或15,另一端接谐振电路的电感部分。该电感部分由串联连接的电感L1和L2组成,电感L1和L2又和电容C2和C3串联连接。L1和L2的串联连接中心点接电路的信号地线16,如图中所示。图中,信号地线16以三条短粗平行线表示。该电容和电感部分形成平衡并联谐振电路10。
在平衡振荡电路9的情况下,举例说,在其振荡频率下工作时,谐振电路或槽路10的阻抗中心都处于信号地线电位,任一接触端14、15及其中心之间的信号输出电压,其大小相等,相位相反。
本发明书的前序部分说过,封装集成电路,特别是应用在射频方面的封装集成电路的问题是由芯片的封装有关的内在电容和电感以及内外电路通过芯片上和芯片外接触端的耦合引起的。
图3是图2所示电路的简化集总元件等效电路图。电容Cp分别连接在芯片上的各接触端与信号地线之间,表示芯片上焊片7(图1)所形成的寄生电容。电感Lw表示连接引线8(图1)的寄生自感,电感Lt则表示封装件的引线框架和接触端(图1)的寄生自感。电感Lw和Lt串联连接在频率响应电路9的芯片上部分与芯片外连接的谐振电路10之间,如图中所示。
任何与焊片、连接引线和接触端有关的欧姆电阻以及与集成电路在印刷电路板上的安装有关的寄生电容和电感对理解本发明无关重要,因而在集总等效电路图中没有清楚展示出来。
从芯片上的频率响应电路9看,可以区分出三个不同的谐振环路17、18和19,如图4中所示。谐振环路17由谐振电路10即电容C1、C2和C3以及电感L1和L2构成。谐振环路18由电容Cp和Ci以及电感Lw和Lt构成。谐振环路19由电容Cq、C2和C3以及电感Lw、Lt、L1和L2构成。不难理解,谐振环路17表示电路所要求的频率响应,环路18和19则因内在封装电路和电感形成的。环路18和19引起的谐振通常在射频方面的应用中会产生不希望有的寄生谐振率的输出信号。因此,启动设计成振荡电路的频率响应电路9时,保证不了谐振电路会在哪一个频率下工作。
图5示出了本发明一个最佳实施例的一般电路图,该电路由集成或芯片上的平衡频率响应电路9和平衡谐振电路20组成,平衡谐振电路20则电容部分C1′、C2′和C3′以及电感部分L1′和L2′组成。点划线11表示芯片上线路与芯片外线路之间的界面。
与图2所示的现有技术的不同点在于,谐振电路电容部分的部件C1′是在芯片上连接在芯片上接触端12与13之间,谐振电路电容部分的其它部件C2′和C3′和电感部分L1′、L2′则在芯片外分别串联连接在第一和第二芯片外接触端14、15与信号地线之间。电感L1′、L2′和电容C2′和C3′与芯片上的电容C1′一起,形成平衡并联谐振电路20。
图6示出了本发明图5所示的电路的谐振环路图。内在电容Cp串联连接,再与谐振电路20的芯片上电容部分C1′并联连接。根据欧姆定律且假设集总等效电容Cp都相等,则总芯片上电容在电气上可用电容值等于C1和Cp电容值的和的一个集总电容代替。内在电感Lw和Lt与谐振电路20的芯片外部分(即电感L1′和L2′以及电容C2′和C3′)串联连接。根据欧姆定律,集总等效电感Lw、Lt以及电感L1′和L2′可用一个电感值等于Lw、Lt和L1′电感值和Lw、Lt和L2′电感值各自的和的一个电感代替。
如图6中所示,在本发明的上述实施例中只能区分出一个谐振环路21。因此,与图4所示的现有技术电路相比,频率响应电路9实质上在单一的谐振频率下工作而不致产生不希望有的寄生谐振频率的输出信号,这正符合本发明的目的。
为举例说明起见,在一个实施例中,本发明是在下列电容值和电感值的情况下工作的:C1′=1pF,C2′=C3′=4.7pF,L1′=L2′=3nH。在大约2GHz谐振频率下,Cp的电容值约等于0.2pF,Lw的电感值约为1nH,Lt约等于1.5nH。本技术领域的行家们都知道,设计计算芯片外谐振电路20的元件值时为使电路总的达到所要求或所希望有的频率响应,必须把有关的内在电容和电感值考虑进去。
图7a是图4所示现有技术集总等效谐振电路的阻抗值Z对频率f的模拟关系曲线图,图7b则是图6本发明的集总等效谐振电路的模拟且经测定证实了的阻抗值Z(即|Z|)对频率f的关系曲线图。电路的阻抗Z是指芯片上接触端处的阻抗值,各电路元件的元件值基本上如上述那样。频率f以对数尺度绘制,其范围为1至10GHz。这些曲线只是举例说明而已,因而都没有标出阻抗值。
图7a的现有技术曲线除示出了环路17(图4)所要求的在大约2GHz频率下的一次并联谐振(高阻抗值)外,还示出了主要由环路18(图4)引起的在大约6GHz频率下不希望有的二次并联谐振。在例如振荡电路的情况下,这可能会产生在大约GHz频率下的杂散输出谐振信号。本技术领域的行家们都知道与这类杂散输出谐振信号有关的问题。
然而,按照本发明,在1至10GHz的整个频率范围内只产生单一的在所要求的大约2GHz原频率下的谐振作用,从而使本发明的电路比起现有技术的电路优异得多,这一点很重要。
图8是本发明集成电路器件22的示意顶视图,器件的封装外壳2部分剖开以供举例说明。如图中所示,本发明是将分立电容器23配置在芯片3上,电连接在频率响应电路5芯片上部分的芯片上接触端12和13之间。电路5通过连接引线8分别连接芯片外的接触端14和15。
不然也可以不采用分立的电容器而采用与芯片3(即其半导体基片)形成一个整体的电容。
图9示出了本发明的芯片上的平衡振荡电路25与芯片外平衡谐振电路24耦合的原理电路图。点划线11表示芯片上部分与芯片外部分的界面。有源振荡部分由两个双极NPN晶体管26和27组成。晶体管26的基极端通过电容器28接晶体管27的集电极端。晶体管27的基极端通过电容器29接晶体管26的集电极端。晶体管26和27各自的发射极端通过串联电阻器30接恒流源31的一端,恒流源31的另一端接电路的信号地线。有源振荡部分主要由一个带正反馈的平衡导纳放大器组成,导纳级的集电极端之间耦合着一个无源平衡并联谐振电路。
按照本发明,电容器32在芯片上连接在晶体管26和27各自的集电极端之间,该两端又分别通过电感33和34接电路的电源端VDD。电容器35和36分别连接在VDD与信号地线之间,如图所示使谐振电路24形成完整的通路。电感33、34和电容器35、36可采用可调式的,从而形成可加以调谐的平衡振荡电路。
在启动的过程中,导纳放大器在其线性区工作,在集电极端之间形成过量的负电阻,使信号的幅值增加。然而,流过谐振电路24的电流受到恒流源31的限制。在稳态振荡过程中,输出信号的频率按本发明设计时得到保证和有一定的限制,这时环路的增益等于1,导纳级引来的负电阻等于谐振电路并联电阻的对应值。
在一个实施例中,采用了125欧的发射极电阻器30和1pF的正反馈电容器28和29。电流源31由三个按周知的方式连接的NPN晶体管(图中未示出)组成,形成一个恒流源。谐振电路24的电容器35和36采用所谓压控变电容,即压控可调电容器,例如西门子公司出品的BBY51-03W压控变电容。电感33和34都蚀刻在印刷电路板上使谐振电路可任意在印刷电路板上加以调谐。用这些压控变电容可以形成压控振荡(VCO)电路。
本技术领域的行家们都知道,振荡电路25的有源部分还可以采用PNP双极晶体管、MOS晶体管等,同时考虑到电路的供电而作出显而易见的改变。
不言而喻,芯片外的谐振部分可以包括分立的一般无源电容器和感应线圈以及半导体集成电容器和其它具电容作用的器件和线条式的传输器件或其它电感器,无论是无源式的还是用电子学的方法制成的都行。此外,芯片外谐振电路的多个电容器和电感器本身还可以由电容器和电感器网路组成,但仍然保留本发明单一谐振环路的原理。
此外,不难理解,通过将设计得使其具有若干谐振频率的外部谐振电路连接到本发明芯片上的频率响应器件,本发明所述和要求保护的单一谐振环路原理可适用于谐振电路的各个分立的谐振环路。
图10示出了本发明的平衡振荡电路在收发信机半导体器件37中的典型应用。器件37即所谓专用集成电路(ASIC),由平衡收信部分38、平衡发信部分39和平衡振荡电路40组成。
收信部分38的平衡低噪输入放大器43具信号输入端44、45和信号输出端46、47,后者接由两个平衡混频器48和49组成的正交网络的输入端,而平衡混频器48和49的输出端分别接平衡移相器50、51。该相器50、51的输出馈给加法电路52,在电路37的输出端53提供接收到的信号。
发送部分39的平衡输出放大器54具输出端55和56和输入端57和58,后者接平衡加法电路59的输出端。发送部分39还有由平衡移相器60组成的正交网络,平衡移相器60的输入端接中频(IF)VCO(压控振荡器)电路61,中频VCO电路61的输入端62、63接收待发送的调制器输出信号。移相器60的输出端分别接平衡混频器64和65的输入端。两混频器的输出信号都馈给加法电路59。
收发信机37按周知的外差原理工作,需要有本机振荡器(LO)信号。LO信号由振荡电路40提供。芯片外谐振电路待连接到振荡电路40的接触端41、42的电容部分按本发明是用电容器66示出的,该电容器业已安置在收发信机37的半导体基片上。
振荡电路40的输出端接平衡移相器67,平衡移相器67的输出端接混频器48、49和64、65相应的输入端,如图中所示。
在一个实施例中,器件37设计成与无线电基地台和/或遥控无线电通信终端[例如按数字增强无塞绳电信(DECT)标工作的无线电电话送收话器]配合使用。振荡器40作为VCO在1.8GHz的中心频率下工作。
Claims (8)
1.一种平衡频率响应电路,其各电路元件在半导芯片上形成,芯片的第一和第二芯片上的接触端分别连接第一和第二芯片外的接触端,所述接触端与一个平衡谐振电路耦合,其中所述谐振电路由电容部分和电感部分组成,其特征在于,所述电容部分在芯片上连接在所述第一和第二芯片上的接触端,所述电容部分的另一部分在芯片外串联连接在所述第一和第二芯片外的接触端之间,从而使所述芯片上和芯片外连接的谐振部分形成在单谐振环路中含所述各接触端的平衡并联谐振电路。
2.如权利要求1所述的频率响应电路,其特征在于,所述芯片外连接的电容部分的第一部分和所述电感部分的第一部分串联连接在所述第一芯片外的接触端与电路的信号地线之间,且所述芯片外连接的电容部分的第二部分与所述电感部分的第二部分串联连接在所述芯片外的接触端与电路信号地线之间。
3.如权利要求1或2所述的频率响应电路,其特征在于,所述芯片外连接的部分有一个可调的电容和/或电感部分。
4.如权利要求1或2所述的频率响应电路,其特征在于,所述芯片上连接的电容部分一个与所述半导体芯片形成一个整体的电容部分。
5.如权利要求1或2所述的频率响应电路,其特征在于,所述集成电路元件设计得使其构成一个平衡振荡电路。
6.如权利要求5所述的频率响应电路,其特征在于,所述振荡电路由第一和第二同导电类型的双极晶体管组成,其发射极端经串联电阻接集成电流源,其集电极端与基极端容性交叉耦合,且所述集电极端分别接所述第一和第二芯片上接触端。
7.如权利要求6所述的频率响应电路,其特征在于,所述集成电路元件配置得使其形成一个收发信电路,其混频电路耦合到所述振荡电路,振荡电路形成所述混频电路的本机振荡电路。
8.根据权利要求1或2所述的频率响应电路,特征在于,所述半导体芯片形成在一个集成半导体器件中,它具有第一和第二芯片外的接触端,供连接由电容部分和电感部分组成的平衡谐振电路,从而通过将所述电容部分的另一部分和所述电感部分串联连接在所述第一与第二芯片外的接触端之间形成一个平衡并联谐振电路,其在单一谐振环路中包括所述接触端。
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US6020616A (en) * | 1998-03-31 | 2000-02-01 | Vlsi Technology, Inc. | Automated design of on-chip capacitive structures for suppressing inductive noise |
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CN100530620C (zh) * | 2005-01-24 | 2009-08-19 | 三洋电机株式会社 | 半导体装置 |
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1996
- 1996-01-22 EP EP96200152A patent/EP0785616B1/en not_active Expired - Lifetime
- 1996-01-22 DE DE69620859T patent/DE69620859T2/de not_active Expired - Lifetime
- 1996-01-22 ES ES96200152T patent/ES2173245T3/es not_active Expired - Lifetime
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1997
- 1997-01-20 CA CA002195493A patent/CA2195493C/en not_active Expired - Lifetime
- 1997-01-20 TW TW086100558A patent/TW365702B/zh not_active IP Right Cessation
- 1997-01-21 US US08/787,527 patent/US5844301A/en not_active Expired - Lifetime
- 1997-01-21 CN CN97102318A patent/CN1105416C/zh not_active Expired - Lifetime
- 1997-01-21 JP JP9008329A patent/JPH1065442A/ja active Pending
- 1997-01-21 KR KR1019970001588A patent/KR100303176B1/ko not_active IP Right Cessation
-
1998
- 1998-02-19 HK HK98101301A patent/HK1002301A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
ES2173245T3 (es) | 2002-10-16 |
DE69620859D1 (de) | 2002-05-29 |
CA2195493A1 (en) | 1997-07-23 |
JPH1065442A (ja) | 1998-03-06 |
KR100303176B1 (ko) | 2001-11-22 |
DE69620859T2 (de) | 2002-10-31 |
US5844301A (en) | 1998-12-01 |
TW365702B (en) | 1999-08-01 |
EP0785616B1 (en) | 2002-04-24 |
EP0785616A1 (en) | 1997-07-23 |
CA2195493C (en) | 2005-04-12 |
CN1163511A (zh) | 1997-10-29 |
HK1002301A1 (en) | 1998-08-14 |
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