CN110476240B - 用于高密度2.5d和3d集成的互连方法 - Google Patents

用于高密度2.5d和3d集成的互连方法 Download PDF

Info

Publication number
CN110476240B
CN110476240B CN201880022465.3A CN201880022465A CN110476240B CN 110476240 B CN110476240 B CN 110476240B CN 201880022465 A CN201880022465 A CN 201880022465A CN 110476240 B CN110476240 B CN 110476240B
Authority
CN
China
Prior art keywords
metal layer
die
layer
anodic
cathodic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880022465.3A
Other languages
English (en)
Chinese (zh)
Other versions
CN110476240A (zh
Inventor
J·S·甘地
S·瑞玛林嘉
H·刘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of CN110476240A publication Critical patent/CN110476240A/zh
Application granted granted Critical
Publication of CN110476240B publication Critical patent/CN110476240B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs
    • H10W70/635Through-vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66Conductive materials thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251Changing the shapes of bumps
    • H10W72/01253Changing the shapes of bumps by etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251Changing the shapes of bumps
    • H10W72/01255Changing the shapes of bumps by using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01931Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01951Changing the shapes of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01951Changing the shapes of bond pads
    • H10W72/01953Changing the shapes of bond pads by etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00Direct bonding of chips, wafers or substrates
    • H10W80/301Bonding techniques, e.g. hybrid bonding
    • H10W80/314Bonding techniques, e.g. hybrid bonding characterized by direct bonding of pads or other interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/297Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
CN201880022465.3A 2017-03-29 2018-03-28 用于高密度2.5d和3d集成的互连方法 Active CN110476240B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/473,294 US10593638B2 (en) 2017-03-29 2017-03-29 Methods of interconnect for high density 2.5D and 3D integration
US15/473,294 2017-03-29
PCT/US2018/024778 WO2018183453A1 (en) 2017-03-29 2018-03-28 Methods of interconnect for high density 2.5d and 3d integration

Publications (2)

Publication Number Publication Date
CN110476240A CN110476240A (zh) 2019-11-19
CN110476240B true CN110476240B (zh) 2023-10-20

Family

ID=62002720

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880022465.3A Active CN110476240B (zh) 2017-03-29 2018-03-28 用于高密度2.5d和3d集成的互连方法

Country Status (6)

Country Link
US (1) US10593638B2 (https=)
EP (1) EP3580779B1 (https=)
JP (1) JP7145169B2 (https=)
KR (1) KR102496142B1 (https=)
CN (1) CN110476240B (https=)
WO (1) WO2018183453A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10943791B2 (en) * 2018-10-31 2021-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Pattern formation method and method for manufacturing a semiconductor device
US11658122B2 (en) 2019-03-18 2023-05-23 Intel Corporation EMIB patch on glass laminate substrate
US11211378B2 (en) * 2019-07-18 2021-12-28 International Business Machines Corporation Heterogeneous integration structure for artificial intelligence computing
KR20240165937A (ko) 2022-03-24 2024-11-25 미쯔비시 가스 케미칼 컴파니, 인코포레이티드 구리 표면 보호용 조성물, 그리고 이것을 이용한 반도체 중간체 및 반도체의 제조방법
CN117525061A (zh) * 2022-07-25 2024-02-06 矽磐微电子(重庆)有限公司 扇出型系统级封装结构及其制作方法
CN115732407B (zh) * 2022-12-06 2026-04-24 通富微电子股份有限公司 分散硅中介芯片封装方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218281B1 (en) * 1997-12-26 2001-04-17 Fujitsu Limited Semiconductor device with flip chip bonding pads and manufacture thereof
CN102005397A (zh) * 2009-08-31 2011-04-06 中芯国际集成电路制造(上海)有限公司 提高芯片键合块抗腐蚀性的方法
CN103035604A (zh) * 2012-12-17 2013-04-10 矽力杰半导体技术(杭州)有限公司 一种倒装芯片封装结构及其制作工艺

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3452795B2 (ja) * 1997-05-07 2003-09-29 東京エレクトロン株式会社 塗布膜形成方法および塗布装置
US6190940B1 (en) * 1999-01-21 2001-02-20 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
US6703069B1 (en) * 2002-09-30 2004-03-09 Intel Corporation Under bump metallurgy for lead-tin bump over copper pad
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
US20050003650A1 (en) * 2003-07-02 2005-01-06 Shriram Ramanathan Three-dimensional stacked substrate arrangements
US6979647B2 (en) * 2003-09-02 2005-12-27 Texas Instruments Incorporated Method for chemical etch control of noble metals in the presence of less noble metals
JP3794403B2 (ja) * 2003-10-09 2006-07-05 セイコーエプソン株式会社 半導体装置
JP2006179570A (ja) * 2004-12-21 2006-07-06 Renesas Technology Corp 半導体装置の製造方法
US7402509B2 (en) * 2005-03-16 2008-07-22 Intel Corporation Method of forming self-passivating interconnects and resulting devices
KR101534682B1 (ko) * 2009-03-13 2015-07-08 삼성전자주식회사 범프에 스틱을 구비하는 반도체 장치
US8841766B2 (en) * 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8993431B2 (en) * 2010-05-12 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating bump structure
US9048135B2 (en) * 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
US8598030B2 (en) * 2010-08-12 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making conductive post with footing profile
US10128206B2 (en) * 2010-10-14 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure
CN102569171B (zh) * 2010-11-18 2015-02-04 精材科技股份有限公司 改善冠状缺陷的线路结构及其制作方法
US8242011B2 (en) * 2011-01-11 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming metal pillar
JP6118816B2 (ja) * 2012-11-16 2017-04-19 日立オートモティブシステムズ株式会社 接合部材、単電池および組電池
KR20140130915A (ko) 2013-05-02 2014-11-12 삼성전자주식회사 범프를 갖는 반도체 소자를 제조하는 방법
US9412709B2 (en) 2013-05-21 2016-08-09 Freescale Semiconductor, Inc. Semiconductor structure with sacrificial anode and passivation layer and method for forming
KR102192195B1 (ko) * 2014-07-28 2020-12-17 삼성전자주식회사 솔더 조인트를 갖는 반도체 소자 및 그 형성 방법
KR102245825B1 (ko) * 2014-09-04 2021-04-30 삼성전자주식회사 반도체 패키지
US9496238B2 (en) * 2015-02-13 2016-11-15 Advanced Semiconductor Engineering, Inc. Sloped bonding structure for semiconductor package
US20170051426A1 (en) * 2015-08-19 2017-02-23 Apple Inc. Processes to avoid anodic oxide delamination of anodized high strength aluminum alloys
US10181448B2 (en) * 2016-03-22 2019-01-15 Advanced Semiconductor Engineering, Inc. Semiconductor devices and semiconductor packages
US9859258B2 (en) * 2016-05-17 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10020281B2 (en) * 2016-08-30 2018-07-10 International Business Machines Corporation Metal bonding pads for packaging applications
DE102016119485A1 (de) * 2016-10-12 2018-04-12 Infineon Technologies Ag Chipträger mit elektrisch leitfähiger Schicht, die sich über eine wärmeleitfähige dielektrische Sheet-Struktur hinaus erstreckt

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218281B1 (en) * 1997-12-26 2001-04-17 Fujitsu Limited Semiconductor device with flip chip bonding pads and manufacture thereof
CN102005397A (zh) * 2009-08-31 2011-04-06 中芯国际集成电路制造(上海)有限公司 提高芯片键合块抗腐蚀性的方法
CN103035604A (zh) * 2012-12-17 2013-04-10 矽力杰半导体技术(杭州)有限公司 一种倒装芯片封装结构及其制作工艺

Also Published As

Publication number Publication date
WO2018183453A1 (en) 2018-10-04
US20180286826A1 (en) 2018-10-04
JP2020512703A (ja) 2020-04-23
KR102496142B1 (ko) 2023-02-03
CN110476240A (zh) 2019-11-19
EP3580779B1 (en) 2021-09-01
US10593638B2 (en) 2020-03-17
JP7145169B2 (ja) 2022-09-30
KR20190132478A (ko) 2019-11-27
EP3580779A1 (en) 2019-12-18

Similar Documents

Publication Publication Date Title
CN110476240B (zh) 用于高密度2.5d和3d集成的互连方法
US12283549B2 (en) High density interconnection using fanout interposer chiplet
KR102650296B1 (ko) 범프 구조물을 갖는 반도체 디바이스 및 반도체 디바이스의 제조 방법
CN103187380B (zh) 具有穿基板通路的半导体装置
US20200303212A1 (en) Semiconductor device and manufacturing method thereof
KR101368538B1 (ko) 멀티칩 웨이퍼 레벨 패키지
US8884431B2 (en) Packaging methods and structures for semiconductor devices
KR101515276B1 (ko) 3차원 집적 회로를 제조하는 방법
TWI499002B (zh) 封裝元件與其製法
US20130040423A1 (en) Method of Multi-Chip Wafer Level Packaging
TW201104797A (en) Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US11791326B2 (en) Memory and logic chip stack with a translator chip
CN107408515A (zh) 具有用于晶片与晶片互连的桥接模块的半导体组件
Chai et al. Development of Large Die Fine-Pitch Cu/Low-$ k $ FCBGA Package With Through Silicon via (TSV) Interposer
CN113643994A (zh) 用于凸块下金属结构的套环及相关联的系统及方法
CN114121836A (zh) 封装结构、半导体器件及其制造方法
US9136237B2 (en) Electroplated solder for high-temperature interconnect
TW201232730A (en) Stackable package by using internal stacking modules
US20190096850A1 (en) Stacked package structure and manufacturing method thereof
TW201225209A (en) Semiconductor device and method of confining conductive bump material with solder mask patch
Kim et al. From 3D-IC to 3D-HI for environmentally durable rugged electronics (EnDuRE)
Lau et al. Solder Joints in PCB Assembly and Semiconductor Packaging
Solberg 2.5 D and 3D semiconductor package technology: Evolution and innovation
Wu et al. Thermal stress and creep strain analyses of a 3D IC integration SiP with passive interposer for network system application

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TG01 Patent term adjustment

Free format text: NEW EXPIRY DATE: 20380418

TG01 Patent term adjustment