JP7145169B2 - 高密度２．５ｄおよび３ｄ集積のための相互接続の方法 - Google Patents

高密度２．５ｄおよび３ｄ集積のための相互接続の方法 Download PDF

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JP7145169B2
JP7145169B2 JP2019553500A JP2019553500A JP7145169B2 JP 7145169 B2 JP7145169 B2 JP 7145169B2 JP 2019553500 A JP2019553500 A JP 2019553500A JP 2019553500 A JP2019553500 A JP 2019553500A JP 7145169 B2 JP7145169 B2 JP 7145169B2
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metal layer
anode
cathode
anode metal
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ガンディー，ジャスプリート・シング
ラマリンガム，スレッシュ
リウ，ヘンリー
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Xilinx Inc
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
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    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01253—Changing the shapes of bumps by etching
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    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
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    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938—Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
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    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W80/00—Direct bonding of chips, wafers or substrates
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    • H10W80/314—Bonding techniques, e.g. hybrid bonding characterized by direct bonding of pads or other interconnections
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
JP2019553500A 2017-03-29 2018-03-28 高密度２．５ｄおよび３ｄ集積のための相互接続の方法 Active JP7145169B2 (ja)

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US15/473,294 US10593638B2 (en) 2017-03-29 2017-03-29 Methods of interconnect for high density 2.5D and 3D integration
US15/473,294 2017-03-29
PCT/US2018/024778 WO2018183453A1 (en) 2017-03-29 2018-03-28 Methods of interconnect for high density 2.5d and 3d integration

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JP2020512703A JP2020512703A (ja) 2020-04-23
JP2020512703A5 JP2020512703A5 (https=) 2021-02-18
JP7145169B2 true JP7145169B2 (ja) 2022-09-30

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EP (1) EP3580779B1 (https=)
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CN117525061A (zh) * 2022-07-25 2024-02-06 矽磐微电子(重庆)有限公司 扇出型系统级封装结构及其制作方法
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WO2018183453A1 (en) 2018-10-04
US20180286826A1 (en) 2018-10-04
JP2020512703A (ja) 2020-04-23
KR102496142B1 (ko) 2023-02-03
CN110476240A (zh) 2019-11-19
CN110476240B (zh) 2023-10-20
EP3580779B1 (en) 2021-09-01
US10593638B2 (en) 2020-03-17
KR20190132478A (ko) 2019-11-27
EP3580779A1 (en) 2019-12-18

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