CN103187380B - 具有穿基板通路的半导体装置 - Google Patents

具有穿基板通路的半导体装置 Download PDF

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Publication number
CN103187380B
CN103187380B CN201210593062.9A CN201210593062A CN103187380B CN 103187380 B CN103187380 B CN 103187380B CN 201210593062 A CN201210593062 A CN 201210593062A CN 103187380 B CN103187380 B CN 103187380B
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semiconductor crystal
crystal wafer
wafer
solder bump
conductive
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CN103187380A (zh
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A·V·萨莫伊洛夫
T·帕伦特
L·Y·王
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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Abstract

半导体装置描述为包括仅部分地穿入基板延伸的通路。穿基板通路（TSV）向形成于基板中的电子器件提供电互连。在实施例中，通过首先用粘合材料将半导体晶圆粘合到载体晶圆来制造半导体装置。所述半导体晶圆包括布置在晶圆内（例如，在晶圆的第一表面和第二表面之间）的蚀刻阻止部。穿入晶圆形成一个或多个通路。所述通路从第二表面延伸到蚀刻阻止部。

Description

具有穿基板通路的半导体装置
技术领域
本发明涉及一种具有穿基板通路的半导体装置。
背景技术
消费电子装置，特别是例如智能电话、平板电脑等的移动电子装置，越来越多地采用更小、更紧凑的器件来提供用户期望的功能。这种装置经常采用三维集成电路装置（3DIC）。三维集成电路装置是采用两层或多层有源电子器件的半导体装置。穿基板通路（TSV）使装置的不同层（例如，不同基板）上的电子器件互相连接，以允许该装置在竖向和横向上同样地集成。因此，与传统的二维集成电路装置相比，三维集成电路装置能够以更小、更紧凑的基底面提供增强的功能。
发明内容
半导体装置描述为包括仅部分地穿入基板延伸的通路。可以为穿基板通路（TSV）的通路向形成于基板中的电子器件提供电互连。在实施例中，通过首先用粘合材料将半导体晶圆粘合到载体晶圆以在后续制造步骤中为半导体晶圆提供机械支撑来制造半导体装置。所述半导体晶圆包括布置在晶圆内（例如，在晶圆的第一表面和第二表面之间）的蚀刻阻止部。穿入晶圆形成一个或多个通路。所述通路从第二表面延伸到蚀刻阻止部。
本发明内容被提供用于以简化的形式介绍发明思想的选择，该发明思想的选择将在下面的具体实施方式中进一步描述。本发明内容不意图确定所要求保护的主题的关键特征或重要特征，也不意图用于帮助确定所要求保护的主题的范围。
附图说明
具体实施方式参考附图来描述。在描述和附图中，相同的附图标记在不同的实例中可用于表示相应或相同的物件。
图1是示出了根据本公开的一个示例性实施例的半导体装置的图解性的局部剖视图，所述半导体装置具有一个或多个通路。
图2A和2B是示出了用于制造具有一个或多个通路的半导体装置的过程的一个示例性实施例的流程图，所述半导体装置例如为图1中示出的装置。
图3A至3F是示出了根据图2中示出的过程来制造具有一个或多个通路的半导体装置的图解性的局部剖视图，所述半导体装置例如为图1中示出的装置。
具体实施方式
概述
穿硅通路（TSV）是用于提供三维（3D）集成电路装置的竖向电互连。例如，集成电路裸片可在硅晶圆上方堆叠。通过将集成电路裸片与在硅晶圆中形成的集成电路互连，所述集成电路裸片与硅晶圆中的集成电路成为单一的装置。在一个实施例中，TSV可完全地穿透基板（晶圆或裸片）延伸，从而在形成于基板中的集成电路装置和与该集成电路装置相关的其它器件（例如，集成电路裸片）之间提供电互连。
因此，描述了晶圆级封装技术来允许将多个裸片封装为单一的晶圆级封装装置。半导体装置包括部分地穿入该装置的基板延伸的通路，以允许在半导体装置的表面附近附加的布线。在一个或多个实施例中，半导体装置的制造首先是用粘接材料将半导体晶圆粘合到载体晶圆上。所述半导体晶圆包括布置在晶圆内（例如，在晶圆的第一表面和第二表面之间）的蚀刻阻止部。于是，一个或多个通路穿入晶圆从晶圆的第二表面附近延伸至蚀刻阻止部而形成。在一个或多个实施例中，集成电路裸片布置在晶圆的第二表面上方。封装结构可形成于第二表面上方，以至少大体上封装集成电路裸片。加强结构可形成于封装结构上，以向所述装置提供机械支撑。在一个实施例中，加强结构可由四二（42）合金合成物制造。
在下述讨论中，首先描述了示例性半导体装置。然后描述可用来制造该示例性半导体装置的示例性工序。
示例性实施例
图1示出了根据本公开的示例性实施例的半导体装置100。如图所示，半导体装置100包括基板102（例如，半导体晶圆的一部分）。所述基板102包括对准标记104，所述对准标记104在半导体制造过程中用于对准所述基板102。所述基板102还包括第一表面106和第二表面108。
基板102包括基材，所述基材被用来通过例如光刻、离子注入、沉积、蚀刻等多种制造技术形成集成电路装置110。基板102可以多种方式构造。例如，基板102可包括n型硅晶圆或p型硅晶圆。在一个实施例中，基板102可包括被构造为提供n型电荷载体元素的V族元素（例如，磷、砷、锑等）。在另一实施例中，基板102可包括被构造为提供p型电荷载体元素的IIIV族元素（例如，硼等）。
集成电路装置110可以多种方式构造。例如，集成电路装置110可以是数字集成电路装置、模拟集成电路装置、混合信号电路装置等。在实施例中，集成电路装置可包括数字逻辑装置、模拟装置（例如，放大器等）、它们的组合等。如上所述，可利用多种制造技术（例如，前道工序（FEOL）制造技术）来制造集成电路装置110。例如，可通过互补金属氧化物半导体（CMOS）技术、双极半导体技术等来制造集成电路装置110。
如图1所示，装置100还包括导电层112。在一个实施例中，导电层112可包括导电（例如，接触）垫、再分布结构等。在另一实施例中，导电层112可包括允许镀内衬（plated-line）形成的籽晶金属层和/或阻挡金属层。导电层112的数量和构造可根据集成电路装置110的复杂度和构造等而变化。导电层112可提供电互连，通过所述电互连使集成电路装置110和与装置100相关的其它电子器件或布置在装置100内的其它集成电路装置110互连，所述其它电子器件例如是印刷电路板。在实施例中，导电层112可由例如金属材料（例如，铝、铜等）等的导电材料构成。
如上所述，导电层112在多种与装置100相关的电器件之间提供电互连。例如，布置在第二表面108上方的第一导电层112可提供集成电路装置110和焊锡凸块114之间的电互连。焊锡凸块114和微焊锡凸块115被设置用来在导电层112和形成于印刷电路板的表面上的对应的垫之间提供机械和/或电互连。在一个实施例中，焊锡凸块114和微焊锡凸块115可由无铅焊料制造，所述无铅焊料例如是锡-银-铜(Sn-Ag-Cu)合金焊料（即，SAC）、锡-银（Sn-Ag）合金焊料、锡-铜（Sn-Cu）合金焊料等。然而，可想到使用锡-铅（PbSn）焊料。如图1所示，微焊锡凸块115的第一阵列113布置在装置100的第一表面106上方，且焊锡凸块114的第二阵列117布置在装置100的第二表面108上方。
凸块接口116可施加于导电层112，以在导电层112和焊锡凸块114之间提供可靠的互连边界。例如，在图1中示出的半导体装置100中，凸块接口116包括施加于基板102的导电层112的凸块下金属化部（UBM）118。所述UBM118可具有多种组分。例如，UBM118包括多个不同的金属（例如，铝（Al）、镍（Ni）、铜（Cu）等）层，所述金属层起着粘接层、扩散阻挡层、可焊层、氧化阻挡层等的作用。然而，也可有其它UBM结构。在另一实施例中，凸块接口116可包括铜柱等。
在实施例中，装置100可采用在再分布层（“RDL”）构造中实施的导电层112。所述RDL构造采用再分布结构120，所述再分布结构120包括薄膜金属（例如，铝、铜等）重布线和互连系统，所述系统将导电层112再分布为凸块接口116的区域阵列（例如，UBM垫），所述区域阵列可更均匀地布置在装置100的表面上。如图1所示，装置100还可包括布置在第一表面106上的RDL结构121，以进一步向与装置100相关的器件（例如，集成电路装置110、TSV等）提供电互连功能。
焊锡凸块114和微焊锡凸块115随后放置在这些凸块接口116上而分别形成凸块组件122和凸块组件123。因此，一起看来，焊锡凸块114、微焊锡凸块115和相关的凸块接口116（例如，UBM118、铜柱等）分别组成凸块组件122、123，所述凸块组件122、123被构造为提供集成电路装置110至例如印刷电路板或另一裸片（如这里描述的）的其它电子装置的机械和/或电互连。
虽然图1示出的装置100采用了再分布层（“RDL”）构造，但也可想到，这里示出和描述的装置100也可采用直接撞击垫（Bump-On-Pad，“BOP”）构造。BOP构造可采用布置在凸块接口116（例如，UBM垫）下方的导电层112。
导电垫124、126（例如，导电层112）可布置在基板102中。如图1所示，导电垫124布置在基板102内，且导电垫126接近表面108布置。在一些实施例中，导电垫126布置在基板102的表面上。导电垫124、126可以多种方式构造。在一个示例中，导电垫124、126可由铝构成。在另一示例中，导电垫124、126可由铜构成。然而，其它示例也是可行的。
如图1所示，穿基板通路（TSV）128从表面106延伸到导电垫124。因此，导电垫124可被构造为在穿硅通路128（TSV）的形成过程中起蚀刻阻止部125的作用。在一个或多个实施例中，蚀刻阻止部125可包括金属1层、金属2层、金属3层、金属4层等。导电垫124也被用来在TSV128（所述TSV128被连接于凸块组件122的第一阵列113的焊锡凸块114）和其它相关的电子器件（例如，集成电路装置110）之间提供电互连功能。如图所示，TSV128没有延伸基板102的整个深度（D）（例如，TSV128仅部分地穿基板102延伸）。例如，在一个示例中，TSV128可具有大约五十微米（50um）至大约一百微米（100um）的深度，而基板102的深度（D）是大约六十五微米（65um）至大约一百二十微米（120um）。然而，可想到，在其它示例性实施例中，TSV128的深度和基板102的深度可根据不同的应用而变化。这样，由于TSV128没有延伸基板102的整个深度而产生的附加的空间，可接近基板102的第二表面108布置附加的布线（例如，附加的RDL结构120）和/或附加的集成电路装置（例如，集成电路装置110）。TSV128可以多种方式构造。例如，在一个特定的示例中，TSV128可具有范围从四比一（4:1）至十比一（10:1）的纵横比。在实施例中，导电垫124可包括例如铜、铝等的金属层。
图1还示出了电介质层127（例如，夹层），所述电介质层127布置在导电垫124之上，且至少基本上延展基板102的宽度。如图所示，电介质层127接近（例如，邻近或在之上）导电垫（蚀刻阻止部125）定位。电介质层127可被用来减慢TSV128的蚀刻速度。例如，在制造步骤中，可形成第一TSV128和第二TSV128。然而，（第一TSV128的）第一蚀刻速度可快于（例如，大于）（第二TSV128的）第二蚀刻速度。因此，电介质层127可用来减慢第一蚀刻速度，使得第二蚀刻速度近似等于第一蚀刻速度（例如，当蚀刻材料遇到蚀刻阻止部时，蚀刻速度可近似相等）。在一个或多个实施例中，电介质层127可包括由以下至少一种构成的多个层：氮化硅、掺磷氧化硅或无掺杂的氧化硅。
如图1所示，导电垫126靠近（例如，在上方）第二表面108布置，且被用来在RDL结构120和装置100的其它电子器件之间提供电互连功能。在一个实施例中，导电垫126可布置在基板102的表面上方。导电垫126可在RDL结构120和集成电路装置110之间提供电互连，所述集成电路装置110布置在导电垫124（蚀刻阻止部125）和导电垫126之间。
如上所述，穿硅通路128（TSV）部分地穿入基板102延伸到至少一个导电层112，所述导电层112例如是基板102的蚀刻阻止部125。例如，TSV128被示为布置在基板102内，且延伸到蚀刻阻止部125。因此，在一个实施例中，所述TSV128没有穿过基板102延伸（例如，TSV128没有从表面106延伸到表面108）。如图1所示，TSV128包括导电材料130，所述导电材料130在基板102的第一导电层112（例如，导电垫124）和凸块组件123的第一阵列113的焊锡凸块114之间提供电互连。导电材料130穿TSV128竖直地延伸，且在第一表面106上水平地延伸。导电材料130在第一表面106上水平地延伸的部分起着RDL结构121的作用。例如，导电材料130可在集成电路装置110和焊锡凸块114之间提供电互连。在一个实施例中，导电材料130可由例如铜等的金属材料组成。
TSV128包括绝缘内衬132，以使布置在TSV128中的导电材料130与上部晶圆104电隔离。因此，绝缘内衬132被用来防止导电材料130与基板102之间的短路。如图1所示，绝缘内衬132被沉积到TSV128中，使得内衬132至少基本上衬填TSV128。绝缘内衬132可以多种方式构造。例如，绝缘内衬132可以是绝缘材料，所述绝缘材料例如是氧化物材料（SiO2）、氮化物材料、它们的组合等。绝缘内衬132通过以下方式形成：使绝缘材料沉积在TSV128中，然后蚀刻掉TSV128的底部处的所述绝缘材料，同时保存沿TSV128侧面的绝缘内衬132。在一个或多个实施例中，绝缘材料的沉积可通过等离子体增强化学气相沉积（PECVD）技术实现，然后非均质地向下蚀刻所述绝缘材料到导电垫124，从而形成内衬132。
凸块组件123的第一阵列113可与集成电路裸片134形成电接触，以将片上系统（SoC）功能延伸到装置100。例如，集成电路裸片134可包括数字电路、模拟电路或混合信号电路。
附加地，如图1所示，装置100包括布置在第一表面106上的聚合物层136，以向凸块组件123的第一阵列113提供稳定性。在一个或多个实施例中，可利用低温聚苯并二恶唑类聚合物（PBO）过程在第一表面106上形成聚合物层136。所述低温PBO过程可发生的温度范围在大约一百五十摄氏度（150℃）到大约二百摄氏度（200℃）。在一个实施例中，低温PBO过程可发生于大约一百七十五摄氏度（175℃）的温度下。低温PBO过程被用来在不损害已经完成的制造步骤（集成电路装置110、临时粘合层（见图3C中的临时粘合层322））的情况下形成聚合物层136。
封装结构138布置在聚合物层136上，以提供支撑且至少基本上将集成电路裸片134保持在位。如图1所示，封装结构可至少基本上封装集成电路裸片134。在一个或多个实施例中，封装结构138可由合适的模制合成物等组成。
如图1所示，装置100还包括布置在封装结构138上的加强结构140，以向装置100提供机械支撑。加强结构140的热膨胀率（CET）可与装置100（例如，基板102等）的CET相当。因此，加强结构140可以多种方式构造。例如，加强结构140可由硅材料构成，所述硅材料的CET与装置100的CET相当。在另一示例中，加强结构140可由金属合成物组成，所述金属合成物的CET与装置100的CET相当。在一个实施例中，所述金属材料可以是四二（42）合金合成物（例如，镍铁（Ni-Fe）合金）等。
半导体装置100还包括第一和第二聚合物层142、144，以向所述一个或多个导电层112（例如，RDL结构120、导电垫126）提供隔离。例如，可利用聚合物层142、144使所述一个或多个导电层112与后续处理步骤隔离。在一个实施例中，可通过低温PBO过程等形成聚合物层142、144。
示例性制造过程
图2A和2B示出了采用晶圆级封装技术来制造半导体装置的示例性过程200，所述半导体装置例如是图1中示出的半导体装置100。图3A至3F示出了可被用来制造半导体装置300（例如图1中示出的半导体装置100）的示例晶圆的各个阶段。半导体晶圆、例如3A中示出的晶圆302包括第一表面304和第二表面306。晶圆302还包括一个或多个通过FEOL制造技术形成的集成电路装置308。例如，可通过互补金属-氧化物-半导体（CMOS）技术、双极半导体技术等来制造集成电路装置308。在一个或多个实施例中，集成电路装置308可包括数字逻辑装置、模拟装置（例如，放大器等）、它们的组合等。
如图3A所示，装置300还包括多个导电层310。导电层310包括第一（例如，如图3A所示的最上的垫）导电垫312和第二（例如，如图3A所示的最下的垫）导电垫314。在一个或多个实施例中，导电垫312、314可以是铝等。如图所示，第一导电垫312布置在第一表面304上，并且第二导电垫314布置在晶圆302内，以在形成一个或多个TSV（这里所述的）的过程中起蚀刻阻止部（例如，蚀刻阻止部315）的作用。如图所示，第二导电垫314接近（例如，邻近或靠近）电介质层316布置，电介质层316被构造为在TSV的形成过程中控制一个或多个蚀刻速度。例如，第一TSV的第一蚀刻速度可快于（例如，大于）第二TSV的第二蚀刻速度。因此，电介质层316可用于减慢第一蚀刻速度，从而使第二蚀刻速度大于等于如上所述的第一蚀刻速度。电介质层316还可包括扩散阻挡材料（例如，氮化硅、碳化硅等），以防止通过FEOL制造技术形成的集成电路装置308受到金属化和夹层电介质沉积过程中引入的污染。装置300还可包括对准标记318，以在后续制造过程中（例如，粘合于载体晶圆、形成TSV等）对准晶圆302。在一个实施例中，可利用可见光线和/或红外光线对准技术来对准晶圆302。
如图2A所示，载体晶圆被粘合到半导体晶圆上（框202）。如图3A所示，钝化层320布置在第一导电垫312的第一表面304上。钝化层320首先至少基本上封装导电垫312，然后钝化层320被选择性地蚀刻成至少部分地露出导电垫312。合适的临时粘合层322沉积在钝化层320上，以允许载体晶圆324被粘合于半导体晶圆302。在一个实施例中，载体晶圆324可以是硅晶圆等。
然后，半导体晶圆接受合适的背磨过程（框204）。如图3B所示，晶圆302的第二表面306接受背磨过程而使晶圆302变薄。于是在半导体晶圆的第二表面上形成硬掩膜层（框206）。硬掩膜层326形成于表面306上，用于在TSV的形成过程中保护晶圆302的多个部分（见图3B）。在一个实施例中，硬掩膜层326可由双氧化物-氮化物硬掩膜等构成。
然后，一个或多个TSV在半导体晶圆内形成（框208）。所述TSV可通过蚀刻半导体晶圆中的TSV区域而形成（框210）。例如，在硬掩膜层326上形成光阻层。通过选择性地图案化和蚀刻光阻层区域（例如，光阻层的未露出区域）而形成TSV区域328，从而开始TSV330的形成。如图3C所示，TSV330从第二表面306附近延伸到第二导电垫314（例如，蚀刻阻止部315）。
绝缘层被沉积到TSV区域内（框212）。如图3C所示，绝缘层332被沉积到TSV330内，以使TSV330与晶圆302电隔离。在一个实施例中，绝缘层332可以是氧化物层（SiO2）等。非均匀的干燥蚀刻过程被用来将绝缘层从TSV的底部去除，同时保留在TSV的侧壁上的该绝缘层。然后，扩散阻挡金属334（例如，Ti等）和金属334被沉积到第二表面306上。扩散阻挡金属334和籽晶金属334可被图案化（通过合适的光刻步骤），以在不同的器件（例如，集成电路装置308、焊锡凸块等）之间提供电互连。
导电材料被沉积到TSV区域内和第二表面上（框214）。如图3C所示，导电材料336被沉积到TSV区域328内而形成TSV330（例如，形成用于电互连功能的通路），导电材料336被沉积到第二表面306上而形成RDL结构331（例如，TSV330被充填，而RDL结构331的形成可以单一电镀过程（例如，镀铜）中实现。RDL结构331可被用来在与集成电路装置308存在电通信的TSV330、和一个或多个焊锡凸块（这里描述的）之间提供电互连。在一个或多个实施例中，导电材料336可通过一种或多种合适的电镀技术被沉积。例如，可用铜材料以镀铜的方式将导电材料336沉积到TSV330内和第二表面306上。因此，导电材料336可被用作TSV330内的电互连，同时也起着再分布结构的作用。
电介质材料被沉积到半导体晶圆的第二表面上方（框216）。如图3C所示，电介质材料338被沉积到半导体晶圆302的第二表面306上方。在一个实施例中，电介质材料338可以是低温聚苯并二恶唑类聚合物（PBO）。电介质层338可被图案化和蚀刻（通过合适的光刻过程）成至少部分地露出导电材料336。
如图2A所示，集成电路裸片被加装于半导体晶圆上（框218）。集成电路裸片的加装包括在第二表面上方形成焊锡凸块的第一阵列（框220）。微焊锡凸块342的第一阵列340形成于第二表面306上方（例如，形成于电介质层338的被蚀刻的部分上）。例如，一个或多个微焊锡球（预回流的微焊锡凸块342）被定位（通过焊锡球放置模板等）在电介质层338的被蚀刻的部分上，所述被蚀刻的部分至少部分地露出导电材料336。可想到，熔剂可被施加于导电材料336，以去除露出的导电材料336区域表面的氧化物。然后，微焊锡球被回流而形成微焊锡凸块342。导电材料336可被图案化，以形成凸块接口341。例如，凸块接口341可被构造为UBM344。在另一示例中，凸块接口341可被构造为铜柱。然后，集成电路裸片被定位在焊锡凸块上（框222）。如图3C所示，集成电路裸片346被定位在微焊锡凸块342上。微焊锡凸块342被构造为在集成电路裸片346和TSV330之间提供电互连功能。集成电路裸片346可以多种方式构造。例如，集成电路裸片346可以是数字集成电路裸片。在另一示例中，集成电路裸片346可以是模拟集成电路裸片。在又一示例中，集成电路裸片346可以是混合信号集成电路裸片。
如图2B所示，封装结构形成于半导体晶圆的第二表面上方（框224）。封装结构348然后形成于第二表面306上方（例如，形成在电介质层338上），以封装集成电路裸片346（见图3D）。因此，封装结构348可至少部分地将集成电路裸片346保持在位，同时将集成电路裸片346从进一步的加工步骤中隔离。在一个实施例中，封装结构348可由合适的模制合成物等组成。
加强结构被沉积到封装结构上（框226）。如图3D所示，加强结构350被沉积（例如，形成）到封装结构348上，以向装置300提供机械强度。如上所述，加强结构350的CET可与装置300（例如，晶圆302）的CET相当。在一个或多个实施例中，加强结构350可以是硅材料或金属材料（例如，42合金）。
然后，将载体晶圆从半导体晶圆上脱粘（例如，去除）（框228）。例如，通过充分加热临时粘合层332至允许去除载体晶圆324（见图3E），可将载体晶圆324从晶圆302上脱粘。一旦载体晶圆被去除，一个或多个导电层形成于半导体晶圆的第一表面上（框230）。如图3E所示，第一聚合物层352可被沉积到第一表面304上，且选择性地被图案化成至少部分地露出第一导电垫312。一旦第一导电垫312被至少部分地露出，导电层354可形成（例如，被沉积或被图案化）于聚合物层352上。如上所述，扩散阻挡金属和籽晶金属（例如，扩散阻挡金属334和籽晶金属334）可首先被沉积和图案化，然后是导电层354的沉积。在一个实施例中，导电层354可被构造为再分布结构355等。一旦导电层354形成于聚合物层352上，第二聚合物层356可被沉积到聚合物层352和导电层354上。然后，聚合物层356被图案化成至少部分地露出导电层354。在一个实施例中，第一和第二聚合物层352、356可通过一个或多个合适的低温PBO过程形成。然后，导电层358被沉积到聚合物层356上，且被图案化成形成凸块接口360。在一个实施例中，凸块接口360可被构造为UBM362（见图3E）。在另一实施例中，凸块接口360可被构造为铜柱。
如图2B所示，可采用合适的晶圆级封装过程来分段和封装独立的半导体装置（框232）。例如，焊锡凸块的第二阵列形成于半导体晶圆的第一表面上方（框234）。焊锡凸块365的第二阵列364形成于导电层358（例如，凸块接口360）上。如在焊锡凸块342的第一阵列340方面所述，熔剂可被施加于凸块接口360，然后一个或多个焊锡球被定位在凸块接口360上。焊锡球一旦被定位，则接受合适的回流过程来形成焊锡凸块365。在一个或多个实施例中，分段的半导体装置可包括晶圆芯片规模封装装置。
结论
虽然已经以具体到结构特征和/或过程操作的语言描述了本主题，但是应该理解，在所附权利要求中限定的主题并不局限于上述的具体特征或操作。相反，上述的具体特征和操作是作为实施权利要求的示例性形式公开的。

Claims (18)

1.一种过程，包括：
用粘合材料将载体晶圆粘合到半导体晶圆的第一表面，所述半导体晶圆包括电介质层、用于使所述载体晶圆与所述半导体晶圆对准的对准标记、以及导电蚀刻阻止部，所述导电蚀刻阻止部在半导体晶圆内布置在第一表面和与第一表面相反的第二表面之间，其中所述电介质层接近导电蚀刻阻止部布置，所述电介质层被构造为用于控制一个或多个蚀刻速度；和
在半导体晶圆中形成通路，所述通路延伸穿过所述半导体晶圆的一部分和所述电介质层到导电蚀刻阻止部，所述载体晶圆在通路的形成过程中为半导体晶圆提供机械支撑。
2.如权利要求1所述的过程，其特征在于，所述过程还包括：
在半导体晶圆的第二表面上方形成焊锡凸块的第一阵列；
将集成电路裸片定位在焊锡凸块的第一阵列中的一个或多个焊锡凸块上；
在第二表面上方形成封装结构，以至少实质上封装集成电路裸片；和
在封装结构上形成加强结构，以便为半导体晶圆提供机械支撑。
3.如权利要求2所述的过程，其特征在于，所述加强结构由42合金合成物组成。
4.如权利要求2所述的过程，其特征在于，所述封装结构由模制合成物组成。
5.如权利要求1所述的过程，其特征在于，形成通路包括：
在半导体晶圆中蚀刻通路区域，所述通路区域从第二表面附近延伸到导电蚀刻阻止部；
在通路区域中沉积内衬；和
在通路区域中和第二表面上沉积导电材料。
6.如权利要求1所述的过程，其特征在于，所述导电蚀刻阻止部由铝和铜中的至少一种构成。
7.一种过程，包括：
获得一种半导体晶圆，其具有第一表面和与第一表面相反的第二表面，所述半导体晶圆包括电介质层、对准标记、第一导电垫和第二导电垫，所述第一导电垫布置在第一表面上，所述第二导电垫布置在半导体晶圆内，其中所述电介质层接近第二导电垫布置，所述电介质层被构造为用于控制一个或多个蚀刻速度；
用粘合材料将载体晶圆粘合到半导体晶圆的第一表面，所述载体晶圆经由所述对准标记与所述半导体晶圆对准；
背磨半导体晶圆的第二表面；和
在半导体晶圆中形成通路，所述通路从第二表面附近穿过所述半导体晶圆的一部分和所述电介质层延伸到第二导电垫，
其中，在半导体晶圆的背磨和通路的形成过程中，所述载体晶圆为半导体晶圆提供机械支撑。
8.如权利要求7所述的过程，所述过程还包括：
在半导体晶圆的第二表面上方形成焊锡凸块的第一阵列；
将集成电路裸片定位在焊锡凸块的第一阵列中的一个或多个焊锡凸块上；
在第二表面上方形成封装结构，以至少实质上封装集成电路裸片；
在封装结构上形成加强结构，以便为半导体晶圆提供机械支撑；和
在半导体晶圆的第一表面上方形成焊锡凸块的第二阵列。
9.如权利要求8所述的过程，其特征在于，所述加强结构由42合金合成物组成。
10.如权利要求8所述的过程，其特征在于，所述封装结构由模制合成物组成。
11.如权利要求7所述的过程，其特征在于，形成通路包括：
在半导体晶圆中蚀刻通路区域，所述通路区域从第二表面附近延伸到第二导电垫；
在通路区域中沉积内衬；和
在通路区域中和第二表面上沉积导电材料，
其中，所述内衬被构造为使导电材料与半导体晶圆电隔离。
12.如权利要求7所述的过程，其特征在于，第一导电垫和第二导电垫由铝和铜中的至少一种构成。
13.一种半导体装置，包括：
基板，其具有第一表面和第二表面，所述基板包括电介质层、用于使载体晶圆与所述基板对准的对准标记、布置在基板内的蚀刻阻止部、和形成在基板中的一个或多个集成电路装置，所述电介质层接近蚀刻阻止部布置，所述电介质层被构造为用于控制一个或多个蚀刻速度；
布置在第一表面上方的焊锡凸块的第一阵列；
布置在第二表面上方的焊锡凸块的第二阵列；和
从第二表面附近穿过电介质层延伸到蚀刻阻止部的通路，
其中，至少一个集成电路装置通过通路电连接于焊锡凸块的第二阵列中的至少一个焊锡凸块。
14.如权利要求13所述的半导体装置，其特征在于，所述半导体装置还包括导电材料，所述导电材料至少部分地布置在通路区域内，且至少部分地布置在第二表面上。
15.如权利要求13所述的半导体装置，其特征在于，所述半导体装置还包括再分布结构，所述再分布结构布置在第一表面上，以在焊锡凸块的第一阵列中的至少一个焊锡凸块与所述一个或多个集成电路装置中的至少一个集成电路装置之间提供电连接。
16.如权利要求13所述的半导体装置，其特征在于，所述半导体装置还包括粘合于所述基板的所述载体晶圆，所述载体晶圆用于为所述基板提供机械支撑。
17.如权利要求13所述的半导体装置，其特征在于，所述半导体装置还包括：
集成电路裸片，其布置在焊锡凸块的第二阵列中的至少一个焊锡凸块上；
封装结构，其布置在基板的第二表面上方，以至少实质上封装所述集成电路裸片；和
加强结构，其布置在所述封装结构上，以便为基板提供机械支撑。
18.如权利要求17所述的半导体装置，其特征在于，所述加强结构由42合金合成物组成。
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9437564B2 (en) 2013-07-09 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9607921B2 (en) 2012-01-12 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package interconnect structure
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US9401308B2 (en) 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US9368398B2 (en) 2012-01-12 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US10015888B2 (en) 2013-02-15 2018-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect joint protective layer apparatus and method
US9589862B2 (en) 2013-03-11 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9082776B2 (en) 2012-08-24 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having protective layer with curved surface and method of manufacturing same
US8987851B2 (en) * 2012-09-07 2015-03-24 Mediatek Inc. Radio-frequency device package and method for fabricating the same
US8937387B2 (en) * 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US9543373B2 (en) * 2013-10-23 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US9401287B2 (en) * 2014-02-07 2016-07-26 Altera Corporation Methods for packaging integrated circuits
US9355881B2 (en) 2014-02-18 2016-05-31 Infineon Technologies Ag Semiconductor device including a dielectric material
US9570413B2 (en) 2014-02-25 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with solder ball revealed through laser
US9711474B2 (en) * 2014-09-24 2017-07-18 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure with polymeric layer and manufacturing method thereof
CN105448862B (zh) * 2014-09-29 2018-08-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其制作方法
TWI595613B (zh) 2014-11-18 2017-08-11 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI604565B (zh) * 2015-08-04 2017-11-01 精材科技股份有限公司 一種感測晶片封裝體及其製造方法
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
CN107275197A (zh) * 2016-04-08 2017-10-20 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10026687B1 (en) * 2017-02-20 2018-07-17 Globalfoundries Inc. Metal interconnects for super (skip) via integration
CN108346588B (zh) * 2017-09-30 2020-12-04 中芯集成电路（宁波）有限公司 一种晶圆级系统封装方法以及封装结构
US20190148325A1 (en) * 2017-11-10 2019-05-16 Advanced Semiconductor Engineering, Inc. Electronic device and method for manufacturing the same
US10504854B2 (en) * 2017-12-07 2019-12-10 Intel Corporation Through-stiffener inerconnects for package-on-package apparatus and methods of assembling same
US10700008B2 (en) * 2018-05-30 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having redistribution layer structures
US11037908B2 (en) 2019-07-25 2021-06-15 Sandisk Technologies Llc Bonded die assembly containing partially filled through-substrate via structures and methods for making the same
CN113793838B (zh) * 2021-11-15 2022-02-25 深圳市时代速信科技有限公司 半导体器件及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071781A (zh) * 2006-05-09 2007-11-14 探微科技股份有限公司 晶片级封装方法及其结构
CN101309854A (zh) * 2005-11-17 2008-11-19 皇家飞利浦电子股份有限公司 包括mems元件的电子器件

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101309854A (zh) * 2005-11-17 2008-11-19 皇家飞利浦电子股份有限公司 包括mems元件的电子器件
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