CN110416285A - 一种超结功率dmos器件 - Google Patents
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Abstract
本发明提供一种超结功率DMOS器件,包括金属化漏电极、第一导电类型重掺杂半导体衬底、第一导电类型半导体柱区、第二导电类型半导体柱区、第二导电类型半导体体区、第一导电类型重掺杂半导体源区、第二导电类型重掺杂半导体接触区、多晶硅栅电极、栅介质层、金属化源电极,本发明通过在常规超结功率DMOS器件的基础上,将第一导电类型重掺杂半导体衬底由均匀掺杂改变为非均匀掺杂,避免了高掺杂衬底与低掺杂漂移区层的电场尖峰,缓解了SEB效应,从而提高其器件的可靠性。
Description
技术领域
本发明属于功率半导体器件技术领域,涉及一种超结功率DMOS器件。
背景技术
具有超结结构的DMOS器件是近年来出现的一种重要的功率器件,它的基本原理是电荷平衡原理,通过在普通功率DMOS的漂移区中引入彼此间隔的P柱和n柱的超结结构,打破了常规器件中漂移区的比导通电阻与耐压间的2.5次方的关系,从而在高压应用的情况下,大大降低器件的导通电阻,提高了高压功率器件的转化效率,是电力电子领域理想的功率开关器件,应用前景十分广阔。
随着战略武器技术、空间技术和核技术的快速发展,越来越多的电子设备要工作在核辐射和空间辐射等恶劣的辐射环境之中。辐射使得电子系统的性能发生退化,大大降低其可靠性和寿命,甚至导致整个电子系统瘫痪,造成巨大的安全隐患和成本浪费。其中,单粒子效应是影响宇宙空间中航天器正常运行所面临的主要威胁之一,而重离子和高能质子是诱发航天器内电子元器件发生单粒子效应的重要粒子源。当单个重粒子或高能质子突然穿入到半导体器件中时,沿材料入射径迹产生大量电荷将引发诸如单粒子烧毁(SEB)、单粒子栅穿(SEGR)等瞬发性效应,这给元器件带来致命性损伤,影响整个电学系统的正常运行。超结MOSFET作为一款性能较VDMOS有极大提升的功率器件,在航空航天领域的前景非常广阔。提高超结功率DMOS器件的抗SEB辐射能力,目前除了普遍采用一些像普通超结功率DMOS器件一样降低源区掺杂浓度之外,还可以在衬底与漂移区之间增加buffer层。但是降低器件源区掺杂浓度,会使其导通电阻增大;增加buffer层的方法可以降低N+衬底与N-漂移区之间的电场峰值,但是在buffer层和N-漂移区之间的界面仍然有电场峰值存在,缓解SEB能力有限。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种超结功率DMOS器件。
为实现上述发明目的,本发明技术方案如下:
一种超结功率DMOS器件,从下至上依次包括包括金属化漏电极1、第一导电类型重掺杂半导体衬底2、第一导电类型半导体柱区3,第一导电类型半导体柱区3和第二导电类型半导体柱区4交替设置,所述第二导电类型半导体柱区4顶部具有第二导电类型半导体体区5,所述第二导电类型半导体体区5的侧面与第一导电类型半导体柱区3相接触;所述第二导电类型半导体体区5内部设有具有第一导电类型重掺杂半导体源区6和第二导电类型重掺杂半导体接触区7;多晶硅栅电极8覆盖全部的第一导电类型半导体柱区3和部分的第二导电类型半导体体区5,并与第一导电类型半导体柱区3和第二导电类型半导体体区5之间通过栅介质层9相隔离;金属化源电极10位于器件的最上层,金属化源电极10的下表面与第二导电类型重掺杂半导体接触区7的上表面和第一导电类型重掺杂半导体源区6的部分上表面直接接触,其特征在于:所述的第一导电类型重掺杂半导体衬底2采用非均匀掺杂,其掺杂浓度满足:从靠近金属化漏电极1到靠近第一导电类型半导体柱区3的方向上,掺杂浓度逐渐降低;第一导电类型重掺杂半导体衬底2的掺杂浓度还满足:靠近金属化漏电极1的掺杂浓度使其能够与金属形成欧姆接触,靠近第一导电类型半导体柱区3底部1-3um处的浓度与第一导电类型半导体柱区3的掺杂浓度相同。
作为优选方式,所述器件采用硅、锗、锗硅、碳化硅、砷化镓、磷化铟、氮化镓半导体材料制作。
作为优选方式,第一导电类型重掺杂半导体衬底2和金属化漏电极1之间设有第一导电类型半导体buffer层21。
作为优选方式,所述第一导电类型为N型,所述第二导电类型为P型;或者所述第一导电类型为P型,所述第二导电类型为N型。
本发明的有益效果为:通过在常规超结功率DMOS器件的基础上,将第一导电类型重掺杂半导体衬底由均匀掺杂改变为非均匀掺杂,避免了高掺杂衬底与低掺杂漂移区层的电场尖峰,缓解了SEB效应,从而提高其器件的可靠性。
附图说明
图1是本发明实施例1的一种超结功率DMOS器件结构及其寄生BJT管的示意图;
图2是常规超结功率DMOS器件纵向上的掺杂浓度示意图;
图3是本发明实施例2的超结功率DMOS器件结构示意图;
图4是本发明实施例2的超结功率DMOS器件纵向上的掺杂浓度示意图;
图5是本发明实施例1的一种超结功率DMOS器件纵向上的掺杂浓度示意图。
图中:1是金属化漏电极、21是第一导电类型半导体buffer层、2是第一导电类型重掺杂半导体衬底、3是第一导电类型半导体柱区、4是第二导电类型半导体柱区、5是第二导电类型半导体体区、6是第一导电类型重掺杂半导体源区、7是第二导电类型重掺杂半导体接触区、8是多晶硅栅电极、9是栅介质层、10是金属化源电极。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
实施例1
一种超结功率DMOS器件,从下至上依次包括包括金属化漏电极1、第一导电类型重掺杂半导体衬底2、第一导电类型半导体柱区3,第一导电类型半导体柱区3和第二导电类型半导体柱区4交替设置,所述第二导电类型半导体柱区4顶部具有第二导电类型半导体体区5,所述第二导电类型半导体体区5的侧面与第一导电类型半导体柱区3相接触;所述第二导电类型半导体体区5内部设有具有第一导电类型重掺杂半导体源区6和第二导电类型重掺杂半导体接触区7;多晶硅栅电极8覆盖全部的第一导电类型半导体柱区3和部分的第二导电类型半导体体区5,并与第一导电类型半导体柱区3和第二导电类型半导体体区5之间通过栅介质层9相隔离;金属化源电极10位于器件的最上层,金属化源电极10的下表面与第二导电类型重掺杂半导体接触区7的上表面和第一导电类型重掺杂半导体源区6的部分上表面直接接触,其特征在于:所述的第一导电类型重掺杂半导体衬底2采用非均匀掺杂,其掺杂浓度满足:从靠近金属化漏电极1到靠近第一导电类型半导体柱区3的方向上,掺杂浓度逐渐降低;第一导电类型重掺杂半导体衬底2的掺杂浓度还满足:靠近金属化漏电极1的掺杂浓度使其能够与金属形成欧姆接触,靠近第一导电类型半导体柱区3底部1-3um处的浓度与第一导电类型半导体柱区3的掺杂浓度相同,能够实现杂质浓度的平滑过渡。
基于上述技术方案,当第一导电类型半导体为N型半导体而第二导电类型半导体为P型时,本发明提供的超结功率DMOS器件为N沟道超结功率DMOS器件;当第一导电类型半导体为P型半导体而第二导电类型半导体为N型时,本发明提供的超结功率DMOS器件为P沟道超结功率DMOS器件。
以N沟道超结功率DMOS器件为例说明本发明的工作原理:
图2为常规超结功率DMOS器件纵向上的掺杂浓度示意图。超结功率DMOS器件在金属化漏电极1偏压低于正常击穿电压的情况下,辐射产生的电子空穴对漂移电流可以改变外延层的电场分布,造成第一导电类型重掺杂半导体衬底2和第一导电类型半导体柱区3的界面发生雪崩击穿。重离子入射和雪崩击穿产生的电子空穴对在金属化漏电极1偏压的作用下形成漂移电流。其中空穴越过第一导电类型半导体柱区3成为寄生三极管的基极电流,使处于关断状态的寄生三极管导通,引起发射结的载流子注入效应,进一步促进了雪崩倍增效应的发生。其中超结功率DMOS器件内部的寄生三极管,如图1所示。超结功率DMOS器件的第一导电类型重掺杂半导体源区6为寄生三极管的发射极,第一导电类型半导体柱区3为寄生三极管的集电极,第二导电类型半导体体区5为寄生三极管的基极。这一正反馈机制将使漏极电流持续上升直至造成器件温度过高烧毁就是超结功率DMOS器件发生SEB失效。
通过常规超结功率DMOS器件的SEB失效机理,防止电场峰值向N+衬底和N-柱区之间的界面转移,降低雪崩倍增效应的发生,可以提高器件的抗SEB辐射能力。
本发明提出的一种抗辐射加固的超结功率DMOS器件,第一导电类型重掺杂半导体衬底2采用非均匀掺杂。图5为本发明提供的一种超结功率DMOS器件纵向上的掺杂浓度示意图。本发明提出的超结功率DMOS器件能够加固其抗辐射能力的原因是:由于第一导电类型重掺杂半导体衬底2采用非均匀掺杂,使第一导电类型重掺杂半导体衬底2到第一导电类型半导体柱区3掺杂浓度缓慢变化,不存在明显的结区,因此电场峰值能够被拉平,降低雪崩倍增效应的发生,则寄生三极管更难被开启,能够更有效的缓解SEB效应,提高器件可靠性。
优选的,所述器件采用硅、锗、锗硅、碳化硅、砷化镓、磷化铟、氮化镓半导体材料制作。
实施例2
本实施例和实施例1的区别在于:第一导电类型重掺杂半导体衬底2和金属化漏电极1之间设有第一导电类型半导体buffer层21。
图3是具有N-buffer层的超结功率DMOS器件结构示意图,图4是具有buffer层的超结功率DMOS器件纵向上的掺杂浓度示意图。此结构将电场峰值转移到N-buffer层和N-柱区之间的界面,一定程度上缓解了SEB效应,但是N-buffer/N-柱区结仍存在电场峰,因此缓解能力有限。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (4)
1.一种超结功率DMOS器件,从下至上依次包括包括金属化漏电极(1)、第一导电类型重掺杂半导体衬底(2)、第一导电类型半导体柱区(3),第一导电类型半导体柱区(3)和第二导电类型半导体柱区(4)交替设置,所述第二导电类型半导体柱区(4)顶部具有第二导电类型半导体体区(5),所述第二导电类型半导体体区(5)的侧面与第一导电类型半导体柱区(3)相接触;所述第二导电类型半导体体区(5)内部设有具有第一导电类型重掺杂半导体源区(6)和第二导电类型重掺杂半导体接触区(7);多晶硅栅电极(8)覆盖全部的第一导电类型半导体柱区(3)和部分的第二导电类型半导体体区(5),并与第一导电类型半导体柱区(3)和第二导电类型半导体体区(5)之间通过栅介质层(9)相隔离;金属化源电极(10)位于器件的最上层,金属化源电极(10)的下表面与第二导电类型重掺杂半导体接触区(7)的上表面和第一导电类型重掺杂半导体源区(6)的部分上表面直接接触,其特征在于:所述的第一导电类型重掺杂半导体衬底(2)采用非均匀掺杂,其掺杂浓度满足:从靠近金属化漏电极(1)到靠近第一导电类型半导体柱区(3)的方向上,掺杂浓度逐渐降低;第一导电类型重掺杂半导体衬底(2)的掺杂浓度还满足:靠近金属化漏电极(1)的掺杂浓度使其能够与金属形成欧姆接触,靠近第一导电类型半导体柱区(3)底部1-3um处的浓度与第一导电类型半导体柱区(3)的掺杂浓度相同。
2.根据权利要求1所述的一种超结功率DMOS器件,其特征在于:所述器件采用硅、锗、锗硅、碳化硅、砷化镓、磷化铟、氮化镓半导体材料制作。
3.根据权利要求1所述的一种超结功率DMOS器件,其特征在于:第一导电类型重掺杂半导体衬底(2)和金属化漏电极(1)之间设有第一导电类型半导体buffer层(21)。
4.根据权利要求1所述的一种超结功率DMOS器件,其特征在于:所述第一导电类型为N型,所述第二导电类型为P型;或者所述第一导电类型为P型,所述第二导电类型为N型。
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