CN110416168A - 扇出型半导体封装件 - Google Patents
扇出型半导体封装件 Download PDFInfo
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- CN110416168A CN110416168A CN201910113935.3A CN201910113935A CN110416168A CN 110416168 A CN110416168 A CN 110416168A CN 201910113935 A CN201910113935 A CN 201910113935A CN 110416168 A CN110416168 A CN 110416168A
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Abstract
本公开提供一种扇出型半导体封装件,所述扇出型半导体封装件包括:芯构件,具有通孔;半导体芯片,设置在所述芯构件的所述通孔中并具有设置有连接焊盘的有效表面和设置为与所述有效表面背对的无效表面;散热构件,直接结合到所述半导体芯片的所述无效表面;包封剂,包封所述半导体芯片的至少一部分;以及连接构件,设置在所述半导体芯片的所述有效表面上并包括电连接到所述半导体芯片的连接焊盘的重新分布层。
Description
本申请要求于2018年4月27日在韩国知识产权局提交的第10-2018-0048919号韩国专利申请的优先权的权益,所述韩国专利申请的公开内容通过引用全部包含于此。
技术领域
本公开涉及一种扇出型半导体封装件。
背景技术
半导体封装件在形状方面已被持续地需要变薄和变轻,并且已需要以功能方面需要复杂化和多功能化的系统级封装(SiP)形式实现。为满足如上所述的技术要求而提出的封装技术的类型之一是扇出型半导体封装件。这种扇出型半导体封装件具有紧凑的尺寸,并且可使得通过将连接端子重新分布在半导体芯片所设置的区域的外部来实现多个引脚。
具体地,近来已经开发的具有层叠封装(POP)结构的半导体封装件需要一种能够改善散热特性同时显著减小封装件的厚度的结构。
发明内容
本公开的一方面可提供一种提高散热特性的扇出型半导体封装件。
在扇出型半导体封装件中,包含碳的散热构件可直接结合到半导体芯片的无效表面。
根据本公开的一方面,一种扇出型半导体封装件可包括:芯构件,具有通孔;半导体芯片,设置在所述芯构件的所述通孔中并具有设置有连接焊盘的有效表面和设置为与所述有效表面背对的无效表面;散热构件,直接结合到所述半导体芯片的所述无效表面;包封剂,包封所述半导体芯片的至少一部分;以及连接构件,设置在所述半导体芯片的所述有效表面上并包括电连接到所述半导体芯片的连接焊盘的重新分布层。
根据本公开的一方面,一种扇出型半导体封装件可包括:第一半导体封装件,包括:芯构件,具有通孔;第一半导体芯片,设置在所述芯构件的所述通孔中并具有设置有连接焊盘的有效表面和设置为与所述有效表面背对的无效表面;散热构件,直接结合到所述第一半导体芯片的无效表面;第一包封剂,包封所述第一半导体芯片的至少一部分;及连接构件,设置在所述第一半导体芯片的有效表面上并包括电连接到所述第一半导体芯片的连接焊盘的重新分布层;以及第二半导体封装件,包括:布线基板,设置在所述第一半导体封装件上并通过连接端子电连接到所述连接构件;至少一个第二半导体芯片,设置在所述布线基板上;及第二包封剂,包封所述第二半导体芯片的至少一部分。
附图说明
通过下面结合附图进行的详细描述,本公开的以上和其他方面、特征和其他优点将被更清楚地理解,在附图中:
图1是示出电子装置系统的示例的示意性框图;
图2是示出电子装置的示例的示意性透视图;
图3A和图3B是示出扇入型半导体封装件在被封装之前和封装之后的状态的示意性截面图;
图4是示出扇入型半导体封装件的封装工艺的示意性截面图;
图5是示出扇入型半导体封装件安装在中介基板上并且最终安装在电子装置的主板上的情况的示意性截面图;
图6是示出扇入型半导体封装件嵌入在中介基板中并且最终安装在电子装置的主板上的情况的示意性截面图;
图7是示出扇出型半导体封装件的示意性截面图;
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图;
图9是示出扇出型半导体封装件的示例的示意性截面图;
图10A至图10C是将散热构件结合到第一半导体芯片的工艺的示例的示意图;
图11是示出扇出型半导体封装件的另一示例的示意性截面图;
图12是示出扇出型半导体封装件的另一示例的示意性截面图;
图13是示出扇出型半导体封装件的另一示例的示意性截面图;
图14是示出扇出型半导体封装件的另一示例的示意性截面图;以及
图15A至图15C是示意性地示出根据示例性实施例的扇出型半导体封装件的散热效果的曲线图。
具体实施方式
在下文中,将参照附图描述本公开中的示例性实施例。在附图中,为了清楚起见,可夸大或缩小组件的形状、尺寸等。
然而,本公开可以以许多不同的形式例示,并且不应该被解释为局限于这里阐述的具体实施例。更确切地,提供这些实施例,使得本公开将是彻底的和完整的,并且将要把本公开的范围充分地传达到本领域的技术人员。
电子装置
图1是示出电子装置系统的示例的示意性框图。
参照图1,电子装置1000可将主板1010容纳在其中。主板1010可包括物理连接或者电连接到其的芯片相关组件1020、网络相关组件1030、其他组件1040等。这些组件可通过各种信号线1090连接到以下将描述的其他组件。
芯片相关组件1020可包括:存储器芯片,诸如易失性存储器(例如,动态随机存取存储器(DRAM))、非易失性存储器(例如,只读存储器(ROM))、闪存等;应用处理器芯片,诸如中央处理器(例如,中央处理单元(CPU))、图形处理器(例如,图形处理单元(GPU))、数字信号处理器、密码处理器、微处理器、微控制器等;以及逻辑芯片,诸如模拟数字转换器(ADC)、专用集成电路(ASIC)等。然而,芯片相关组件1020不限于此,而是还可包括其他类型的芯片相关组件。此外,芯片相关组件1020可彼此组合。
网络相关组件1030可包括被指定为根据诸如以下的协议操作的组件:无线保真(Wi-Fi)(电工电子工程师协会(IEEE)802.11族等)、全球微波接入互操作性(WiMAX)(IEEE802.16族等)、IEEE 802.20、长期演进(LTE)、演进数据最优化(Ev-DO)、高速分组接入+(HSPA+)、高速下行链路分组接入+(HSDPA+)、高速上行链路分组接入+(HSUPA+)、增强型数据GSM环境(EDGE)、全球移动通信系统(GSM)、全球定位系统(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、蓝牙、3G协议、4G协议和5G协议以及在上述协议之后指定的任意其他无线协议和有线协议。然而,网络相关组件1030不限于此,而是还可包括被指定为根据各种其他无线标准或协议或者有线标准或协议操作的组件。此外,网络相关组件1030可与上述芯片相关组件1020一起彼此组合。
其他组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等。然而,其他组件1040不限于此,而是还可包括用于各种其他目的的无源组件等。此外,其他组件1040可与上述芯片相关组件1020或网络相关组件1030一起彼此组合。
根据电子装置1000的类型,电子装置1000可包括可物理连接和/或电连接到主板1010或者可不物理连接和/或电连接到主板1010的其他组件。这些其他组件可包括例如相机1050、天线1060、显示器1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、指南针(未示出)、加速计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储单元(例如,硬盘驱动器)(未示出)、光盘(CD)驱动器(未示出)、数字通用光盘(DVD)驱动器(未示出)等。然而,这些其他组件不限于此,而是还可根据电子装置1000的类型等而包括用于各种目的的其他组件。
电子装置1000可以是智能电话、个人数字助理(PDA)、数字摄像机、数码相机、网络系统、计算机、监视器、平板个人计算机(PC)、膝上型PC、上网本PC、电视机、视频游戏机、智能手表、汽车组件等。然而,电子装置1000不限于此,而可以是处理数据的任意其他电子装置。
图2是示出电子装置的示例的示意性透视图。
参照图2,半导体封装件可在如上所述的各种电子装置1000中用于各种目的。例如,母板1110可容纳在智能电话1100的主体1101中,并且各种电子组件1120可物理连接或者电连接到母板1110。另外,可物理连接和/或电连接到母板1110或者可不物理连接或电连接到母板1110的其他组件(诸如,相机1130)可容纳在主体1101中。电子组件1120中的一些可以是芯片相关组件,半导体封装件100可以是例如芯片相关组件之中的应用处理器,但不限于此。电子装置不必然地限于智能电话1100,而可以是如上所述的其他电子装置。
半导体封装件
通常,半导体芯片中集成了大量的微电子电路。然而,半导体芯片本身可能无法用作成品的半导体产品,并且可能会由于外部的物理冲击或者化学冲击而损坏。因此,半导体芯片本身可能不会被使用,而半导体芯片被封装并且在封装的状态下在电子装置等中使用。
需要半导体封装的原因在于:就电连接而言,半导体芯片和电子装置的主板之间的电路宽度存在差异。详细地,半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间距非常细小,而在电子装置中使用的主板的组件安装焊盘的尺寸和主板的组件安装焊盘之间的间距显著大于半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间距。因此,可能难以将半导体芯片直接安装在主板上,并且需要用于缓解半导体芯片和主板之间的电路宽度的差异的封装技术。
通过封装技术制造的半导体封装件可根据其结构和目的而分为扇入型半导体封装件和扇出型半导体封装件。
在下文中,将参照附图更详细地描述扇入型半导体封装件和扇出型半导体封装件。
扇入型半导体封装件
图3A和图3B是示出扇入型半导体封装件在被封装之前和封装之后的状态的示意性截面图。
图4是示出扇入型半导体封装件的封装工艺的示意性截面图。
参照附图,半导体芯片2220可以是例如处于裸态的集成电路(IC),并且包括:主体2221,包括硅(Si)、锗(Ge)、砷化镓(GaAs)等;连接焊盘2222,形成在主体2221的一个表面上,并且包括诸如铝(Al)等的导电材料;以及诸如氧化物膜、氮化物膜等的钝化层2223,形成在主体2221的一个表面上并且覆盖连接焊盘2222的至少部分。在这种情况下,由于连接焊盘2222非常小,因此难以将集成电路(IC)安装在中尺寸等级的印刷电路板(PCB)以及电子装置的主板等上。
因此,根据半导体芯片2220的尺寸,可在半导体芯片2220上形成连接构件2240,以使连接焊盘2222重新分布。连接构件2240可通过如下步骤形成:使用诸如光可成像介电(PID)树脂的绝缘材料在半导体芯片2220上形成绝缘层2241,形成使连接焊盘2222敞开的通路孔2243h,然后形成布线图案2242和过孔2243。然后,可形成保护连接构件2240的钝化层2250,可形成开口2251,并且可形成凸块下金属层2260等。也就是说,可通过一系列工艺制造包括例如半导体芯片2220、连接构件2240、钝化层2250和凸块下金属层2260的扇入型半导体封装件2200。
如上所述,扇入型半导体封装件可具有半导体芯片的所有的连接焊盘(例如,输入/输出(I/O)端子)设置在半导体芯片的内部的封装件形式,可具有优异的电特性,并且可以以低成本生产。因此,安装在智能电话中的许多元件已经按照扇入型半导体封装件形式来制造。详细地,安装在智能电话中的许多元件已经被开发为在具有紧凑的尺寸的同时实现快速的信号传输。
然而,在扇入型半导体封装件中,由于所有的I/O端子需要设置在半导体芯片的内部,因此扇入型半导体封装件具有很大的空间局限性。因此,难以将此结构应用于具有大量的I/O端子的半导体芯片或者具有小尺寸的半导体芯片。另外,由于上述缺点,可能无法在电子装置的主板上直接安装和使用扇入型半导体封装件。原因在于:即使在半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距通过重新分布工艺被增大的情况下,半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距可能仍不足以将扇入型半导体封装件直接安装在电子装置的主板上。
图5是示出扇入型半导体封装件安装在中介基板上并且最终安装在电子装置的主板上的情况的示意性截面图。
图6是示出扇入型半导体封装件嵌入在中介基板中并且最终安装在电子装置的主板上的情况的示意性截面图。
参照附图,在扇入型半导体封装件2200中,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过中介基板2301再次重新分布,并且在扇入型半导体封装件2200安装在中介基板2301上的状态下,扇入型半导体封装件2200可最终安装在电子装置的主板2500上。在这种情况下,焊球2270等可通过底部填充树脂2280等固定,并且半导体芯片2220的外侧可利用模制材料2290等覆盖。可选地,扇入型半导体封装件2200可嵌入在单独的中介基板2302中,在扇入型半导体封装件2200嵌入在中介基板2302中的状态下,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过中介基板2302再次重新分布,并且扇入型半导体封装件2200可最终安装在电子装置的主板2500上。
如上所述,可能难以在电子装置的主板上直接安装和使用扇入型半导体封装件。因此,扇入型半导体封装件可安装在单独的中介基板上然后通过封装工艺安装在电子装置的主板上,或者可在扇入型半导体封装件嵌入在中介基板中的状态下在电子装置的主板上安装和使用扇入型半导体封装件。
扇出型半导体封装件
图7是示出扇出型半导体封装件的示意性截面图。
参照图7,在扇出型半导体封装件2100中,例如,半导体芯片2120的外侧可通过包封剂2130保护,并且半导体芯片2120的连接焊盘2122可通过连接构件2140重新分布到半导体芯片2120的外部。在这种情况下,钝化层2150还可形成在连接构件2140上,并且凸块下金属层2160还可形成在钝化层2150的开口中。焊球2170还可形成在凸块下金属层2160上。半导体芯片2120可以是包括主体2121、连接焊盘2122、钝化层(未示出)等的集成电路(IC)。连接构件2140可包括:绝缘层2141;重新分布层2142,形成在绝缘层2141上;及过孔2143,将连接焊盘2122和重新分布层2142彼此电连接。
如上所述,扇出型半导体封装件可具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式。如上所述,在扇入型半导体封装件中,半导体芯片的所有的I/O端子需要设置在半导体芯片的内部。因此,当半导体芯片的尺寸减小时,球的尺寸和节距需要减小,使得在扇入型半导体封装件中可能无法使用标准化的球布局。另一方面,如上所述,扇出型半导体封装件具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式。因此,即使在半导体芯片的尺寸减小的情况下,在扇出型半导体封装件中仍可按照原样使用标准化的球布局,使得扇出型半导体封装件可在不使用单独的中介基板的情况下安装在电子装置的主板上,如下所述。
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图。
参照图8,扇出型半导体封装件2100可通过焊球2170等安装在电子装置的主板2500上。也就是说,如上所述,扇出型半导体封装件2100包括连接构件2140,连接构件2140形成在半导体芯片2120上并且能够使连接焊盘2122重新分布到半导体芯片2120的尺寸的外部的扇出区域,使得可在扇出型半导体封装件2100中按照原样使用标准化的球布局。结果,扇出型半导体封装件2100可在不使用单独的中介基板等的情况下安装在电子装置的主板2500上。
如上所述,由于扇出型半导体封装件可在不使用单独的中介基板的情况下安装在电子装置的主板上,因此扇出型半导体封装件可按照比使用中介基板的扇入型半导体封装件的厚度小的厚度实现。因此,扇出型半导体封装件可被小型化和薄型化。另外,扇出型半导体封装件具有优异的热特性和电特性,使得其特别适合于移动产品。因此,扇出型半导体封装件可按照比使用印刷电路板(PCB)的普通的层叠封装(POP)类型的形式紧凑的形式实现,并且可解决由于翘曲现象的发生而引起的问题。
另一方面,扇出型半导体封装指的是如上所述的用于将半导体芯片安装在电子装置的主板等上并且保护半导体芯片免受外部冲击的影响的封装技术,并且是与诸如中介基板的印刷电路板(PCB)等(具有与扇出型半导体封装件的规格、用途等不同的规格、用途等,并且具有嵌入其中的扇入型半导体封装件)的概念不同的概念。
图9是示出扇出型半导体封装件的示例的示意性截面图。
参照图9,根据示例性实施例的扇出型半导体封装件10A可具有POP结构,该POP结构包括在竖直方向上堆叠的第一半导体封装件100和第二半导体封装件200,并且第二半导体封装件200可堆叠在第一半导体封装件100上。第一半导体封装件100可包括:芯构件110,具有通孔110H;第一半导体芯片120,设置在芯构件110的通孔110H中并具有其上设置有连接焊盘122的有效表面和与该有效表面背对的无效表面;散热构件170,直接结合到第一半导体芯片120的无效表面上并包含碳;第一包封剂130,包封芯构件110的至少一部分和第一半导体芯片120的至少一部分;连接构件140,设置在芯构件110和第一半导体芯片120的有效表面上;背侧布线结构190,设置在第一包封剂130上;钝化层150,设置在连接构件140上;凸块下金属层160,设置在钝化层150的开口中;电连接结构165,设置在钝化层150上并连接到凸块下金属层160;以及无源组件180,设置在钝化层150上。第二半导体封装件200可包括布线基板210、设置在布线基板210上的多个第二半导体芯片220、包封第二半导体芯片220的第二包封剂230和位于布线基板210下方的上连接端子265。
另一方面,在POP结构的情况下,由于半导体芯片在竖直方向上堆叠,因此存在发热加强且半导体芯片的性能劣化的问题。具体地,在诸如AP的片上系统(SoC)的情况下,在执行半导体芯片内部的操作的位置局部地产生热。因此,可通过将散热构件设置在靠近这样的发热位置来有效地实现散热。在根据示例性实施例的扇出型半导体封装件10A中,作为扇出型半导体封装件的第一半导体封装件100可用于安装诸如AP芯片的第一半导体芯片120并在其上安装诸如存储器芯片的第二半导体芯片220,可通过将散热构件170设置在第一半导体芯片120上来确保散热特性。
散热构件170可利用具有优异的散热效果的碳基材料形成,并且可包括例如碳化硅(SiC)、石墨、石墨烯、碳纳米管(CNT)和金属石墨复合材料中的至少一种。石墨烯是利用石墨的单个原子层形成的二维碳六边形网片。散热构件170可利用与具有约2.7ppm/K的热膨胀系数的硅(Si)具有不大于10ppm/K的热膨胀系数(CTE)的差异的材料形成。具体地,散热构件170可利用具有在2ppm/K至10ppm/K的范围中的热膨胀系数的材料形成,并且可具体地利用具有在3ppm/K至9ppm/K的范围中的热膨胀系数的材料形成。例如,不管晶体结构如何,碳化硅(SiC)可具有约3ppm/K至6ppm/K的热膨胀系数,石墨可具有在约1ppm/K至8ppm/K的范围中的热膨胀系数,铜-石墨(Cu-Gr)复合材料可具有在约4ppm/K至9ppm/K的范围中的热膨胀系数。
如上所述,散热构件170可利用能够通过显著减小与主要利用硅形成的第一半导体芯片120的热膨胀系数的差异来防止发生翘曲的材料形成,并且可利用具有比硅的约150W/mK的导热率高的导热率的材料形成。具体地,散热构件170可利用具有在250W/mK至500W/mK的范围中的导热率的材料形成。例如,根据晶体结构,对于单晶体,碳化硅(SiC)可具有在约350W/mK至500W/mK的范围中的导热率,并且对于多晶体,碳化硅(SiC)可具有比单晶体的导热率低的在250W/mK至300W/mK的范围中的导热率。石墨可根据方向具有不同的导热率,但是在水平方向上可具有约500W/mK或更高的导热率,铜-石墨(Cu-Gr)复合材料可具有在约300W/mK至400W/mK的范围中的导热率。
此外,尽管图9中示出了扇出型半导体封装件10A包括第一半导体封装件100和第二半导体封装件200的实施例,但是扇出型半导体封装件仅包括第一半导体封装件也是可行的。
在下文中,将更详细地描述根据示例性实施例的扇出型半导体封装件10A中包括的各个组件。
芯构件110可根据特定材料而提高第一半导体封装件100的刚性,并且可用于确保第一包封剂130的厚度的均匀性。另外,根据示例性实施例的扇出型半导体封装件10A可通过芯构件110而用作POP的一部分。芯构件110可具有通孔110H。第一半导体芯片120可设置在通孔110H中,以与芯构件110分开预定距离。第一半导体芯片120的侧表面可被芯构件110包围。然而,这种形式仅是示例并且可进行各种变型以具有其他形式,并且芯构件110可根据这样的形式执行另外的功能。如果需要,可以省略芯构件110,但是在确保扇出型半导体封装件10A包括芯构件110的本公开中所预期的板级可靠性方面可以是更有利的。
芯构件110可包括芯绝缘层111、设置在芯绝缘层111的背对表面上的布线层112以及穿过芯绝缘层111并将上布线层112和下布线层112彼此连接的芯过孔113。因此,设置在芯绝缘层111的背对表面上的布线层112可通过芯过孔113彼此电连接。
绝缘材料可用作芯绝缘层111的材料。在这种情况下,绝缘材料可以是诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂浸在诸如无机填料和/或玻璃纤维(或玻璃布或玻璃织物)的芯材料中的绝缘材料(例如,半固化片、ABF(Ajinomoto Build-up Film)、FR-4、双马来酰亚胺三嗪(BT)等)。这种芯构件110可用作支撑构件。
布线层112可用于使第一半导体芯片120的连接焊盘122重新分布。布线层112中的每个的材料可以是导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。布线层112可根据它们的对应层的设计而执行各种功能。例如,布线层112可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。这里,信号(S)图案可包括除接地(GND)图案、电力(PWR)图案等之外的各种信号图案(诸如,数据信号图案等)。另外,布线层112可包括过孔焊盘、布线焊盘、连接端子焊盘等。
芯过孔113可将形成在不同层上的布线层112彼此电连接,从而在芯构件110中形成电路径。芯过孔113中的每个的材料可以是导电材料。芯过孔113中的每个可完全填充有导电材料,或者导电材料可沿着通路孔中的每个的壁形成。另外,芯过孔113中的每个可具有现有技术中已知的任意形状,诸如锥形形状、圆柱形形状等。
第一半导体芯片120可以是按照在单个芯片中集成数量为数百至数百万或更多的元件而设置的集成电路(IC)。例如,第一半导体芯片120可以是诸如中央处理器(例如,CPU)、图形处理器(例如,GPU)、现场可编程门阵列(FPGA)、数字信号处理器、密码处理器、微处理器、微控制器等的处理器芯片(更具体地,应用处理器(AP)),但是不限于此。也就是说,IC可以是诸如模数转换器、专用集成IC(ASIC)等的逻辑芯片,或者是诸如易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM和闪存)等的存储器芯片,但不限于此。另外,上述元件还可彼此结合和设置。
第一半导体芯片120的有效表面指第一半导体芯片120的其上设置有连接焊盘122的表面,第一半导体芯片120的无效表面指与有效表面背对的表面。第一半导体芯片120可基于有效晶圆形成。在这种情况下,主体121的基体材料可以是硅(Si)、锗(Ge)、砷化镓(GaAs)等。可在主体121上形成各种电路。连接焊盘122可将第一半导体芯片120电连接到其他组件,并且诸如铝(Al)等的导电材料可用作连接焊盘122中的每个的材料,而没有具体限制。使连接焊盘122暴露的钝化层123可形成在主体121上,并且钝化层123可以是氧化物层、氮化物层等或者是氧化物层和氮化物层的双层。连接焊盘122的下表面可通过钝化层123而相对于第一包封剂130的下表面具有台阶。结果,可在一定程度上防止第一包封剂130渗入到连接焊盘122的下表面中的现象。绝缘层(未示出)等也可进一步设置在其他所需位置中。
散热构件170可直接结合到第一半导体芯片120。散热构件170的厚度可增大省略的粘合层的厚度。将参照图10A至图10C更详细地描述直接结合。相应地,散热构件170可与第一半导体芯片120的整个无效表面直接接触,并且可与第一半导体芯片120一起设置在通孔110H中。散热构件170可在平面上具有与第一半导体芯片120的尺寸相同的尺寸。散热构件170可具有与第一半导体芯片120的第一厚度T1相同或比第一半导体芯片120的第一厚度T1小的第二厚度T2。例如,第一厚度T1和第二厚度T2可均是第一半导体芯片120和散热构件170的总厚度T3的一半,但不限于此。
第一包封剂130可保护芯构件110、第一半导体芯片120等。第一包封剂130的包封形式没有具体限制,而可以是第一包封剂130包围第一半导体芯片120的至少部分的形式。例如,第一包封剂130可覆盖芯构件110的至少一部分和第一半导体芯片120的无效表面的至少一部分,并填充通孔110H的壁与第一半导体芯片120的侧表面之间的空间的至少部分。另一方面,第一包封剂130可填充通孔110H,以如此根据特定材料用作用于固定第一半导体芯片120的粘合剂并减少第一半导体芯片120的屈曲。第一包封剂130的材料没有具体限制。例如,绝缘材料可用作第一包封剂130的材料。在这种情况下,绝缘材料可以是诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合或与无机填料一起浸在诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料中的树脂(例如,半固化片、ABF(Ajinomoto Build-up Film)、FR-4、双马来酰亚胺三嗪(BT)等)。可选地,PID树脂也可用作绝缘材料。
连接构件140可使第一半导体芯片120的连接焊盘122重新分布。第一半导体芯片120的具有各种功能的数十至数百的连接焊盘122可通过连接构件140重新分布,并且可根据功能通过电连接结构165物理连接和/或电连接到外部。连接构件140可包括:第一绝缘层141a,设置在芯构件110和第一半导体芯片120的有效表面上;第一重新分布层142a,设置在第一绝缘层141a上;第一过孔143a,将第一重新分布层142a与第一半导体芯片120的连接焊盘122彼此连接;第二绝缘层141b,设置在第一绝缘层141a上;第二重新分布层142b,设置在第二绝缘层141b上;第二过孔143b,穿过第二绝缘层141b并将第一重新分布层142a与第二重新分布层142b彼此连接;第三绝缘层141c,设置在第二绝缘层141b上;第三重新分布层142c,设置在第三绝缘层141c上;以及第三过孔143c,穿过第三绝缘层141c并将第二重新分布层142b与第三重新分布层142c彼此连接。第一重新分布层142a、第二重新分布层142b和第三重新分布层142c可电连接到第一半导体芯片120的连接焊盘122。
绝缘材料可用作绝缘层141a、141b和141c中的每个的材料。在这种情况下,除了如上所述的绝缘材料之外,诸如PID树脂的感光绝缘材料也可用作绝缘材料。也就是说,绝缘层141a、141b和141c可以是感光绝缘层。当绝缘层141a、141b和141c具有感光性质时,绝缘层141a、141b和141c可形成为具有较小的厚度,并且可更容易地实现过孔143a、143b和143c的精细节距。绝缘层141a、141b和141c可以是包括绝缘树脂和无机填料的感光绝缘层。当绝缘层141a、141b和141c是多层时,绝缘层141a、141b和141c的材料可彼此相同,并且如果需要,也可彼此不同。当绝缘层141a、141b和141c是多层时,绝缘层141a、141b和141c可根据工艺彼此一体化,使得它们之间的边界也可以是不明显的。可形成数量比图中所示的绝缘层的数量多的绝缘层。
重新分布层142a、142b和142c可用于使连接焊盘122大体上重新分布。重新分布层142a、142b和142c中的每个的材料可以是导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。例如,形成重新分布层142a、142b和142c的种子金属层和镀覆金属层可利用铜(Cu)或它的合金形成,并且结合金属层可利用钛(Ti)或它的合金形成。然而,第二结合金属层可以是可选构造,并且根据示例性实施例可省略。重新分布层142a、142b和142c可根据它们的对应层的设计而执行各种功能。例如,重新分布层142a、142b和142c可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。这里,信号(S)图案可包括除接地(GND)图案、电力(PWR)图案等之外的各种信号图案(诸如,数据信号图案等)。另外,重新分布层142a、142b和142c可包括过孔焊盘图案、电连接结构焊盘图案等。
过孔143a、143b和143c可相应地将形成在不同层上的重新分布层142a、142b和142c、连接焊盘122等彼此电连接,从而在扇出型半导体封装件10A中形成电路径。过孔143a、143b和143c中的每个的材料可以是导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。例如,形成过孔143a、143b和143c的种子金属层和镀覆金属层可利用铜(Cu)或它的合金形成,并且结合金属层可利用钛(Ti)或它的合金形成。过孔143a、143b和143c中的每个可完全填充有导电材料,或者导电材料也可沿着通路孔中的每个的壁形成。另外,过孔143a、143b和143c中的每个可具有现有技术中已知的所有形状,诸如锥形形状、圆柱形形状等。
背侧布线结构190可包括设置在第一包封剂130上的背侧重新分布层192和穿过第一包封剂130的背侧过孔193。背侧过孔193可将背侧重新分布层192与芯构件110的芯过孔113彼此连接。背侧重新分布层192和背侧过孔193中的每一者的材料可以是导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。背侧重新分布层192可根据设计而执行各种功能。例如,背侧重新分布层192可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。背侧过孔193中的每个的形状可以是与连接构件140的过孔143a、143b和143c在不同方向上的锥形形状。
钝化层150可保护连接构件140免受外部物理或化学损坏。钝化层150可具有使连接构件140的第三重新分布层142c的至少部分暴露的开口。形成在钝化层150中的开口的数量可以是数十至数千。钝化层150的材料没有具体限制。例如,绝缘材料可用作钝化层150的材料。在这种情况下,绝缘材料可以是诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合或与无机填料一起浸在诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料中的树脂(例如,半固化片、ABF(Ajinomoto Build-upFilm)、FR-4、双马来酰亚胺三嗪(BT)等)。可选地,也可使用阻焊剂。背侧钝化层155也可形成在背侧布线结构190上。
凸块下金属层160可改善电连接结构165的连接可靠性,从而改善扇出型半导体封装件10A的板级可靠性。凸块下金属层160可连接到连接构件140的通过钝化层150的开口暴露的第三重新分布层142c。可通过已知的金属化方法,使用诸如金属的已知导电材料在钝化层150的开口中形成凸块下金属层160,但不限于此。
电连接结构165可将扇出型半导体封装件10A物理连接和/或电连接到外部。例如,扇出型半导体封装件10A可通过电连接结构165安装在电子装置的主板上。电连接结构165中的每个可利用例如焊料等的导电材料形成。然而,这仅是示例,并且电连接结构165中的每个的材料不具体限于此。电连接结构165中的每个可以是焊盘、球、引脚等。电连接结构165可形成为多层结构或单层结构。当电连接结构165形成为多层结构时,电连接结构165可以包括铜(Cu)柱和焊料。当电连接结构165形成为单层结构时,电连接结构165可包括锡-银焊料或铜(Cu)。然而,这仅是示例,电连接结构165不限于此。
电连接结构165的数量、间距、设置形式等不受具体地限制,而是可根据设计细节进行充分地修改。例如,电连接结构165可按照数十至数千的数量设置,或者可按照数十至数千或更多或者数十至数千或更少的数量设置。当电连接结构165为焊球时,电连接结构165可覆盖凸块下金属层160的延伸到钝化层150的一个表面上的侧表面,且连接可靠性可以是更加优异的。
电连接结构165中的至少一个可设置在第一半导体芯片120的扇出区域中。扇出型封装件可具有比扇入型封装件的可靠性优异的可靠性,可实现多个I/O端子,并且可容易执行3D互连。另外,与球栅阵列(BGA)封装件、栅格阵列(LGA)封装件等相比,扇出型封装件可被制造为具有小的厚度,且可具有价格竞争力。
无源组件180可设置在钝化层150的下表面上,并且可设置在电连接结构165之间。无源组件180可电连接到第三重新分布层142c。无源组件180可包括例如包括电感器、电容器等的表面安装技术(SMT)组件。
另一方面,尽管未在附图中示出,但是如果需要,可在通孔110H的壁上形成金属薄膜,从而散热或阻截电磁波。另外,如果需要,可在通孔110H中设置执行彼此相同或彼此不同的功能的多个半导体芯片。此外,如果需要,可在通孔110H中设置单独的无源组件,诸如电感器、电容器等。
布线基板210可以是诸如中介基板的印刷电路板(PCB)。布线基板210可包括绝缘层和形成在绝缘层中的导电布线层。钝化层等可形成在布线基板210的背对表面上。根据示例性实施例,可不同地改变布线基板210的结构和形式。另外,在示例性实施例中,中介基板可进一步设置在布线基板210与第一半导体封装件100之间。
第二半导体芯片220可包括彼此并列堆叠的多个半导体芯片221、222、223和224。第二半导体芯片220可通过粘合构件225附着到布线基板210或下侧的第二半导体芯片220。第二半导体芯片220可通过连接到连接焊盘221P的导线240电连接到布线基板210的布线层。然而,在示例性实施例中,第二半导体芯片220也可以是结合到布线基板210上的倒装芯片。
第二半导体芯片220也可以是按照在单个芯片中集成数量为数百至数百万或更多的元件而设置的集成电路(IC)。IC可以是诸如易失性存储器(诸如DRAM)、非易失性存储器(诸如ROM和闪存)等的存储器芯片,但不限于此。第二半导体芯片220的有效表面指第二半导体芯片220的其上设置有连接焊盘221P的表面,第二半导体芯片220的无效表面指与有效表面背对的表面。然而,根据示例性实施例,第二半导体芯片220也可以以面朝下的形式设置。第二半导体芯片220可基于有效晶圆形成。在这种情况下,基体材料可以是硅(Si)、锗(Ge)、砷化镓(GaAs)等。可在第二半导体芯片220中形成各种电路。连接焊盘221P可将第二半导体芯片220电连接到其他组件,并且诸如铝(Al)等的导电材料可用作连接焊盘221P中的每个的材料。
粘合构件225可容易地将第二半导体芯片220的无效表面附着到下侧的第二半导体芯片220或布线基板210的上表面。粘合构件225可以是诸如裸片附着膜(DAF)的带。粘合构件225的材料不受具体限制。粘合构件225可包括例如环氧树脂组分,但不限于此。可通过粘合构件225更稳定地安装第二半导体芯片220,从而可提高可靠性。
第二包封剂230可保护第二半导体芯片220。第二包封剂230的包封形式没有具体限制,而可以是第二包封剂230包围第二半导体芯片220的至少部分的形式。例如,第二包封剂230可覆盖第二半导体芯片220的有效表面的至少部分,并且还覆盖第二半导体芯片220的侧表面的至少部分。第二包封剂230可包括绝缘材料。第二包封剂230的绝缘材料可以是光可成像环氧树脂(PIE)、PID等。然而,绝缘材料不限于此。也就是说,包括无机填料和绝缘树脂的材料可用作绝缘材料,例如诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂或具有浸在热固性树脂或热塑性树脂中的诸如无机填料的增强材料的树脂(更具体地,ABF等)也可用作绝缘材料。另外,也可使用诸如环氧塑封料(EMC)等的已知模制材料。可选地,热固性树脂或热塑性树脂浸在诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料和/或无机填料中的材料也可用作绝缘材料。
上连接端子265可使布线基板210和背侧布线结构190彼此电连接。上连接端子265可以介于布线基板210的布线层与背侧布线结构190的背侧重新分布层192之间。上连接端子265中的每个可利用例如焊料等的导电材料形成。然而,这仅是示例,并且上连接端子265中的每个的材料不具体限于此。上连接端子265中的每个可以是焊盘、球、引脚等。
图10A至图10C是将散热构件结合到第一半导体芯片的工艺的示例的示意图。
参照图10A,可对第一半导体芯片120的无效表面120S和散热构件170的下表面170S执行抛光工艺,第一半导体芯片120的无效表面120S和散热构件170的下表面170S彼此结合。抛光工艺可以是例如化学机械抛光(CMP)工艺。如所示的,可使用包括抛光头320和附着到抛光头320的抛光垫310的抛光机300来执行抛光工艺。由于第一半导体芯片120和散热构件170以原子级结合,因此可将第一半导体芯片120和散热构件170抛光为具有约1nm的低表面粗糙度Ra。
参照图10B,可对第一半导体芯片120的无效表面120S和散热构件170的下表面170S执行活化工艺(activation process)。活化工艺可以是用于增加表面能态的工艺。例如,活化工艺可以是使用诸如氩(Ar)的惰性气体的离子对第一半导体芯片120的无效表面120S和散热构件170的下表面170S施加离子轰击从而破坏表面上的原子键的工艺。
参照图10C,可执行将散热构件170的下表面170S紧密接触并按压到第一半导体芯片120的无效表面120S上的工艺。通过按压工艺,第一半导体芯片120的无效表面120S的原子和散热构件170的下表面170S的原子可彼此紧密接触并且可以以原子级形成键。在按压过程中,例如,可施加约100kN的压力,但是压力可根据第一半导体芯片120和散热构件170的尺寸等而改变。
通过如上所述的工艺,第一半导体芯片120和散热构件170可彼此直接结合,而无需具有介于它们之间的单独粘合层。因此,可简化半导体封装件的结构和工艺,并且可更有效地排放从第一半导体芯片120产生的热。
图11是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图11,在根据本公开中的另一示例性实施例的扇出型半导体封装件10B中,散热构件170可包括在竖直方向上堆叠的第一散热层172和第二散热层174。第一散热层172和第二散热层174可具有不同的厚度,并且可利用不同的材料形成。例如,第一散热层172可包括具有各向异性的导热率的材料并且材料被设置为使得具有较低导热率的轴沿着从第一半导体芯片120的有效表面到第一半导体芯片120的无效表面的方向。例如,下侧的第一散热层172可包括石墨,第二散热层174可包括铜-石墨(Cu-Gr)复合材料。石墨可通过碳原子的六边形网结构而具有水平方向上的导热率高而竖直方向上的导热率低的导热率的各向异性。因此,可通过第一散热层172在与第一半导体芯片120相邻的区域中确保水平方向上的高导热率,并且可通过第二散热层174确保竖直方向(即,向上方向)上的导热率。第一散热层172的厚度T4可小于第二散热层174的厚度T5,但不限于此。除了上述构造之外的其他构造和制造方法的描述与根据上述示例的扇出型半导体封装件10A中描述的构造和制造方法重复,因此被省略。
图12是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图12,在根据本公开中的另一示例性实施例的扇出型半导体封装件10C中,除了背侧重新分布层192和背侧过孔193之外,背侧布线结构190还可包括散热过孔195。散热过孔195可穿过第一包封剂130以使背侧重新分布层192与散热构件170彼此连接。通过散热过孔195,从第一半导体芯片120产生的热可更有效地从第一半导体封装件100向上排放。可向散热过孔195施加电信号或者可不向散热过孔195施加电信号。在电信号未施加到散热过孔195的情况下,连接到散热过孔195的背侧重新分布层192可用作散热图案层。散热过孔195中的每个的材料可与背侧过孔193中的每个的材料相同,并且可与散热构件170的材料不同。散热过孔195中的每个的材料可以是导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。此外,在图12中的实施例中,背侧布线结构190包括背侧重新分布层192、背侧过孔193和散热过孔195,但是如果必要,背侧布线结构也可仅包括背侧重新分布层和散热过孔。除了上述构造之外的其他构造和制造方法的描述与上述的构造和制造方法重复,因此被省略。
图13是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图13,在根据本公开中的另一示例性实施例的扇出型半导体封装件10D中,芯构件110可包括:第一绝缘层111a,与连接构件140接触;第一布线层112a,与连接构件140接触并嵌入在第一绝缘层111a中;第二布线层112b,设置在第一绝缘层111a的与第一绝缘层111a的嵌入有第一布线层112a的一个表面背对的另一表面上;第二绝缘层111b,设置在第一绝缘层111a上并覆盖第二布线层112b;以及第三布线层112c,设置在第二绝缘层111b上。第一布线层112a、第二布线层112b和第三布线层112c可电连接到连接焊盘122。第一布线层112a和第二布线层112b以及第二布线层112b和第三布线层112c可分别通过穿过第一绝缘层111a的第一过孔113a和穿过第二绝缘层111b的第二过孔113b彼此电连接。
当第一布线层112a嵌入在第一绝缘层111a中时,由于第一布线层112a的厚度而产生的台阶可显著减小,并且连接构件140的绝缘距离可因此变得恒定。也就是说,从连接构件140的第一重新分布层142a到第一绝缘层111a的下表面的距离与从连接构件140的第一重新分布层142a到第一半导体芯片120的连接焊盘122的距离之间的差可小于第一布线层112a的厚度。因此,连接构件140的高密度布线设计可以是容易的。
芯构件110的第一布线层112a的下表面可设置在第一半导体芯片120的连接焊盘122的下表面上方的高度。此外,连接构件140的第一重新分布层142a与芯构件110的第一布线层112a之间的距离可大于连接构件140的第一重新分布层142a与第一半导体芯片120的连接焊盘122之间的距离。原因在于:第一布线层112a可凹入到第一绝缘层111a中。如上所述,当第一布线层112a凹入到第一绝缘层111a中使得第一绝缘层111a的下表面与第一布线层112a的下表面之间具有台阶时,可防止第一包封剂130的材料渗入而污染第一布线层112a的现象。芯构件110的第二布线层112b可设置在第一半导体芯片120的有效表面与散热构件170的上表面之间。芯构件110可以以与第一半导体芯片120与散热构件170的总厚度对应的厚度形成。因此,形成在芯构件110中的第二布线层112b可设置在第一半导体芯片120的有效表面与散热构件170的上表面之间的高度。
芯构件110的布线层112a、112b和112c的厚度可大于连接构件140的重新分布层142a、142b和142c的厚度。由于芯构件110的厚度可大于第一半导体芯片120的厚度,因此布线层112a、112b和112c可根据芯构件110的规格而以较大的尺寸形成。另一方面,为了薄型化,连接构件140的重新分布层142a、142b和142c可以以比布线层112a、112b和112c的尺寸相对小的尺寸形成。
绝缘层111a和111b中的每个的材料没有具体限制。例如,绝缘材料可用作绝缘层111a和111b的材料。在这种情况下,绝缘材料可以是诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合或与无机填料一起浸在诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料中的树脂(例如,半固化片、ABF(AjinomotoBuild-up Film)、FR-4、双马来酰亚胺三嗪(BT)等)。可选地,PID树脂也可用作绝缘材料。
布线层112a、112b和112c可用于使第一半导体芯片120的连接焊盘122重新分布。布线层112a、112b和112c中的每个的材料可以是导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。布线层112a、112b和112c可根据它们的对应层的设计而执行各种功能。例如,布线层112a、112b和112c可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。这里,信号(S)图案可包括除接地(GND)图案、电力(PWR)图案等之外的各种信号图案(例如,数据信号图案等)。另外,布线层112a、112b和112c可包括过孔焊盘、布线焊盘、连接端子焊盘等。
过孔113a和113b可将形成在不同层上的布线层112a、112b和112c彼此电连接,从而在芯构件110中形成电路径。过孔113a和113b中的每个的材料可以是导电材料。过孔113a和113b中的每个可完全填充有导电材料,或者导电材料也可沿着通路孔中的每个的壁形成。另外,过孔113a和113b中的每个可具有现有技术中已知的全部形状,诸如锥形形状、圆柱形形状等。当形成用于第一过孔113a的孔时,第一布线层112a的焊盘中的一些焊盘可用作止动部,因此在第一过孔113a中的每个具有上表面的宽度大于下表面的宽度的锥形形状的工艺中可以是有利的。在这种情况下,第一过孔113a可与第二布线层112b的焊盘图案一体化。另外,当形成用于第二过孔113b的孔时,第二布线层112b的焊盘中的一些焊盘可用作止动部,因此在使第二过孔113b中的每个具有上表面的宽度大于下表面的宽度的锥形形状的工艺中可以是有利的。在这种情况下,第二过孔113b可与第三布线层112c的焊盘图案一体化。
其他构造(例如,参照图9描述的散热构件170的内容)也可应用于根据另一示例性实施例的扇出型半导体封装件10D,并且其详细描述与上述扇出型半导体封装件10A中描述的那些大体上相同。因此,将省略其详细描述。
图14是示出扇出型半导体封装件的另一示例的示意性截面图。
参照图14,在根据本公开中的另一示例性实施例的扇出型半导体封装件10E中,芯构件110可包括:第一绝缘层111a;第一布线层112a和第二布线层112b,分别设置在第一绝缘层111a的背对表面上;第二绝缘层111b,设置在第一绝缘层111a上并覆盖第一布线层112a;第三布线层112c,设置在第二绝缘层111b上;第三绝缘层111c,设置在第一绝缘层111a上并覆盖第二布线层112b;以及第四布线层112d,设置在第三绝缘层111c上。第一布线层112a、第二布线层112b、第三布线层112c和第四布线层112d可电连接到连接焊盘122。由于芯构件110可包括较多数量的布线层112a、112b、112c和112d,因此可进一步简化连接构件140。因此,可抑制根据在形成连接构件140的工艺中发生的缺陷导致的良率的降低。另一方面,第一布线层112a和第二布线层112b可通过穿过第一绝缘层111a的第一过孔113a彼此电连接,第一布线层112a和第三布线层112c可通过穿过第二绝缘层111b的第二过孔113b彼此电连接,第二布线层112b和第四布线层112d可通过穿过第三绝缘层111c的第三过孔113c彼此电连接。
第一绝缘层111a的厚度可大于第二绝缘层111b的厚度和第三绝缘层111c的厚度。第一绝缘层111a可大体上相对厚以保持刚性,并且可引入第二绝缘层111b和第三绝缘层111c以形成较多数量的布线层112c和112d。第一绝缘层111a可包括与第二绝缘层111b和第三绝缘层111c的绝缘材料不同的绝缘材料。例如,第一绝缘层111a可以是例如包括芯材料、填料和绝缘树脂的半固化片,第二绝缘层111b和第三绝缘层111c可以是包括填料和绝缘树脂的PID膜或ABF膜。然而,第一绝缘层111a以及第二绝缘层111b和第三绝缘层111c的材料不限于此。类似地,穿过第一绝缘层111a的第一过孔113a的平均直径可分别大于穿过第二绝缘层111b的第二过孔113b和穿过第三绝缘层111c的第三过孔113c的平均直径。
芯构件110的第三布线层112c的下表面可设置在第一半导体芯片120的连接焊盘122的下表面下方的高度。另外,连接构件140的第一重新分布层142a与芯构件110的第三布线层112c之间的距离可小于连接构件140的第一重新分布层142a与第一半导体芯片120的连接焊盘122之间的距离。原因在于:第三布线层112c可以以突出的形式设置在第二绝缘层111b上,从而与连接构件140接触。芯构件110的第一布线层112a和第二布线层112b可设置在第一半导体芯片120的有效表面与散热构件170的上表面之间。芯构件110可以以与第一半导体芯片120与散热构件170的总厚度对应的厚度形成。因此,形成在芯构件110中的第一布线层112a和第二布线层112b可设置在第一半导体芯片120的有效表面与散热构件170的上表面之间的高度。
芯构件110的布线层112a、112b、112c和112d的厚度可大于连接构件140的重新分布层142a、142b和142c的厚度。由于芯构件110的厚度可大于第一半导体芯片120的厚度,因此布线层112a、112b、112c和112d也可以以较大的尺寸形成。另一方面,为了纤薄型化,连接构件140的重新分布层142a、142b和142c可以以相对小的尺寸形成。
其他构造(例如,参照图9描述的散热构件170的内容)也可应用于根据另一示例性实施例的扇出型半导体封装件10E,并且其详细描述与上述扇出型半导体封装件10A中描述的那些大体上相同。因此,将省略其详细描述。
图15A至图15C是示意性地示出根据示例性实施例的扇出型半导体封装件的散热效果的曲线图。
参照图15A,示出了对于在如图9中所示的扇出型半导体封装件10A中具有不同条件的散热构件170的比较示例1至4和发明示例的AP结温的模拟结果。AP结温指第一半导体芯片120(为应用处理器(AP))中的热点处的温度。在比较示例1的情况下,第一半导体芯片120的厚度为300μm,并且未设置散热构件170。在比较示例2的情况下,第一半导体芯片120的厚度为290μm,并且散热构件170利用厚度为10μm的铜(Cu)形成。在比较示例3的情况下,第一半导体芯片120的厚度为150μm,并且散热构件170利用厚度为130μm的铜(Cu)形成并且通过具有20μm的厚度的裸片附着膜(DAF)附着到第一半导体芯片120。在比较示例4的情况下,第一半导体芯片120的厚度为150μm,并且散热构件170利用厚度为130μm的单晶碳化硅(SiC)形成并且通过具有20μm的厚度的裸片附着膜(DAF)附着到第一半导体芯片120。在发明示例的情况下,第一半导体芯片120的厚度为150μm,并且散热构件170利用厚度为150μm的单晶碳化硅(SiC)形成并且直接附着到第一半导体芯片120。
如所示的,与比较示例1中那样未设置散热构件170的结构相比,在如比较示例2中那样设置散热构件170的情况下,结温低,并且在如比较示例3中那样增大散热构件170的厚度的情况下,结温也降低。在与比较示例3和比较示例4相同的条件下,使用碳化硅(SiC)的情况的结温可低于使用铜(Cu)的情况的结温。另外,在如发明示例中那样散热构件170直接结合到第一半导体芯片120的情况下,结温可示出约67℃的最低温度。这是因为由于省略了诸如DAF的粘合层而提高散热效率,且通过使散热构件170的厚度增大省略的粘合层的厚度而提高散热特性。
参照图15B,示出了对于在如图11中所示的扇出型半导体封装件10B中具有不同条件的散热构件170的比较示例和发明示例的AP结温的模拟结果。比较示例是针对于第一半导体芯片120的厚度为300μm并且未设置散热构件170的情况,发明示例是针对于第一半导体芯片120的厚度为150μm并且散热构件170包括利用具有2μm的厚度的石墨形成的第一散热层172和利用具有148μm的厚度的铜-石墨复合材料形成的第二散热层174的情况。在发明示例的情况下,示出了通过在500W/mK至10000W/mK的范围中改变石墨在水平方向上的导热率的值的同时模拟AP结温而获得的结果。如上所述的石墨的导热率可根据测量方向、石墨的厚度、形成方法等而变化。
如所示的,比较示例示出了约75℃的结温,但发明示例示出了在66.9℃至68.6℃的范围中的结温。因此,可以看出,在发明示例的情况下,通过使用如上所述结构的散热构件170改善了散热特性。
参照图15C,示出了对于在如图9中所示的扇出型半导体封装件10A中具有不同条件的散热构件170的比较示例和发明示例的AP结温的模拟结果。比较示例1是针对于第一半导体芯片120的厚度为160μm并且未设置散热构件170的情况,发明示例1是针对于第一半导体芯片120的厚度为158μm并且散热构件170利用具有2μm的厚度的石墨形成的情况。比较示例2是针对于第一半导体芯片120的厚度为300μm并且未设置散热构件170的情况,发明示例2是针对于第一半导体芯片120的厚度为298μm并且散热构件170利用具有2μm的厚度的石墨形成的情况。在发明示例的情况下,示出了通过在500W/mK至10000W/mK的范围中改变石墨在水平方向上的导热率的值的同时模拟AP结温而获得的结果。
如所示的,比较示例1示出了最高结温,发明示例1示出了比比较示例1的结温低的结温。比较示例2示出比比较示例1的结温低的结温,发明示例2示出比比较示例2的结温低的结温。如上所述,在第一半导体芯片120的厚度相对薄的情况下,出现相对高的结温。然而,随着用作散热构件170的材料的导热率变大,根据第一半导体芯片120的厚度的结温的差减小。因此,第一半导体芯片120的厚度对散热效果有影响,但是在第一半导体芯片120的厚度相对薄而散热构件170的导热率高的情况下,可以看出,可出现与第一半导体芯片120的厚度厚的情况接近的散热效果。
这里,与附图的截面相关的下侧、下部、下表面等用来指朝向扇出型半导体封装件的安装表面的方向,而上侧、上部、上表面等用来指与该方向相反的方向。然而,这些方向是为了便于解释而定义的,权利要求不受如上所述定义的方向的具体限制。
说明书中的组件与另一组件的“连接”的含义包括通过粘结层的间接连接以及两个组件之间的直接连接。另外,“电连接”意味着包括物理连接以及物理断开的概念。可理解的是,当利用“第一”和“第二”来提及元件时,该元件不会由此受限。它们可仅用于将元件与其他元件相区分的目的,并且可不限制元件的顺序或重要性。在一些情况下,在不脱离本公开的范围的情况下,第一组件可被称为第二组件,类似地,第二组件也可被称为第一组件。
这里使用的术语“示例性实施例”不是指相同的示例性实施例,而是被提供来强调与另一示例性实施例的特定特征或特性不同的特定特征或特性。然而,这里提供的示例性实施例被认为能够通过彼此全部或部分组合来实现。例如,除非其中提供了相反或相矛盾的描述,否则即使特定示例性实施例中描述的一个元件未在另一示例性实施例中描述,该元件仍可被理解为与另一示例性实施例相关的描述。
这里使用的术语仅用于描述示例性实施例,而并不限制本公开。在这种情况下,除非在上下文中另外解释,否则单数形式也包括复数形式。
如以上阐述的,根据本公开中的示例性实施例,可提供一种其散热特性被提高的扇出型半导体封装件。
虽然以上已经示出并且描述了示例性实施例,但是对本领域技术人员将显而易见的是,在不脱离由所附的权利要求限定的本发明的范围的情况下,可做出修改和变形。
Claims (18)
1.一种扇出型半导体封装件,包括:
芯构件,具有通孔;
半导体芯片,设置在所述芯构件的所述通孔中并具有设置有连接焊盘的有效表面和设置为与所述有效表面背对的无效表面;
散热构件,直接结合到所述半导体芯片的所述无效表面;
包封剂,包封所述半导体芯片的至少一部分;以及
连接构件,设置在所述半导体芯片的所述有效表面上并包括电连接到所述半导体芯片的连接焊盘的重新分布层。
2.根据权利要求1所述的扇出型半导体封装件,其中,所述散热构件包括碳化硅、石墨和金属-石墨复合材料中的至少一种。
3.根据权利要求1所述的扇出型半导体封装件,其中,所述散热构件具有在2ppm/K至10ppm/K的范围中的热膨胀系数。
4.根据权利要求1所述的扇出型半导体封装件,其中,所述散热构件在平面上具有与所述半导体芯片的尺寸相同的尺寸并与所述半导体芯片的整个无效表面直接接触。
5.根据权利要求1所述的扇出型半导体封装件,其中,所述散热构件位于所述通孔中。
6.根据权利要求1所述的扇出型半导体封装件,其中,所述散热构件包括顺次地堆叠在所述半导体芯片上的第一散热层和第二散热层。
7.根据权利要求6所述的扇出型半导体封装件,其中,所述第一散热层包括石墨,并且
所述第二散热层包括金属-石墨复合材料。
8.根据权利要求1所述的扇出型半导体封装件,其中,所述散热构件具有比硅的导热率高的导热率。
9.根据权利要求8所述的扇出型半导体封装件,其中,所述散热构件具有在从250W/mK至500W/mK的范围中的导热率。
10.根据权利要求1所述的扇出型半导体封装件,其中,所述散热构件的厚度等于或小于所述半导体芯片的厚度。
11.根据权利要求1所述的扇出型半导体封装件,所述扇出型半导体封装件还包括:
背侧重新分布层,设置在所述包封剂上;以及
散热过孔,穿过所述包封剂并将所述背侧重新分布层和所述散热构件彼此连接。
12.根据权利要求1所述的扇出型半导体封装件,所述扇出型半导体封装件还包括附着到所述连接构件的下表面的无源组件。
13.根据权利要求1所述的扇出型半导体封装件,其中,所述芯构件包括:第一芯绝缘层;第一布线层,与所述连接构件接触并嵌入在所述第一芯绝缘层中;以及第二布线层,设置在所述第一芯绝缘层的与嵌入有所述第一布线层的一个表面背对的另一表面上,并且
所述第一布线层和所述第二布线层电连接到所述连接焊盘。
14.根据权利要求1所述的扇出型半导体封装件,其中,所述芯构件包括第一芯绝缘层以及设置在所述第一芯绝缘层的背对表面上的第一布线层和第二布线层,并且
所述第一布线层和所述第二布线层电连接到所述连接焊盘。
15.根据权利要求1所述的扇出型半导体封装件,其中,所述散热构件包括:
第一散热层,直接结合到所述半导体芯片的无效表面,所述第一散热层包括具有各向异性的导热率的材料并且所述材料被设置为使得具有较低导热率的轴沿着从所述有效表面到所述无效表面的方向;以及
第二散热层,直接结合到所述第一散热层。
16.根据权利要求1所述的扇出型半导体封装件,其中,所述散热构件包括:
第一散热层,包括石墨并直接结合到所述无效表面,所述第一散热层被设置为使得石墨的片沿着从所述半导体芯片的有效表面延伸到所述半导体芯片的无效表面的方向堆叠;以及
第二散热层,包括金属-石墨复合物并设置在所述第一散热层上。
17.一种扇出型半导体封装件,包括:
第一半导体封装件,包括:芯构件,具有通孔;第一半导体芯片,设置在所述芯构件的所述通孔中并具有设置有连接焊盘的有效表面和设置为与所述有效表面背对的无效表面;散热构件,直接结合到所述第一半导体芯片的无效表面;第一包封剂,包封所述第一半导体芯片的至少一部分;及连接构件,设置在所述第一半导体芯片的有效表面上并包括电连接到所述第一半导体芯片的连接焊盘的重新分布层;以及
第二半导体封装件,包括:布线基板,设置在所述第一半导体封装件上并通过连接端子电连接到所述连接构件;至少一个第二半导体芯片,设置在所述布线基板上;及第二包封剂,包封所述第二半导体芯片的至少一部分。
18.根据权利要求17所述的扇出型半导体封装件,其中,所述散热构件具有在2ppm/K至10ppm/K的范围中的热膨胀系数。
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US20190333837A1 (en) | 2019-10-31 |
TW201946238A (zh) | 2019-12-01 |
KR20190124892A (ko) | 2019-11-06 |
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