CN110289266A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN110289266A CN110289266A CN201810939441.6A CN201810939441A CN110289266A CN 110289266 A CN110289266 A CN 110289266A CN 201810939441 A CN201810939441 A CN 201810939441A CN 110289266 A CN110289266 A CN 110289266A
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- 230000005611 electricity Effects 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 claims description 112
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Classifications
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018051485A JP2019165089A (ja) | 2018-03-19 | 2018-03-19 | 半導体装置 |
JP2018-051485 | 2018-03-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110289266A true CN110289266A (zh) | 2019-09-27 |
CN110289266B CN110289266B (zh) | 2023-10-27 |
Family
ID=67904643
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810939441.6A Active CN110289266B (zh) | 2018-03-19 | 2018-08-17 | 半导体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10833096B2 (zh) |
JP (1) | JP2019165089A (zh) |
CN (1) | CN110289266B (zh) |
TW (1) | TWI670833B (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110140204B (zh) * | 2016-09-21 | 2023-04-04 | 铠侠股份有限公司 | 半导体装置及其制造方法 |
JP2020047786A (ja) * | 2018-09-19 | 2020-03-26 | キオクシア株式会社 | 半導体記憶装置 |
JP7313996B2 (ja) | 2019-09-11 | 2023-07-25 | 株式会社アルファ | 車両のハンドル装置 |
KR20210115646A (ko) | 2020-03-16 | 2021-09-27 | 삼성전자주식회사 | 반도체 메모리 장치 및 이의 제조 방법 |
CN111886696B (zh) | 2020-06-12 | 2021-09-14 | 长江存储科技有限责任公司 | 具有漏极选择栅极切口的三维存储器器件及其形成方法 |
JP2022047770A (ja) * | 2020-09-14 | 2022-03-25 | キオクシア株式会社 | 半導体記憶装置及び半導体記憶装置の製造方法 |
JP2022051007A (ja) | 2020-09-18 | 2022-03-31 | キオクシア株式会社 | 半導体記憶装置 |
US11737274B2 (en) | 2021-02-08 | 2023-08-22 | Macronix International Co., Ltd. | Curved channel 3D memory device |
JP2022133126A (ja) * | 2021-03-01 | 2022-09-13 | キオクシア株式会社 | 半導体記憶装置及びその製造方法 |
US11916011B2 (en) | 2021-04-14 | 2024-02-27 | Macronix International Co., Ltd. | 3D virtual ground memory and manufacturing methods for same |
US20230039621A1 (en) * | 2021-08-05 | 2023-02-09 | Micron Technology, Inc. | Memory Array And Method Used In Forming A Memory Array |
US11751492B2 (en) | 2021-09-24 | 2023-09-05 | International Business Machines Corporation | Embedded memory pillar |
Citations (6)
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US20100109065A1 (en) * | 2008-11-06 | 2010-05-06 | Jin-Yong Oh | Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices |
CN102544018A (zh) * | 2010-12-30 | 2012-07-04 | 海力士半导体有限公司 | 非易失性存储器件及其制造方法 |
US20130069141A1 (en) * | 2011-01-31 | 2013-03-21 | Liyang Pan | Vertically foldable memory array structure |
CN106653684A (zh) * | 2017-03-08 | 2017-05-10 | 长江存储科技有限责任公司 | 三维存储器及其通道孔结构的形成方法 |
CN106920772A (zh) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | 三维存储器及其通道孔结构的形成方法 |
CN107017260A (zh) * | 2016-01-27 | 2017-08-04 | 株式会社东芝 | 半导体存储装置及其制造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4768557B2 (ja) | 2006-09-15 | 2011-09-07 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
JP4468433B2 (ja) | 2007-11-30 | 2010-05-26 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2009135328A (ja) | 2007-11-30 | 2009-06-18 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2010021191A (ja) | 2008-07-08 | 2010-01-28 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
CN101911287B (zh) | 2007-12-27 | 2013-05-15 | 株式会社东芝 | 半导体存储器件及其制造方法 |
JP2009164433A (ja) | 2008-01-08 | 2009-07-23 | Toshiba Corp | 不揮発性半導体記憶装置 |
US20120241866A1 (en) | 2011-03-24 | 2012-09-27 | Toshiba America Electronic Components, Inc. | Transistor structure and manufacturing method which has channel epitaxial equipped with lateral epitaxial structure |
JP2015170643A (ja) | 2014-03-05 | 2015-09-28 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US9431419B2 (en) | 2014-09-12 | 2016-08-30 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing same |
KR20170053030A (ko) | 2015-11-05 | 2017-05-15 | 에스케이하이닉스 주식회사 | 3차원 반도체 장치 및 이의 제조방법 |
WO2017099220A1 (ja) * | 2015-12-09 | 2017-06-15 | 株式会社 東芝 | 半導体装置及びその製造方法 |
US10090319B2 (en) * | 2016-03-08 | 2018-10-02 | Toshiba Memory Corporation | Semiconductor device and method for manufacturing the same |
TW201733020A (zh) * | 2016-03-10 | 2017-09-16 | Toshiba Kk | 半導體裝置及其製造方法 |
US9847342B2 (en) * | 2016-03-14 | 2017-12-19 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing same |
US10297610B2 (en) * | 2017-07-18 | 2019-05-21 | Sandisk Technologies Llc | Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same |
KR20190019672A (ko) * | 2017-08-18 | 2019-02-27 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
US10290650B1 (en) * | 2018-02-05 | 2019-05-14 | Sandisk Technologies Llc | Self-aligned tubular electrode portions inside memory openings for drain select gate electrodes in a three-dimensional memory device |
JP2020031149A (ja) * | 2018-08-23 | 2020-02-27 | キオクシア株式会社 | 半導体メモリ及び半導体メモリの製造方法 |
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2018
- 2018-03-19 JP JP2018051485A patent/JP2019165089A/ja active Pending
- 2018-08-08 TW TW107127649A patent/TWI670833B/zh not_active IP Right Cessation
- 2018-08-17 CN CN201810939441.6A patent/CN110289266B/zh active Active
- 2018-08-31 US US16/118,583 patent/US10833096B2/en active Active
Patent Citations (6)
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US20100109065A1 (en) * | 2008-11-06 | 2010-05-06 | Jin-Yong Oh | Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices |
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CN110289266B (zh) | 2023-10-27 |
TW201939717A (zh) | 2019-10-01 |
TWI670833B (zh) | 2019-09-01 |
US10833096B2 (en) | 2020-11-10 |
US20190287994A1 (en) | 2019-09-19 |
JP2019165089A (ja) | 2019-09-26 |
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