CN110197795A - 形成具有竖立指向的电子构件的电子装置结构的方法及相关结构 - Google Patents

形成具有竖立指向的电子构件的电子装置结构的方法及相关结构 Download PDF

Info

Publication number
CN110197795A
CN110197795A CN201810794981.XA CN201810794981A CN110197795A CN 110197795 A CN110197795 A CN 110197795A CN 201810794981 A CN201810794981 A CN 201810794981A CN 110197795 A CN110197795 A CN 110197795A
Authority
CN
China
Prior art keywords
electronic component
major surfaces
substrate
edge
edge surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810794981.XA
Other languages
English (en)
Inventor
舒恩·布尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anrely Technology Singapore Holdings Pte Ltd
Original Assignee
Imark Technology Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imark Technology Co filed Critical Imark Technology Co
Publication of CN110197795A publication Critical patent/CN110197795A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/6027—Mounting on semiconductor conductive members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/13187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/13294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13301—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13311—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14183—On contiguous sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16106—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting one bonding area to at least two respective bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32155—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation
    • H01L2224/32157—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/8321—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

形成具有竖立指向的电子构件的电子装置结构的方法及相关结构。一种形成电子装置结构的方法，其包含提供第一电子构件，其具有第一主要表面、相对的第二主要表面、第一边缘表面以及相对的第二边缘表面。提供具有基板第一主要表面和相对的基板第二主要表面的基板。所述第一电子构件的所述第二主要表面被放置接近于所述基板第一主要表面并且提供传导材料邻近于所述第一电子构件的所述第一边缘表面。所述传导材料被曝露于升高的温度以回流所述传导材料使所述第一电子构件抬起成直立位置，使得所述第二边缘表面与所述基板第一主要表面的间距是更远于所述第一边缘表面与所述基板第一主要表面的间距。所述方法适用于以垂直或竖立方式提供电子构件，例如天线、传感器或是光学装置。

Description

形成具有竖立指向的电子构件的电子装置结构的方法及相关 结构
技术领域
本发明通常关于电子装置，特别是关于电子结构、其构造以及形成电子结构的方法。
背景技术
无线和携带型手持通信应用是持续成长和发展的应用范例，并致力于将更多电子功能整合到更小、更轻、更薄、更低成本的解决方案中。这些应用面临的持续挑战之一是将有效天线改进并整合到各种产品平台中。在过去，用于手持通信应用的组件结构使用可挠性电缆或是可挠性电路结构以将各种天线装置在相对于与所述天线装置共同封装的集成电路的不同方向上定向。在所述组件结构中，所述可挠性电缆被弯折以定向所述天线装置到期望位置以对于特定通信应用提供3轴涵盖范围。所述可挠性电缆增加组件制程的复杂度、增加所述组件结构的体积以及可能由于所述可挠性电缆的老化和曝露于恶劣的环境条件而导致可靠性问题。
此外，随着蜂巢式网络继续向下一代发展，如5G，需要解决许多工程挑战。例如，波束形成技术(其有助于将信号集中在仅指向用户方向的集中波束中)需要天线在用于通信应用的组装结构上的多个位置处提供3轴(即，x、y和z轴)定向能力。例如，预计在5G应用中，可以将多个天线装置放置在至少两个分离的位置以提供3轴信号覆盖。对于制造商而言，这将是一个挑战，尤其是需要更小、更轻、更薄和成本更低的解决方案。
因此，期望能有一种提供封装电子设备的方法和结构，其克服与可挠性电缆组件相关的问题并且又能支持下一代蜂巢式网络技术。此外，其对于利用现有制造设备的方法和结构以及用于支持多种电子应用的方法和结构(诸如天线、光学和感测装置应用)将是有益的。
发明内容
除其他特征之外，本发明说明书包括形成电子装置结构和具有以竖立(on-edge)或直立配置提供的电子构件的相关结构的方法。在某些实施例中，电子构件的边缘被放置邻近于在基板上的传导图案。传导材料被放置邻近于所述边缘和所述传导图案。所述传导材料被曝露于升高的温度以回流所述传导材料。在所述回流制程中，表面张力效应作用以将电子构件向上升高或转动成直立或竖立指向。在某些实施例中，所述传导材料包含焊料和多个传导凸块，其可沿着所述电子构件的所述边缘而被实质上均匀地分布。在某些实施例中，所述电子构件可以是天线结构，例如半导体天线结构。在某些实施例中，所述电子构件可以是感测装置，例如影像感测装置。在某些实施例中，所述电子构件可以是裸露的半导体晶粒或芯片(即未经封装的)。在某些实施例中，所述电子构件包含导体，其电性连接到沿着所述边缘而放置的所述多个传导凸块中的一个或多个。在某些实施例中，所述传导图案可以在所述电子构件的两个侧边上。多个电子构件可以竖立配置及以习知附接配置方式两者被设置在基板上以提供具有3轴定向能力的电子装置结构。本发明所描述的所述方法和相关结构提供具有经提升的设计灵活性和性能的电子装置结构。
更特别的是，在一个实施例中，一种形成电子装置结构的方法，其包含提供第一电子构件，其具有第一主要表面、相对的第二主要表面、第一边缘表面以及相对的第二边缘表面。所述方法包含提供基板，所述基板具有基板第一主要表面和相对的基板第二主要表面。所述方法包含将所述第一电子构件的所述第二主要表面放置接近于所述基板第一主要表面。所述方法包含提供传导材料，所述传导材料邻近于所述第一电子构件的所述第一边缘表面。所述方法包含将所述传导材料曝露于升高的温度以回流所述传导材料，使所述第一电子构件抬起到直立位置，使得所述第二边缘表面与所述基板第一主要表面的间距是更远于所述第一边缘表面与所述基板第一主要表面的间距。所述方法包括：提供所述基板包含提供第一传导图案邻近于所述基板第一主要表面；提供所述传导材料包含将所述传导材料放置于邻近所述第一传导图案；以及提供所述传导材料包含使所述第一电子构件的所述第二边缘表面保留没有所述传导材料。所述方法进一步包含：形成底部填充层，其邻近于所述第一边缘表面；以及形成封装本体，其囊封所述第一电子构件，其中：提供所述第一电子构件包含提供天线装置、感测装置和光学装置中的一个；以及提供所述传导材料包含提供焊料材料和多个传导凸块。所述方法包括：提供所述第一电子构件包含提供传导图案邻近于所述第一电子构件的所述第一主要表面和所述第二主要表面中的一个或多个。所述方法包括：提供所述传导图案包含提供所述传导图案邻近于所述第一主要表面和所述第二主要表面两者。所述方法进一步包含：使用贯穿基板通孔以电性地耦接所述传导图案到所述传导材料。
在另一个实施例中，一种形成电子装置结构的方法，其包含提供第一电子构件，其具有第一主要表面、相对的第二主要表面、第一边缘表面以及相对的第二边缘表面。所述方法包含提供基板，其具有基板第一主要表面、相对的基板第二主要表面以及邻近所述基板第一主要表面的第一传导图案。所述方法包含将所述第一电子构件的所述第二主要表面放置接近于所述基板第一主要表面。所述方法包含提供传导材料，其邻近于所述第一电子构件的所述第一边缘表面和所述第一传导图案。所述方法包含将所述传导材料曝露于升高的温度以回流所述传导材料，使所述第一电子构件抬起到直立位置，使得所述第二边缘表面与所述基板第一主要表面的间距是更远于所述第一边缘表面与所述基板第一主要表面的间距。在某些实施例中，所述方法可包含将第二电子构件附接至所述基板第一主要表面、将第三电子构件附接至所述基板第二主要表面并且提供封装本体以囊封所述第一电子构件和所述第二电子构件。在其他的实施例中，所述提供所述传导材料可包含提供焊料材料和沿着所述第一电子构件的所述第一边缘表面实质上均匀分布的多个传导凸块。在其他的实施例中，所述方法可包含将所述传导材料曝露于所述升高的温度以使所述第一电子构件抬起，使得所述第一电子构件的所述第一主要表面通常与所述基板第一主要表面正交。在某些实施例中，提供所述第一电子构件包含半导体晶粒，所述半导体晶粒经建构为天线装置、感测装置(例如影像感测装置)或光学装置。
在另外的实施例中，电子装置结构包含基板，所述基板具有基板第一主要表面、相对的基板第二主要表面和邻近于所述基板第一主要表面的第一传导图案；以及第一电子构件，所述第一电子构件具有第一主要表面、相对的第二主要表面、第一边缘表面、相对的第二边缘表面以及设置至少邻近于所述第一主要表面的第一传导图案。所述第一边缘表面是藉由传导材料而附接到所述第一传导图案。所述第一主要表面通常被设置为与所述基板第一主要表面正交，使得所述第二边缘表面是远离于所述基板第一主要表面。在某些实施例中，所述传导材料是电性地耦接至所述第一传导图案。在其他的实施例中，所述电子装置结构进一步包含：第二电子构件，其附接到所述基板第一主要表面；第三电子构件，其附接到所述基板第二主要表面；封装本体，其囊封所述第一电子构件和所述第二电子构件，其中：所述第二电子构件包含第三主要表面、相对的第四主要表面、第三边缘表面以及相对的第四边缘表面；所述传导材料包含焊料材料和多个传导凸块；所述第一电子构件的所述第一主要表面面向所述基板的第一边缘；所述第三边缘表面是藉由额外的焊料材料和额外的多个传导凸块而附接到所述第一传导图案的另一部份；所述第三主要表面通常被设置为与所述基板第一主要表面正交，使得所述第四边缘表面是远离于所述基板第一主要表面；所述第二电子构件的所述第三主要表面面向所述基板的第二边缘；以及所述结构进一步包含底部填充层，其被设置为邻近于所述第一电子构件的第一边缘表面和所述第二电子构件的所述第三边缘表面中的一个或多个。
其他实施例也被包含在本发明说明书的揭露范围中。这些实施例可以在附图、权利要求书及/或本发明说明书的描述中找到。
附图说明
图1为根据本发明实施例的经封装的电子装置而沿着图2的参考线1-1所得到的横截面视图；
图2为根据本发明实施例的经封装的电子装置的俯视平面图；
图3为根据本发明实施例的在制造步骤中的电子装置的部分横截面视图；
图4为根据本发明实施例的电子构件的俯视平面图；
图5为图3的电子装置在制造设备之中的另外的制造步骤中的部分横截面视图；
图6为根据本发明实施例的经封装的电子装置的制造流程图；
图7为根据本发明实施例的电子装置的部分横截面视图；
图8为根据本发明实施例的电子装置的部分横截面视图；
图9为根据本发明实施例的电子装置的部分横截面视图；
图10为根据本发明实施例的电子装置的部分横截面视图；
图11为根据本发明实施例的电子装置的部分横截面视图；
图12为根据本发明实施例的电子装置的部分横截面视图；以及
图13为根据本发明实施例的电子装置的部分横截面视图。
具体实施方式
为了图示的简单和清楚，图式中的组件不一定按比例绘制，并且不同图式中的相同的组件符号表示相同组件。此外，为了简化描述，省略了众所周知的步骤和组件的描述和细节。如本文中所使用的，用语“及/或”包含一个或多个相关所列项目的任何和所有组合。此外，在本文中所使用的术语仅用于描述特定实施例的目的，而不意图限制本发明所揭露的内容。如本文中所使用的，除非上下文另有明确指示，否则单数形式也意图包括复数形式。将进一步理解的是，当在本说明书中使用时，用语"包括"、"包含"、"含有"及/或"具有"指定目前所描述的特征、数字、步骤、操作、组件及/或组件，但不排除有一个或多个其他特征、数字、步骤、操作、元素、组件及/或其组合的存在或添加。将理解的是，虽然用语"第一"、"第二"...等等在本文中被用来描述各种构件、组件、区域、层及/或区段，然而这些构件、组件、区域、层及/或区段不应受这些用语的限制。这些用语仅用来将构件、组件、区域、层及/或区段和另外其他的构件、组件、区域、层及/或区段做区别。因此，举例来说，下文中所讨论的第一构件、第一组件、第一区域、第一层及/或第一区段可以被称为第二构件、第二组件、第二区域、第二层和/或第二区段，而不背离本公开的教示。对“一个实施例”或“实施例”的引用代表着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的用词“在一个实施例中”或“在实施例中”不一定都指同一实施例，但在某些情况下可能是指统一实施例。再者，在一个或多个实施例中，如对所属技术领域中具有通常知识者是显而易见的，则可以以任何合适的方式组合特定的特征、结构或特性。此外，另外，用语"当...时"意味着至少在发起动作的持续时间的某个部分内发生某个动作。使用文字"约"、"大约"或"实质上"代表期望组件的数值是接近状态值或位置。然而，正如本领域所熟知的那样，总是存在微小的差异，从而不能准确地说明数值或位置。除非另有说明，否则如本文所用，用词“上方”或“上”包括指定组件可以直接或间接物理接触的方向、位置或关系。应该进一步理解的是，在下文中说明和描述的实施例可以适当地具有实施例及/或可以在缺少本文未具体描述的任何组件的情况下实施。
图1为根据第一实施例的经封装的电子装置的横截面视图，所述经封装的电子装置具有连接到基板11的电子构件12、14、16和17。图1是沿着图2的参考线1-1所截取的，图2显示经封装的电子装置10的俯视平面图。如图2中所示，经封装的电子装置10进一步包含电子构件18和19。图1和图2图示具有3轴定向能力的电子装置结构的范例。
根据本实施例，电子构件12和18被提供作为竖立型构件12和18或是对于基板11的主要表面110是非平行指向的电子构件。在某些实施例中，电子构件12和电子构件18可以相对于基板11的主要表面110通常是正交的指向提供。在某些实施例中，电子构件12、14、16、17、18和19可被建构为设置在基板11上的天线装置以提供3轴涵盖范围。在某些实施例中，所述电子构件12、14、16、17、18和19中的一个或多个包含封装的半导体晶粒或未经封装的半导体晶粒(裸露的半导体晶粒)。在其他范例中，所述电子构件12、14、16、17、18和19中的一个或多个包含被动构件。作为范例，电子构件12和17被指向为沿着图1和图2的x轴发送和接收讯号120；电子构件14和16被指向为沿着图1的z轴发送和接收讯号121；并且电子构件18和19被指向为沿着图2的y轴发送和接收讯号122。
将理解的是，其他电子构件可被放置到基板11上，但是这里没有显示出来，以免挤压这些图式。其他构件可以包括集成电路装置，例如数字信号处理(DSP)装置、微处理器、内存装置、微控制器装置、功率装置、被动装置或所属技术领域中具有通常知识者已知的其它装置。可以进一步理解的是，电子构件12、14、16、17、18和19中的一个或多个可以是其他类型的电子装置，例如是传感器装置(例如CMOS或CCD影像传感器)、光学装置或是所属技术领域中具有通常知识者已知的其它装置。所属技术领域中具有通常知识者将会理解，所述电子构件以简化形式示出，并且还可以包括多个扩散区域、多个导电层和多个介电质层。
基板11可以是任意种类的电子构件基板，例如印刷电路板(PCB)、组成基板、层叠基板、引线架基板、陶瓷基板、模制基板、模制引线架或是所属技术领域中具有通常知识者已知的其它基板。在一个实施例中，基板11被提供以具有邻近于主要表面110的传导图案21以及邻近于与主要表面110相对的主要表面111的传导图案22。传导图案21和22可包含传导衬垫、传导迹线或是其之组合。在大部分的实施例中，传导图案21和22包含一个或多个材料，例如铜、铜合金、被镀材料、金、镍或是所属技术领域中具有通常知识者已知的其它材料。
基板11可进一步包含埋藏的迹线和传导互连通孔(未显示)，其将传导图案21的特定部分电性连接到传导图案21的其他部分、电性连接到传导图案22或电性连接到邻近于基板11的主要表面111的传导凸块23。作为范例，传导凸块23包含可温度回流焊料凸块、热音波(thermosonic)或热压缩接合凸块(例如，金凸块)、黏着接合凸块或是所属技术领域中具有通常知识者已知的其它凸块材料。传导凸块23经建构以用于附接或电性连接经封装的电子装置10到组件的下一层级。
在某些实施例中，电子构件14藉由传导凸块31被附接到传导图案21并且电子构件16相似地藉由传导凸块31而被附接到传导图案22。传导凸块31可包含可温度回流焊料凸块、热音波或热压缩接合凸块(例如，金凸块)、黏着接合凸块或是所属技术领域中具有通常知识者已知的其它凸块材料。
根据本实施例，电子构件12的边缘126利用一个或多个传导凸块32和焊料33而被附接到传导图案21。在某些实施例中，边缘126仅部分地交叠传导图案21，而传导凸块32和焊料33交叠传导图案21。相对边缘127被设置远离基板11的主要表面110。电子构件17的边缘176利用一个或多个传导凸块32和焊料33而被附接到传导图案21。相对边缘177被设置远离基板11的主要表面110。作为范例，传导凸块32包含多个无铅焊料球或凸块(例如，锡(Sn)、银(Ag))。根据本实施例，将参照图3和图5更详细地解释，在将电子装置12、14、16、17、18和19附接或接合到基板11的回流制程中，利用来自熔化或软化的焊料和所述传导凸块的张力效应来将电子构件12、17、18和19升起或推高成相对于基板11的主要表面110呈直立或非平行指向。换句话说，在所述回流制程之后，电子构件12、17、18和19以竖立配置方式而被设置在基板11上，使得这些构件的所述主要表面与基板11的主要表面110的配置关系是除了平行之外的其他配置关系。在一个实施例中，底部填充层34可被设置相邻于电子构件12、17、18和19的边缘而接近基板11的主要表面110以在电子构件12、17、18、和19被放置在期望的直立指向之后对于电子构件12、17、18和19提供额外的支撑或保护。虽然没有图标于本范例中，可使用多个底部填充层于电子构件14和16的下方。焊料33可以是无铅焊料，例如，锡(Sn)、银(Ag)焊料，并且可被提供为焊料膏。根据本实施例，电子构件12、17、18和19仅被附接到基板11的一个边缘。在某些实施例中，焊料33和传导凸块中的一个或多个可被称为传导材料。如图1中所示，电子构件12具有主要表面125，其面向基板11的边缘112，并且电子构件17具有主要表面175，其面向基板的边缘113。将理解的是，电子构件18和19也具有主要表面，所述主要表面面向基板11的其他边缘118和116，如图2中所示。
在某些实施例中，封装本体36囊封或覆盖电子构件12、14、17、18和19。在某些实施例中，封装本体36可以是基于聚合物的复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或是具有适当填充物的聚合物。封装本体36包含非传导和环境保护材料，其保护电子构件12、14、17、18和19免于外部组件和污染物的影响。封装本体36的形成可利用钢板印刷(paste printing)、压缩成形、转移成形、覆盖成形(over-molding)、液体囊封成形、真空层压、其他适合的施用器或是所属技术领域中具有通常知识者已知的其它制程。在某些实施例中，封装本体36是环氧模压树脂(epoxy mold compound，EMC)，并且可利用转移或射出成形技术而被形成。在某些实施例中，另外的封装本体(未显示)可被用来囊封设置在邻近于基板11的主要表面111的电子构件16。在其他的实施例中，封装本体36可包含帽盖、盖子或是所属技术领域中具有通常知识者已知的其它覆盖结构。在其他实施例中，没有使用封装本体36。
参照图2，将描述附接方式的范例。在一个实施例中，只有电子构件12的一个侧边或边缘126利用多个传导凸块32A到32F以及焊料层33或多个焊料层33而被附接到个别的传导衬垫21A到21F。在一个实施例中，只有电子构件17的一个侧边或边缘176利用多个传导凸块32G到32L以及焊料层33或多个焊料层33而被附接到个别的传导衬垫21G到21L(多个焊料层33的范例显示于图1中)。在某些实施例中，较佳的是所述传导衬垫21A到21F是实质上均匀地沿着电子构件12的边缘126分布以及所述传导衬垫21G到21L是实质上均匀地沿着电子构件17的边缘176分布。如图2中所示，传导衬垫21A到21F和传导凸块32A到32F被设置在基板11和电子构件12的外侧边缘115。也就是，电子构件12的主动表面是邻近或是接近传导凸块32A到32F。进一步如图2所示，传导衬垫21G到21L和传导凸块32G到32L被设置在基板11和电子构件17的外侧边缘117。也就是，电子构件17的主动表面是邻近或是接近传导凸块32G到32L。
在一个实施例中，只有电子构件18的一个侧边或边缘186利用多个传导凸块32M到32W以及焊料层33或多个焊料层33而被附接到个别的传导衬垫21M到21P。在本实施例中，传导衬垫21M到21P中的至少一些容纳一个以上的传导凸块32M到32W。在某些实施例中，较佳的是所述传导衬垫21M到21P是实质上均匀地沿着电子构件18的下边缘186分布。如图2中所示，电子构件18被设置在基板11的外侧边缘116以及传导衬垫21M到21P与传导凸块32M到32W之间。也就是，电子构件18的主动表面是相对于传导凸块32M到32W。
在一个实施例中，只有电子构件19的一个侧边或边缘196利用多个传导凸块32X到32AF以及焊料层33或多个焊料层33而被附接到个别的传导衬垫21Q到21T。在本实施例中，传导衬垫21Q到21T中的至少一些容纳一个以上的传导凸块32X到32AF。在某些实施例中，较佳的是所述传导衬垫21Q到21T是实质上均匀地沿着电子构件19的下边缘196分布。如图2中所示，电子构件19被设置在基板11的外侧边缘118以及传导衬垫21Q到21T与传导凸块32X到32AF之间。也就是，电子构件19的主动表面是相对于传导凸块32X到32AF。
可以理解的是，传导衬垫和焊料凸块的数量由电子构件的电性I/O需求和将电子组件升高到期望的直立位置所需的材料的累积体积来决定。进一步可以理解的是，传导衬垫和焊料凸块中的一些可能不会提供电性连接，但是可能被用来提供本发明的表面张力效应以附接所述电子构件到基板。
图3为根据本发明实施例的范例性电子装置30在制造过程的初期步骤中的部分横截面视图。在本实施例中，电子构件12包含被放置在面朝上的主要表面129上的传导图案128并且以边缘126邻接在基板11上的传导图案21的方式被设置。在本实施例中，电子构件12的主要表面131面向基板11的主要表面110，但是与主要表面110分隔开以提供间隙113。传导凸块32被设置在相邻于电子构件12的主要表面129，并且焊料层33被设置在传导图案21上并且接触边缘126和焊料凸块32。在本实施例中，主要表面129可以是电子构件12的主动表面，其与传导凸块32在相同侧上。根据本实施例，电子构件12相对于边缘126的边缘127被提供为缺乏任何传导凸块32。换句话说，传导凸块32被设置为仅沿着或是相邻于电子构件12的边缘126。
图4是根据本发明较佳实施例的电子构件12的俯视平面图。更具体地说，电子构件12较佳地具有宽度1200对高度1201的比率或长宽比大于1，例如大约5到1的宽高比例，其中标准厚度在大约100微米至约200微米。此长宽比较佳地是用来方便于在后续的制程步骤(例如焊料回流制程)中升高电子构件12到升高的位置(例如直立位置)。再者，根据本实施例，电子构件12的所述宽高比可被用来决定传导凸块的数量和尺寸以及焊料33的体积以用来在所述焊料回流制程中将电子构件12升高到期望的位置。
图5为图3的电子装置30在根据一实施例的制造设备50之中的后段步骤中的部分横截面视图。作为范例，制造设备50可以是回流炉，其具有腔室500、支撑结构501以及热源502。根据本实施例，在所述回流制程中，表面张力作用以移动电子构件12到升高的指向，例如直立指向。更特别是，焊料33、传导凸块31和电子构件12之间的附着力造成了表面张力转动电子构件12的边缘126因而升高电子构件12成直立位置的一瞬间504。根据本实施例，瞬间504是因为在回流制程期间电子构件12的相对边缘127未附着到基板11所导致。在一实施例中，电子构件12通常对于基板11的主要表面110具有正交指向。作为范例，当使用无铅焊料材料时，电子装置30可被曝露到大约220度C到250度C的范围中的一温度大约30到90秒。
图6是根据本发明实施例的经封装的电子装置的制造流程图。在步骤601中，提供电子构件，其被建构为相对于基板为非平行指向。作为范例，所述电子构件可以是天线装置、感测装置或光学装置。在某些实施例中，所述电子构件可以是如图1-3中的电子构件12或电子构件18，或者是下文中图7-13中所示的任何电子构件。在某些较佳的实施例中，所述电子构件具有大约5到1的宽高比。在某些实施例中，所述电子构件是提供有传导凸块，例如传导凸块32，其被设置在所述电子构件的表面上邻近于所述电子构件的边缘沿着所述电子构件的宽度维度。
在步骤602中，提供有用于支撑所述电子构件的基板。作为范例，所述基板可以是PCB基板、组成基板、层叠基板、引线架基板、陶瓷基板、模制基板、模制引线架或是所属技术领域中具有通常知识者已知的其它基板。在某些实施例中，所述基板可以是基板11，其被提供具有传导图案21和22用于接收一个或多个电子构件。
在步骤603中，所述电子构件利用焊料材料被附接到所述基板。作为范例，取放设备可被用来放置所述电子构件到所述基板上的期望位置处。在某些实施例中，焊料材料33被用来初步附接所述电子构件18仅沿着具有传导凸块32的所述边缘。也就是说，与具有传导凸块32的所述边缘相对的所述边缘没有被附接到所述基板。作为范例，所述焊料材料可以在所述电子构件被放置到所述基板之前被首先以所期望的数量被分配到所述传导图案上的期望的位置上。分配或网印制程可被用来提供所述焊料材料余所述基板的期望位置上。在某些实施例中，所述焊料材料至少部分地覆盖传导图案21的各别部份，在所述各别部份中所述电子构件被附接到所述基板。作为范例，所述焊料材料可包含SnAg或其他无铅焊料，可包含助焊材料，并且可被提供为焊料膏。在步骤603中，其他电子构件可以以习知的组态方式被附接到所述基板。例如其他构件可以包括集成电路装置，例如数字信号处理(DSP)装置、微处理器、内存装置、微控制器装置、功率装置、被动装置或所属技术领域中具有通常知识者已知的其它装置。
在步骤604中，所述基板和电子构件被曝露到升高的温度以回流所述传导凸块和焊料材料而将所述电子构件永久性地附接到所述基板。根据本实施例，至少一个电子构件在步骤604的期间被升高到提高的位置使得所述至少一个电子构件最后是以与所述基板不平行的指向方式而被附接到所述基板。作为范例，其可以是图1和图5中所示的电子构件12、图10中所示的电子构件1012或图13中所示的电子构件12。换句话说，在步骤604之后，如图5所示，电子构件12的主要表面129对于基板11的主要表面110是非平行指向。
在可选择的步骤605中，封装本体可被提供以覆盖或囊封所述基板和所述电子构件的至少部份。在某些实施例中，封装本体36可被使用并且可以是基于聚合物的复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或是具有适当填充物的聚合物。所述封装本体的形成可利用钢板印刷、压缩成形、转移成形、覆盖成形(over-molding)、液体囊封成形、真空层压、其他适合的施用器或是所属技术领域中具有通常知识者已知的其它制程。在某些实施例中，在所述封装本体被提供之前，底部填充材料(例如图1中所示的底部填充材料34)被放置在所述电子构件和所述基板之间。
关于图7-13，将描述其他的实施例。在图7-9、11和12中，显示为在所述回流制程之前的所述电子构件。换句话说，所述电子构件还没有被升高到直立位置。应了解的是，在回流制程之后，在图7-9、11和12中的电子构件是在升高的组态。在图10和13中，所述电子构件被图标为在升高的组态。
图7为根据第一实施例的电子装置70的部分横截面视图，其具有在边缘726处附着到基板11上的导电图案21的电子构件712。电子装置70相似于电子装置30，并且主要的不同将描述于下文中。在本实施例中，基板11被进一步提供而具有结构72(例如支柱(stand-off)72、衬垫72或凸块72)，其经建构以在电子构件712被升高到提高的位置高于基板11的主要表面110之前对于相邻于主要表面731的电子构件712提供暂时性的支撑。结构72可包含一材料，其在所述回流制程中不黏着到电子构件712。在某些实施例中，结构72包含聚合物材料、陶瓷材料或是所属技术领域中具有通常知识者已知的其它材料。此外，电子构件712在主要表面729上具有传导层728，其横向地与传导凸块32分隔开。更特别的是，电子构件712不与至少一个传导凸块32电性通讯。相似于电子装置30，电子构件712的边缘726仅重叠传导图案21的一部份。根据本实施例，电子构件712中与边缘726相对的边缘727被提供为缺乏传导凸块32。换句话说，传导凸块32被设置为仅沿着或是相邻于电子构件712的边缘726。
图8为根据另一实施例的电子装置80的部分横截面视图，其具有在边缘826处附着到基板11上的导电图案21的电子构件812。电子装置80相似于电子装置30和70，并且仅将主要的不同部分描述于下文中。在本实施例中，电子构件812在主要表面829上具有传导层828并且在主要表面831上具有传导层838。换句话说，电子构件812在两个相对的主要表面上具有主动装置。此外，传导凸块321和322被分别地提供于电子构件812的所述相对的主要表面829和831上。更特别地，在本实施例中，传导凸块322在接近电子构件812的边缘826物理性地接触传导图案21。根据本实施例，电子构件812相对于边缘826的边缘827被提供为缺乏任何传导凸块321或322。换句话说，传导凸块321和322被设置为仅沿着或是相邻于电子构件812的边缘826。
图9为根据另一实施例的电子装置90的部分横截面视图，其具有在边缘926处附着到基板11上的导电图案21的电子构件912。电子装置90相似于电子装置30、70和80，并且仅将主要的不同部分描述于下文中。在本实施例中，电子构件912在主要表面929上具有传导层928，所述传导层928延伸覆盖边缘926并且延伸以邻近于主要表面931的至少部份。传导凸块321和322被分别地提供于电子构件912的所述相对的主要表面929和931上。更特别地，在本实施例中，传导凸块322在接近电子构件912的边缘926物理性地接触传导图案21。根据本实施例，电子构件912的与边缘926相对的边缘927被提供为缺乏任何传导凸块321或322。换句话说，传导凸块321和322被设置为仅沿着或是相邻于电子构件912的边缘926。
图10为根据另一实施例的电子装置100的部分横截面视图，其具有在边缘1026处附着到基板11上的导电图案21的电子构件1012。电子装置100相似于电子装置30、70、80和90，并且仅将主要的不同部分描述于下文中。在本实施例中，电子构件1012被图标为在升高或直立的组态。在本实施例中，电子构件1012具有传导贯通基板通孔(through-substratevia，TSV)1127，所述传导贯通基板通孔1127从电子构件1012的主要表面1029延伸至相对主要表面1031，所述传导贯通基板通孔1127将相邻于主要表面1029的传导凸块32电性连接到被设置相邻于主要表面1031的传导层1033。在电子构件1012中，主要表面1031是主动表面，其透过TSV1127、传导凸块32和焊料33与传导图案21电性通讯。根据本实施例，电子构件1012的与边缘1026相对的边缘1027被提供为缺乏任何传导凸块32。换句话说，传导凸块32被设置为仅沿着或是相邻于电子构件1012的边缘1026。
图11为根据本发明的另一实施例的电子装置301的部分横截面视图，其具有在边缘126处附着到基板11上的导电图案21的电子构件12。电子装置301相似于电子装置30，并且两个装置之间的主要不同将描述于下文中。在本实施例中，电子构件12与大部分的传导图案21交叠。也就是，在横截面视图中，电子构件12与传导图案21的至少一半交叠。根据本实施例，电子构件12的与边缘126相对的边缘127被提供为缺乏任何传导凸块32。换句话说，传导凸块32被设置为仅沿着或是相邻于电子构件12的边缘126。
图12为根据本发明的另一实施例的电子装置302的部分横截面视图，其具有在边缘126处附着到基板11上的导电图案21的电子构件12。电子装置302相似于电子装置30和301，并且这些装置之间的主要不同将描述于下文中。在本实施例中，电子构件12在电子构件上升到直立位置之前不与导电图案21交迭。
图13为根据本发明的另一实施例的电子装置303的部分横截面视图，其具有在边缘126处附着到基板11上的导电图案21的电子构件12。在本实施例中，电子构件被提供为在升高的位置，使得电子构件12的主要表面129不平行于基板11的主要表面110。此外，在本实施例中，电子构件12的主动表面129不是与基板11的主要表面110正交。换句话说，电子构件12是在升高的位置，其相对于基板11的主要表面110是大于0度且小于90度。
从前述所有内容中，根据一个实施例，所属技术领域中具有通常知识者可以确定，一种方法可以进一步包括在第一边缘表面附近形成底部填充层。在另一实施例中，所述提供所述传导材料可包含提供沿着所述第一电子构件的所述第一边缘表面实质上均匀分布的多个传导凸块。在另外的实施例中，提供邻近所述第一主要表面和第二主要表面两者的传导图案可包括藉由延伸传导图案交迭所述第一电子构件的所述第一边缘表面而将在所述第一主要表面上的所述传导图案耦合到所述第二主要表面上的传导图案。在又另一实施例中，提供基板可包括提供支柱邻近于所述基板第一主要表面，并且放置所述第一电子构件的所述第二主要表面可包含放置所述第二主要表面邻近于所述支柱。
从前述所有内容中，根据另一实施例，所属技术领域中具有通常知识者可以确定，所述第一电子构件可以包括具有大约5到大约1的宽高比的半导体晶粒。
根据上述所有内容，显然已经揭示了一种新颖的方法和相关结构，其提供有竖立或直立配置的电子构件。在某些实施例中，电子构件的边缘被放置邻近于在基板上的传导图案。传导材料被放置邻近于所述边缘和所述传导图案。述传导材料被曝露于升高的温度以回流所述传导材料。在所述回流制程中，表面张力效应作用以将电子构件向上升高或转动成直立或竖立指向。在某些范例中，所述传导材料包含焊料和多个传导凸块，其可沿着所述电子构件的所述边缘而被实质上均匀地分布。在某些实施例中，所述电子构件可以是天线结构，例如半导体天线结构。在某些实施例中，所述电子构件可以是感测装置，例如影像感测装置。在某些实施例中，所述电子构件可以是裸露的半导体晶粒或芯片(即未经封装的)。在某些实施例中，所述电子构件包含导体，其电性连接到沿着所述边缘而放置的所述多个传导凸块中的一个或多个。在某些实施例中，所述传导图案可以在所述电子构件的两个侧边上。多个电子构件可以竖立配置及以习知附接配置方式两者被设置在基板上以提供具有3轴定向能力的电子装置结构。本发明所描述的所述方法和相关结构提供具有经提升的设计灵活性和性能的电子装置结构。此外，所述方法和相关结构可以支持即将到来的电子构件需求，例如5G应用。
虽然本发明的目标藉由具体较佳的实施例和示例性实施例来描述，但是前述图式和其描述仅描绘了所述目标的典型实施例，并且因此不被认为是对其范围的限制。对于所属技术领域中具有通常知识者而言，许多替代和变化将显然是显而易见的。作为范例，多个电子装置可以以并排配置、堆栈配置、其组合或所属技术领域中具有通常知识者已知的其他配置方式附接到基板。
如本发明的权利要求书所反映的，发明的态样可能在于少于单个前述公开实施例的所有特征。因此，下文中表达的权利要求在此明确地并入所述图式的详细描述中，每个权利要求自身作为本发明的单独实施例。此外，尽管本文描述的一些实施例包括其他实施例中包括的一些特征但不包括其他特征，但是如所属技术领域中具有通常知识者将理解的那样，不同实施例的特征的组合也被认为是在本发明的范畴内并且用意是形成不同的实施例。

Claims (10)

1.一种形成电子装置结构的方法，其包含：
提供第一电子构件，其具有第一主要表面、相对的第二主要表面、第一边缘表面以及相对的第二边缘表面；
提供基板，其具有基板第一主要表面和相对的基板第二主要表面；
将所述第一电子构件的所述第二主要表面放置接近于所述基板第一主要表面；
提供传导材料，其邻近于所述第一电子构件的所述第一边缘表面；以及
将所述传导材料曝露于升高的温度以回流所述传导材料使所述第一电子构件抬起成直立位置，使得所述第二边缘表面与所述基板第一主要表面的间距是更远于所述第一边缘表面与所述基板第一主要表面的间距。
2.如权利要求1所述的方法，其中：
提供所述基板包含提供第一传导图案邻近于所述基板第一主要表面；
提供所述传导材料包含将所述传导材料放置于邻近所述第一传导图案；以及
提供所述传导材料包含使所述第一电子构件的所述第二边缘表面保留没有所述传导材料。
3.如权利要求1所述的方法，其进一步包含：
形成底部填充层，其邻近于所述第一边缘表面；以及
形成封装本体，其囊封所述第一电子构件，其中：
提供所述第一电子构件包含提供天线装置、感测装置和光学装置中的一个；以及
提供所述传导材料包含提供焊料材料和多个传导凸块。
4.如权利要求1所述的方法，其中提供所述第一电子构件包含提供传导图案邻近于所述第一电子构件的所述第一主要表面和所述第二主要表面中的一个或多个。
5.如权利要求4所述的方法，其中提供所述传导图案包含提供所述传导图案邻近于所述第一主要表面和所述第二主要表面两者。
6.如权利要求4所述的方法，其进一步包含使用贯穿基板通孔以电性地耦接所述传导图案到所述传导材料。
7.一种形成电子装置结构的方法，其包含：
提供第一电子构件，其具有第一主要表面、相对的第二主要表面、第一边缘表面以及相对的第二边缘表面；
提供基板，其具有基板第一主要表面、相对的基板第二主要表面以及邻近所述基板第一主要表面的第一传导图案；
将所述第一电子构件的所述第二主要表面放置接近于所述基板第一主要表面；
提供传导材料，其邻近于所述第一电子构件的所述第一边缘表面和所述第一传导图案；以及
将所述传导材料曝露于升高的温度以回流所述传导材料使所述第一电子构件抬起成直立位置，使得所述第二边缘表面与所述基板第一主要表面的间距是更远于所述第一边缘表面与所述基板第一主要表面的间距。
8.如权利要求7所述的方法，其进一步包含：
将第二电子构件附接到所述基板第一主要表面；
将第三电子构件附接到所述基板第二主要表面；以及
形成封装本体，其囊封所述第一电子构件和所述第二电子构件，其中：
提供所述传导材料包含提供焊料材料和沿着所述第一电子构件的所述第一边缘表面实质上均匀分布的多个传导凸块；
将所述传导材料曝露于所述升高的温度以使所述第一电子构件抬起，使得所述第一电子构件的所述第一主要表面通常与所述基板第一主要表面正交；以及
提供所述第一电子构件包含提供半导体晶粒。
9.一种电子装置结构，其包含：
基板，其具有基板第一主要表面、相对的基板第二主要表面以及邻近所述基板第一主要表面的第一传导图案；以及
第一电子构件，其具有第一主要表面、相对的第二主要表面、第一边缘表面、相对的第二边缘表面以及设置至少邻近于所述第一主要表面的第一传导图案，其中：
所述第一边缘表面是藉由传导材料而附接到所述第一传导图案；
所述第一主要表面通常被设置为与所述基板第一主要表面正交，使得所述第二边缘表面是远离于所述基板第一主要表面；以及
所述传导材料是电性地耦接至所述第一传导图案。
10.如权利要求9所述的结构，其进一步包含：
第二电子构件，其附接到所述基板第一主要表面；
第三电子构件，其附接到所述基板第二主要表面；
封装本体，其囊封所述第一电子构件和所述第二电子构件，其中：
所述第二电子构件包含第三主要表面、相对的第四主要表面、第三边缘表面以及相对的第四边缘表面；
所述传导材料包含焊料材料和多个传导凸块；
所述第一电子构件的所述第一主要表面面向所述基板的第一边缘；
所述第三边缘表面是藉由额外的焊料材料和额外的多个传导凸块而附接到所述第一传导图案的另一部份；
所述第三主要表面通常被设置为与所述基板第一主要表面正交，使得所述第四边缘表面是远离于所述基板第一主要表面；
所述第二电子构件的所述第三主要表面面向所述基板的第二边缘；以及
所述结构进一步包含底部填充层，其被设置为邻近于所述第一电子构件的第一边缘表面和所述第二电子构件的所述第三边缘表面中的一个或多个。
CN201810794981.XA 2018-02-27 2018-07-19 形成具有竖立指向的电子构件的电子装置结构的方法及相关结构 Pending CN110197795A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/907,039 2018-02-27
US15/907,039 US10847478B2 (en) 2018-02-27 2018-02-27 Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures

Publications (1)

Publication Number Publication Date
CN110197795A true CN110197795A (zh) 2019-09-03

Family

ID=67686092

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810794981.XA Pending CN110197795A (zh) 2018-02-27 2018-07-19 形成具有竖立指向的电子构件的电子装置结构的方法及相关结构

Country Status (3)

Country Link
US (3) US10847478B2 (zh)
CN (1) CN110197795A (zh)
TW (2) TWI763841B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
KR102075764B1 (ko) * 2018-03-28 2020-02-10 한국과학기술원 이종 광 집적회로 및 이의 제조 방법
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
CN109244093B (zh) * 2018-08-30 2020-09-29 维沃移动通信有限公司 一种光学封装组件及移动终端
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0725434A2 (en) * 1995-02-03 1996-08-07 Plessey Semiconductors Limited Microchip module assemblies
US20060220258A1 (en) * 2005-04-01 2006-10-05 Wolfgang Nuechter Method for mounting semiconductor chips on a substrate and corresponding assembly
US20080315399A1 (en) * 2004-09-22 2008-12-25 Infineon Technologies Ag Semiconductor Device Having Through Contacts Through a Plastic Housing Composition and Method for the Production Thereof
CN101621043A (zh) * 2008-06-30 2010-01-06 万国半导体股份有限公司 标准芯片尺寸封装
US20100078804A1 (en) * 2008-09-29 2010-04-01 Analog Devices, Inc. Apparatus with Side Mounted Microchip
US9490195B1 (en) * 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020170290A1 (en) * 2001-05-18 2002-11-21 Victor Bright Multi-dimensional micro-electromechanical assemblies and method of making same
US7049216B2 (en) 2003-10-14 2006-05-23 Unitive International Limited Methods of providing solder structures for out plane connections
JP2007220873A (ja) * 2006-02-16 2007-08-30 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
TWI330951B (en) * 2006-10-04 2010-09-21 Via Tech Inc Electronic apparatus
US20080315388A1 (en) * 2007-06-22 2008-12-25 Shanggar Periaman Vertical controlled side chip connection for 3d processor package
EP2382661B1 (en) * 2008-12-30 2021-08-11 STMicroelectronics Srl Integrated electronic device with transceiving antenna and magnetic interconnection
CN101840893A (zh) * 2009-03-19 2010-09-22 日月光半导体制造股份有限公司 直立式芯片的封装结构
US8278748B2 (en) * 2010-02-17 2012-10-02 Maxim Integrated Products, Inc. Wafer-level packaged device having self-assembled resilient leads
US8138099B1 (en) * 2010-11-17 2012-03-20 International Business Machines Corporation Chip package solder interconnect formed by surface tension
ITTO20120174A1 (it) * 2012-02-27 2013-08-28 St Microelectronics Srl Dispositivo elettronico incapsulato comprendente circuiti elettronici integrati dotati di antenne di ricetrasmissione
US20180040587A1 (en) * 2016-08-08 2018-02-08 Invensas Corporation Vertical Memory Module Enabled by Fan-Out Redistribution Layer
US10354945B2 (en) * 2016-08-08 2019-07-16 Invensas Corporation Multi-surface edge pads for vertical mount packages and methods of making package stacks
KR102635791B1 (ko) * 2016-12-21 2024-02-08 인텔 코포레이션 무선 통신 기술, 장치 및 방법
US10483617B2 (en) * 2017-09-29 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0725434A2 (en) * 1995-02-03 1996-08-07 Plessey Semiconductors Limited Microchip module assemblies
US20080315399A1 (en) * 2004-09-22 2008-12-25 Infineon Technologies Ag Semiconductor Device Having Through Contacts Through a Plastic Housing Composition and Method for the Production Thereof
US20060220258A1 (en) * 2005-04-01 2006-10-05 Wolfgang Nuechter Method for mounting semiconductor chips on a substrate and corresponding assembly
CN101621043A (zh) * 2008-06-30 2010-01-06 万国半导体股份有限公司 标准芯片尺寸封装
US20100078804A1 (en) * 2008-09-29 2010-04-01 Analog Devices, Inc. Apparatus with Side Mounted Microchip
US9490195B1 (en) * 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects

Also Published As

Publication number Publication date
US20220415834A1 (en) 2022-12-29
TWI839711B (zh) 2024-04-21
US20190267334A1 (en) 2019-08-29
TWI763841B (zh) 2022-05-11
US10847478B2 (en) 2020-11-24
US20210043589A1 (en) 2021-02-11
US11482500B2 (en) 2022-10-25
TW201937618A (zh) 2019-09-16
TW202230556A (zh) 2022-08-01

Similar Documents

Publication Publication Date Title
CN110197795A (zh) 形成具有竖立指向的电子构件的电子装置结构的方法及相关结构
TWI601266B (zh) 半導體裝置結構及其製造方法
CN108431952A (zh) 内嵌的引线接合线
EP1119049A2 (en) Laminate type semiconductor apparatus
CN104900596B (zh) 封装堆栈结构及其制法
CN108807297A (zh) 电子封装件及其制法
CN102938401A (zh) 具有紧固元件和无卤素封装件间连接件的堆叠式封装件
JP2007318076A (ja) Ｓｉｐモジュール
KR20080020069A (ko) 반도체 패키지 및 그 제조방법
JP2008147628A (ja) 多層半導体パッケージ
CN103165484B (zh) 堆迭式封装及其制造方法
KR20070076084A (ko) 스택 패키지와 그 제조 방법
KR20060112230A (ko) 전자 부품 수용 구조물
CN107452696A (zh) 电磁屏蔽封装体以及制造方法
JP3668074B2 (ja) 半導体装置およびその製造方法
CN100433320C (zh) 芯片封装结构及凸块制程
JP4556671B2 (ja) 半導体パッケージ及びフレキシブルサーキット基板
CN104979219B (zh) 封装结构及其制法
TWI283918B (en) Electronic carrier board and package structure thereof
CN104051284B (zh) 电子封装结构以及其制造方法
CN102263082A (zh) 封装基板结构及其制造方法
CN220341224U (zh) 塑封电源
KR20040059741A (ko) 반도체용 멀티 칩 모듈의 패키징 방법
TWI502690B (zh) 基板內嵌式模組結構
CN103531546B (zh) 芯片上镂空基板的模块结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20240816

Address after: Singapore City

Applicant after: Anrely Technology Singapore Holdings Pte. Ltd.

Country or region after: Singapore

Address before: 2045 Temple East Road, Innovation Circle, Arizona 85284, USA

Applicant before: AMKOR TECHNOLOGY, Inc.

Country or region before: U.S.A.

TA01 Transfer of patent application right