CN110085274A - 半导体存储装置及存储器系统 - Google Patents
半导体存储装置及存储器系统 Download PDFInfo
- Publication number
- CN110085274A CN110085274A CN201810887364.4A CN201810887364A CN110085274A CN 110085274 A CN110085274 A CN 110085274A CN 201810887364 A CN201810887364 A CN 201810887364A CN 110085274 A CN110085274 A CN 110085274A
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- CN
- China
- Prior art keywords
- chip
- signal
- instruction
- controller
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- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
- Memory System (AREA)
Abstract
Description
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018-010660 | 2018-01-25 | ||
JP2018010660A JP2019128829A (ja) | 2018-01-25 | 2018-01-25 | 半導体記憶装置及びメモリシステム |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110085274A true CN110085274A (zh) | 2019-08-02 |
CN110085274B CN110085274B (zh) | 2023-08-18 |
Family
ID=67299486
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810887364.4A Active CN110085274B (zh) | 2018-01-25 | 2018-08-06 | 半导体存储装置及存储器系统 |
Country Status (4)
Country | Link |
---|---|
US (2) | US10720221B2 (zh) |
JP (1) | JP2019128829A (zh) |
CN (1) | CN110085274B (zh) |
TW (2) | TWI791112B (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112466356A (zh) * | 2019-09-06 | 2021-03-09 | 铠侠股份有限公司 | 半导体装置及其控制方法 |
CN113496736A (zh) * | 2020-03-19 | 2021-10-12 | 铠侠股份有限公司 | 半导体集成电路、存储器控制器以及存储器系统 |
WO2023245923A1 (zh) * | 2022-06-22 | 2023-12-28 | 长鑫存储技术有限公司 | 存储器器件和zq校准方法 |
CN113496736B (zh) * | 2020-03-19 | 2024-07-05 | 铠侠股份有限公司 | 半导体集成电路、存储器控制器以及存储器系统 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019128829A (ja) * | 2018-01-25 | 2019-08-01 | 東芝メモリ株式会社 | 半導体記憶装置及びメモリシステム |
JP2021047562A (ja) | 2019-09-18 | 2021-03-25 | キオクシア株式会社 | 半導体集積回路、送信装置、およびメモリシステム |
JP2021135820A (ja) | 2020-02-27 | 2021-09-13 | キオクシア株式会社 | 不揮発性半導体記憶装置 |
JP2021152779A (ja) | 2020-03-24 | 2021-09-30 | キオクシア株式会社 | 半導体記憶装置 |
JP2022038392A (ja) | 2020-08-26 | 2022-03-10 | キオクシア株式会社 | 半導体記憶装置及び半導体記憶装置におけるコマンド処理方法 |
JP2023039342A (ja) | 2021-09-08 | 2023-03-20 | キオクシア株式会社 | 半導体装置及び半導体装置の出力信号のデューティ比の補正方法 |
KR102481649B1 (ko) * | 2021-12-01 | 2022-12-28 | 삼성전자주식회사 | 비휘발성 메모리 장치, 그것을 제어하는 제어기, 그것을 포함하는 저장 장치 및 그것의 동작 방법 |
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CN104734697A (zh) * | 2013-11-19 | 2015-06-24 | 英特尔公司 | 使用异步数字采样的时钟校准 |
US20170308328A1 (en) * | 2016-04-20 | 2017-10-26 | Samsung Electronics Co., Ltd. | Computing system, nonvolatile memory module and method of storage device |
CN107430548A (zh) * | 2015-03-06 | 2017-12-01 | 东芝存储器株式会社 | 存储装置的控制方法、及存储装置 |
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US6314530B1 (en) * | 1997-04-08 | 2001-11-06 | Advanced Micro Devices, Inc. | Processor having a trace access instruction to access on-chip trace memory |
KR100278653B1 (ko) * | 1998-01-23 | 2001-02-01 | 윤종용 | 이중 데이터율 모드 반도체 메모리 장치 |
KR100574989B1 (ko) * | 2004-11-04 | 2006-05-02 | 삼성전자주식회사 | 데이터 스트로브 버스라인의 효율을 향상시키는메모리장치 및 이를 구비하는 메모리 시스템, 및 데이터스트로브 신호 제어방법 |
KR100715158B1 (ko) | 2005-12-13 | 2007-05-10 | 삼성전자주식회사 | 동작특성 및 동작전압을 개선하는 듀티보정 증폭회로 |
KR101285218B1 (ko) | 2006-07-25 | 2013-07-11 | 삼성전자주식회사 | 듀티 사이클 보정 회로와 듀티 사이클 보정 방법 |
US8233303B2 (en) * | 2006-12-14 | 2012-07-31 | Rambus Inc. | Multi-die memory device |
CN101365273B (zh) * | 2007-08-08 | 2012-06-27 | 群康科技(深圳)有限公司 | 背光调节电路 |
JP5504507B2 (ja) * | 2008-10-20 | 2014-05-28 | 国立大学法人 東京大学 | 集積回路装置 |
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JP2019128829A (ja) * | 2018-01-25 | 2019-08-01 | 東芝メモリ株式会社 | 半導体記憶装置及びメモリシステム |
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2018
- 2018-01-25 JP JP2018010660A patent/JP2019128829A/ja active Pending
- 2018-08-06 CN CN201810887364.4A patent/CN110085274B/zh active Active
- 2018-08-06 TW TW108116319A patent/TWI791112B/zh active
- 2018-08-06 TW TW107127308A patent/TWI668697B/zh active
- 2018-09-02 US US16/120,275 patent/US10720221B2/en active Active
-
2020
- 2020-06-08 US US16/895,689 patent/US11177008B2/en active Active
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CN104734697A (zh) * | 2013-11-19 | 2015-06-24 | 英特尔公司 | 使用异步数字采样的时钟校准 |
CN107430548A (zh) * | 2015-03-06 | 2017-12-01 | 东芝存储器株式会社 | 存储装置的控制方法、及存储装置 |
US20170308328A1 (en) * | 2016-04-20 | 2017-10-26 | Samsung Electronics Co., Ltd. | Computing system, nonvolatile memory module and method of storage device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112466356A (zh) * | 2019-09-06 | 2021-03-09 | 铠侠股份有限公司 | 半导体装置及其控制方法 |
CN112466356B (zh) * | 2019-09-06 | 2024-02-23 | 铠侠股份有限公司 | 半导体装置及其控制方法 |
CN113496736A (zh) * | 2020-03-19 | 2021-10-12 | 铠侠股份有限公司 | 半导体集成电路、存储器控制器以及存储器系统 |
CN113496736B (zh) * | 2020-03-19 | 2024-07-05 | 铠侠股份有限公司 | 半导体集成电路、存储器控制器以及存储器系统 |
WO2023245923A1 (zh) * | 2022-06-22 | 2023-12-28 | 长鑫存储技术有限公司 | 存储器器件和zq校准方法 |
Also Published As
Publication number | Publication date |
---|---|
CN110085274B (zh) | 2023-08-18 |
US20190228826A1 (en) | 2019-07-25 |
TWI668697B (zh) | 2019-08-11 |
US11177008B2 (en) | 2021-11-16 |
JP2019128829A (ja) | 2019-08-01 |
TW201933367A (zh) | 2019-08-16 |
US20200303021A1 (en) | 2020-09-24 |
TW201933368A (zh) | 2019-08-16 |
US10720221B2 (en) | 2020-07-21 |
TWI791112B (zh) | 2023-02-01 |
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Address after: Tokyo Applicant after: Kaixia Co.,Ltd. Address before: Tokyo Applicant before: TOSHIBA MEMORY Corp. Address after: Tokyo Applicant after: TOSHIBA MEMORY Corp. Address before: Tokyo Applicant before: Pangea Co.,Ltd. |
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