WO2014175896A1

WO2014175896A1 - Voltage initialization of a memory

Info

Publication number: WO2014175896A1
Application number: PCT/US2013/038435
Authority: WO
Inventors: David W. Chrudimsky; Padmaraj Sanjeevarao; Jon S. Choy
Original assignee: Freescale Semiconductor, Inc.
Priority date: 2013-04-26
Filing date: 2013-04-26
Publication date: 2014-10-30

Abstract

A memory including a plurality of word line drivers and two charge pumps. During an initialization mode, a first charge pump provides a supply voltage to a first set of word line drivers and a second charge pump provides a voltage to a second set of word line drivers. During a normal read operation, the second charge pump supplies a supply voltage to the word line driver used for the read operation. During a normal mode write operation, the first charge pump supplies a supply voltage to the word line driver being used for the write operation.

Description

VOLTAGE INITIALIZATION OF A MEMORY

BACKGROUND OF THE INVENTION

Field of the Invention

[0001] This invention relates in general to memories and more specifically to initialization of voltages to a memory. Description of the Related Art

[0002] Memories include data cells and circuitry that receive voltages for operation. During a reset, the voltages supplied to those circuits take time to transition to desired levels. One example is a voltage supplied to a word line of a memory. Transitioning modes of operation of the memory may require a change in word line voltage. Because of parasitic capacitance of the voltage supply line to the word line driver circuitry, the change in voltage supplied to the word line may not occur as quickly as desired.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0004] Figure 1 is a circuit diagram of a memory according to one embodiment of the present invention.

[0005] Figure 2 is a timing diagram of a memory according to one embodiment of the present invention.

[0006] The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The Figures are not necessarily drawn to scale. DETAILED DESCRIPTION

[0007] The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting. [0008] As disclosed herein, a memory includes a plurality of word line drivers and a plurality of charge pumps for providing supply voltages to the word line drivers for writing and reading data to and from memory cells of the memory. The memory cells include a first subset of memory cells that are coupled to a first set of word line drivers that, during a portion of an initialization of the memory, receive a supply voltage from a charge pump. The other cells of the memory are coupled to a second set of word line drivers that, during the same portion of the initialization mode, receive a supply voltage from another charge pump. During a normal mode of operation, the second set of word line drivers receive a supply voltage from the first charge pump during a read operation and receive a supply voltage from the second charge pump during a write operation (e.g. erase or program).

[0009] Figure 1 is a block diagram of a memory 101 according to one

embodiment of the present invention. Memory includes memory cells 103 which are divided into a number of blocks of memory cells with blocks 105, 1 07, and 1 1 1 being shown in Figure 1 . In one embodiment, each block represents a portion of a memory array. However, in other embodiments, each block may represent an array. In one embodiment, the cells are arranged in columns and rows of cells.

[0010] Cells 103 are used to store data received from write data lines (WRITE DATA) of a memory bus and to provide data on read data lines (READ DATA) of the memory bus. Read data lines of each block (RD1 , RD2, and RDN) are coupled to a read multiplexer 102 whose output is coupled to the read data lines of the memory bus. The read multiplexer 102 is controlled by read decode signals from controller 133. The write data from the memory bus is provided to write demultiplexer 104 which distributes the data to the selected memory locations based on the write decode signals from controller 133. In some embodiments, the memory blocks include sense amplifiers (not shown) for determining the value of the cell data stored in cells coupled to the sense amplifiers.

[001 1 ] Block 107 includes memory portion 109 which stores boot data for a system that includes memory 101 . In one embodiment, boot data includes code that is first executed by a processor (not shown) during an initialization mode of the system. Boot data may also include trim data that is used to calibrate circuitry of the system (e.g. for adjusting voltage reference values to the charge pumps or setting read and write voltages). In the embodiment shown, block 107 includes other data other than the boot data. However, in some embodiments, all data in block 107 is boot data.

[0012] In one embodiment, memory cells 103 are non volatile memory cells. In one embodiment, the cells are flash memory cells with each cell including a charge storage structure in which charge is stored to selectively adjust a threshold voltage of a transistor of the cell. In one embodiment, the charge storage structure is a floating gate structure or a layer of nanocrystals, but may be of other types of structures in other embodiments. Data is written to a memory cell by selectively storing charge in the charge storage structures to represent one logic value where having no charge stored represents the other logic value. In other embodiments, memory cells 103 may include other types of other memory cells (e.g. volatile memory cells). [0013] In the embodiment shown, each memory cell is coupled to a word line driver by a word line that is connected to the gate of a transistor of the memory cell. Word line driver circuitry 1 13 includes a number of word line driver sets 1 15, 1 17, and 1 19 with each word line driver set coupled via a set of word lines (WL1 , WL2, and WLN) to a block (105, 107, and 1 1 1 ) of memory cells. In one embodiment, each block includes one or more rows of memory cells with each row coupled to a word line of a word line set. Each word line is coupled to a word line driver circuit of a word line driver set (1 15, 1 17, and 1 19). In one embodiment, each word line driver set includes only one word line driver coupled to one word line. [0014] Each word line driver set (1 15, 1 17, and 1 19) receives a word line supply voltage from a power switch (121 , 123, and 125). For example, driver set 1 15 receives word line supply voltage 1 (WLSupply 1 ) from switch 121 . Each of power switches 121 , 123, and 125 includes an input to receive a supply voltage from a read charge pump 129 and a second input to receive a supply voltage from a write power switch 127. Write power switch 127 includes an input to receive a voltage from write charge pump 131 and a second input to receive a supply voltage from a power supply terminal (VDD).

[0015] Power switches 121 , 123, 125, and 127 each include control circuitry for determining which of the supply voltages provided to the switch inputs is to be provided to the output of the switch. In the embodiment shown, the control circuit of each switch receives control signals from a controller 133. In one embodiment, a single signal line controls the position of the switch. However, in other embodiments, multiple signal lines may control the position of the switch. [0016] In the embodiment shown, memory 101 is a read while write memory where different blocks can be written and read to concurrently. Controller 133 is coupled to a memory bus that carries address signals, data signals, and control signals. In the embodiment shown, the memory bus includes both write address signal lines (WRITE ADDRESS) for carrying signals indicating which of the memory cells of cells 103 are to be written, and read address signal lines (READ ADDRESS) for carrying signals indicating which of the memory cells of cells 103 are to be read. Controller 133 includes decode circuitry for decoding the address signals to provide read decode signals and write decode signals to the word line driver circuitry 1 13 that is indicative of the cells to be read from or written to. The word line driver circuitry asserts the word lines that are indicated by the read decode signals or the write decode signals. Controller 133 also generates write select signals to indicate which blocks of the cells are being written to.

[0017] Controller 133 also receives a READ signal to indicate when a read transaction is being initiated on a bus and a WRITE signal to indicate when a write transaction is being initiated on the bus. Controller 133 provides a voltage select signal to switch 127 to control switch 127 to provide either a voltage from the VDD terminal or a voltage from write charge pump 131 at its output. Controller 133 may receive and provide other signals in other embodiments. In some embodiments, controller 133 is a hardware controller, but in other embodiments, controller 133 may have other configurations such as including a processor for executing code.

[0018] In the embodiment shown, power switches 121 , 123, and 125 use the write select signals for controlling which supply voltage to provide at its output. In one embodiment, the write select signals allow for multiple blocks to be selected simultaneously in any combination desired. Thus, for the circuit of Figure 1 , any one or any combination of power switches 121 , 123, or 125 maybe be selectively controlled to provide the supply voltage from the write power switch 127, based upon the particular combination of write select signals. However, the power control switches 121 , 123, and 125 may be controlled by other signal line configurations in other embodiments. For example, controller 133 may output a control signal line to each power switch to selectively control each power switch. In one embodiment, each of power switches 121 , 123, and 125 is configured to provide a supply voltage from read charge pump 129 unless the write select signals indicate that the particular switch is to provide a supply voltage from write power switch 127. Other

embodiments may omit power switch 127 where write charge pump 131 is connected to an input of each of power switches 121 , 123, and 125. Also, in some embodiments, each power switch 121 , 123, and 125 may be set such that its output provides neither of the voltages of its inputs.

[0019] In the embodiment shown, write charge pump 131 receives a voltage level select signal from controller 133 to control the value of the voltage level of its output. In some embodiments, depending upon the voltage level select switch, write charge pump 131 can provide one voltage for writing and erasing the memory cells 103 and a second voltage value equal to the voltage of read charge pump 129's output. In other embodiments, write charge pump 131 is also used to provide a sweeping voltage signal that is used for read verify operations. In one embodiment, the read voltage is 4.5 volts, the write voltage is 9 volts, and VDD is 3 volts, but these voltages may be of other values in other embodiments. [0020] Some signals are not shown in Figure 1 . For example, controller 133 may provide a charge pump enable signals to charge pumps 129 and 131 to activate and deactivate the charge pumps. Also, in some embodiments, the read data out signals (READ DATA) and the write data out signals (WRITE DATA) are provided to controller 133. In other embodiments, memory 101 may be of an other type of memory configuration such as a memory that does not allow concurrent read and write accesses. For example, embodiments of such a memory would include an address bus for both reads and writes and/or a data bus for both read data and write data. [0021 ] In one embodiment, during a normal mode read operation of selected cells of memory cells 103, the power switches 121 , 123, and 125 are placed in a condition to provide a voltage from read charge pump 129 to the word line supply voltage lines (e.g. WLSupplyl ). In one embodiment, during a normal mode write operation to cells of memory cells 103, the specific power switch (121 ,123, and 125) of the block (105, 107, or 1 1 1 ) that contains the cells to be written is placed in a condition to provide the supply voltage from power switch 127 on the specific word line supply voltage line (e.g. WLSupplyl ) coupled to the word line driver(s) providing the word line(s) to the cells being written to (programmed or erased). In some embodiments, each word line driver circuit includes its own power switch. In other embodiments, the power switch may be distributed through the word line driver circuits of a set.

[0022] The word line drivers use the word line supply voltages received via the word line supply voltage lines in providing the word line signals. In some

embodiments, an asserted word line is driven by its associated word line driver at the voltage level of the word line supply voltage provided to the word line driver. A read voltage is a voltage of a word line supply voltage that is needed to drive a word line to a voltage level to perform a proper read operation. A write voltage is a voltage of a word line supply voltage that is needed to drive a word line to perform a proper write operation (e.g. program or erase operation).

[0023] Prior to beginning normal mode operations, the voltage of the word line supply voltages should be initialized to operable values for proper read operations of the memory cells. At times after a reset of the memory, the voltage values of the word line supply voltage lines (e.g. WLSupplyl ) may not be at desired read values. Accordingly, read operations should not be performed until the word line supply voltage lines have been initialized to the proper level. [0024] With prior art circuits, the initialization of the word line supply voltage line was performed by a read charge pump where all of the word line supply voltage lines were coupled to the read charge pump during the initialization process. With such circuits, the read charge pump would have to charge the parasitic capacitances and currents associated with each word line supply voltage line. [0025] With embodiments of the present invention, during an initialization mode, the read charge pump is selectively coupled via the power switches to the word line supply voltage line(s) of the block or blocks (107) that include the boot data (in memory portion 109). The other word line supply voltage lines are biased by the output of switch 127 (which is set to provide the voltage of the write charge pump output) during that portion of the initialization mode. Accordingly, the read charge pump 129 output can more quickly bring the voltage level of the particular word line supply voltage line to the read level in that there is less parasitic capacitance to be charged up due to the reduced number word line supply voltage lines being supplied. The other word line supply voltage lines can be charged more slowly in that their data is not required to be read as quickly as the boot data.

[0026] Figure 2 is a timing diagram showing the operation of memory 101 during an initialization mode and a normal mode of operation. Shown in Figure 2 is the voltage level of the word line supply voltage line 2 (WLSuppy2) which supplies the supply voltage to word line driver set 1 17. Word line driver set 1 17 is coupled to block 107 which contain boot data in memory portion 109. The other line shows the voltage level of the other word line supply voltage lines (WLSupplyl and WLSupply N) of memory 101 .

[0027] At time T1 , a reset operation is performed. In some embodiments, a reset operation may be performed in response to a return from a low power mode in which T1 represents the time when leaving the low power mode. A reset operation may also be performed when the device is turned on. In the embodiment shown, between times T1 and 12, the voltage level of a word line supply voltage line may be at an unknown value (e.g. between 0 volts and the write line voltage (WV)) depending upon the previous operation. At time T1 , power switches 121 , 123, 125 and 127 are placed in a state to provide the voltage from the VDD terminal to all of the word line supply voltage lines to pull the voltage of those lines to VDD regardless of the voltage level of the lines prior to time T1. In other embodiments, the lines are not biased initially to VDD or may be biased at another voltage. [0028] At time T2, power switch 127 is placed in a state to provide the voltage of the write charge pump 131 to the inputs of power switches 121 and 125. At time 12, power switch 123 is placed in a state to provide at its output, the voltage of read charge pump 129 to the word line supply voltage line 2 (WLSuppy2). The other power switches 121 and 125 are placed in a state to provide at their outputs, the voltage of write charge pump 131. In one embodiment, charge pump 131 is placed in a state to provide a read voltage at its output. However, it may provide other voltages at this time in other embodiments.

[0029] Because only one word line supply voltage line is driven by read charge pump 129 at this time, the voltage of that word line supply voltage line (WLSupply2) increases more rapidly than the voltage of the other word line supply voltage lines (WLSupplyl and WLSupplyN) which are being pulled up by write charge pump 131 . During this time, the parasitic capacitances and currents associated with the other word line supply voltage lines increases the time needed to pull those word line supply voltage lines to the read voltage (RV). [0030] At time T3, the voltage of word line supply voltage line 2 is at a level (RV) where it's sufficient to perform a read operation of block 107. At this time, the boot data is read. Also at this time, voltage of the other word line supply voltage lines is not at the desired read voltage level (RV). However, since they are not supplying word line drivers of blocks that contain boot data, no reads are needed to be performed at this time. [0031 ] At time T4, the word line supply voltage lines are initialized to the read voltage level (RV) and memory 101 enters a normal operating mode. At this time, the word line supply voltage lines for all other blocks are switched to be biased by read charge pump 129 at the read voltage level (RV). In this mode, the word line supply voltage line for any block being written to is biased with a voltage from write charge pump 131 . In some embodiments, the word line supply voltages of the blocks not being written to during a write operation are supplied with a voltage from read charge pump 129. In some embodiments, there may be additional startup time to achieve stability after T4 prior to the start of normal operations. [0032] In one embodiment, times T1 , T2, and T3 are fixed times set by controller 133. However in other embodiments, controller 133 may include measurement circuitry to determine when the supply lines are at the desired voltage levels. In other embodiments, a memory may operate in other ways during an initialization mode. [0033] Providing a system that reduces the number of word line supply voltage lines coupled to a read charge pump during an initialization mode may

advantageously provide for a memory where specific memory cells are capable of being read during the initialization mode prior to other memory cells being able to be read. Furthermore, charging the other word line supply voltages with the write charge pump allows for separate charging of the other word line supply voltage lines during the initialization mode using existing circuitry without having to add another charge pump.

[0034] In one embodiment, a memory includes a first charge pump, a second charge pump, a plurality of memory cells, and a plurality of word line drivers for providing word line signals to the plurality of memory cells. The memory is configured that during at least a portion of an initialization mode, a first subset of the plurality of word line drivers receives a supply voltage from the first charge pump, and a second subset of the plurality of word line drivers receive a supply voltage from the second charge pump. The memory is configured that during a normal mode read operation to cells of the plurality of memory cells, for both word line drivers of the first subset and the second subset, a word line driver associated with the cells being read receives a supply voltage from the first charge pump. The memory is configured that during normal write operation to cells of the plurality of memory cells, for word line drivers of the second subset, a word line driver associated with the cells being written receives a supply voltage from the second charge pump.

[0035] In another embodiment, a method of operating a memory, includes during an initialization mode, supplying a first supply voltage from a first charge pump to a first subset of a plurality of word line drivers of the memory, supplying a second supply voltage from a second charge pump to a second subset of the plurality of word line drivers, wherein the second subset includes at least one word line driver, and reading data using at least one word line driver of the second subset of the plurality of word line drivers while being supplied the second supply voltage from the second charge pump and while the first subset is being supplied the first supply voltage by the first charge pump. The method includes performing a normal mode read operation using a word line driver of the first subset of the plurality of word line drivers while the word line driver is being supplied a supply voltage from the second charge pump.

[0036] In another embodiment, a method of operating a memory device, includes during an initialization mode, operating a write charge pump to provide a first supply voltage to a first set of a plurality of word line drivers and operating a read charge pump to provide a second supply voltage to a second set of the plurality of word line drivers. A supply voltage input of each of the first set and the second set are charged to approximately the same voltage level when the initialization mode is complete.

[0037] While particular embodiments of the present invention have been shown and described, it will be recognized to those skilled in the art that, based upon the teachings herein, further changes and modifications may be made without departing from this invention and its broader aspects, and thus, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention.

Claims

CLAIMS What is claimed is:

1. A memory comprising:

a first charge pump;

a second charge pump;

a plurality of memory cells;

a plurality of word line drivers for providing word line signals to the plurality of

memory cells;

wherein the memory is configured that during at least a portion of an initialization mode, a first subset of the plurality of word line drivers receives a supply voltage from the first charge pump, and a second subset of the plurality of word line drivers receive a supply voltage from the second charge pump;

wherein the memory is configured that during a normal mode read operation to cells of the plurality of memory cells, for both word line drivers of the first subset and the second subset, a word line driver associated with the cells being read receives a supply voltage from the first charge pump;

wherein the memory is configured that during a normal write operation to cells of the plurality of memory cells, for word line drivers of the second subset, a word line driver associated with the cells being written receives a supply voltage from the second charge pump.

2. The memory of claim 1 wherein the memory is configured that during a normal mode read operation to cells of the plurality of memory cells, the plurality of word line drivers receives a supply voltage from the first charge pump.

3. The memory of claim 1 , wherein the first subset of the plurality of word line drivers is associated with a first set of memory cells of the plurality of memory cells, wherein the first set of memory cells includes data that is read prior to a completion of an initialization mode, wherein a second set of memory cells of the plurality of memory cells associated with the second subset of the plurality of word line drivers are not read until after the initialization mode is complete.

4. The memory of claim 1 , further comprising: a controller, the controller controlling a voltage of an output of the second charge pump at a plurality of voltage levels, wherein the plurality of voltage levels includes a read voltage level and a write voltage level.

5. The memory of claim 4 wherein the output of the second charge pump provides a read voltage level to the second subset of the plurality of word line drivers at an end of the initialization mode.

6. The memory of claim 1 further comprising a plurality of power switches, each power switch of the plurality of power switches includes an output coupled to supply a word line supply voltage to at least one word line driver of the plurality of word line drivers, wherein each of the plurality of power switches includes a first input for receiving a supply voltage from an output of the first charge pump and a second input for receiving a supply voltage from the output of the second charge pump.

7. The memory of claim 6 further comprising a power switch including an output coupled to the second input of each of the plurality of power switches, a first input coupled to the output of the second charge pump, and a second input coupled to a voltage source.

8. The memory of claim 1 wherein during the at least a portion of an initialization mode, a voltage of an output of the first charge pump rises faster than a voltage of an output of the second charge pump.

9. The memory of claim 1 , wherein the first subset of the plurality of word line drivers is associated with a first set of memory cells of the plurality of memory cells, wherein the first set of memory cells includes boot data.

10. The memory of claim 1 wherein the memory is configured that during normal write operation to cells of the plurality of memory cells, for both word line drivers of the first subset and the second subset, a word line driver associated with the cells being written receives a supply voltage from the second charge pump.

1 1. A method of operating a memory, comprising:

during an initialization mode: supplying a first supply voltage from a first charge pump to a first subset of a plurality of word line drivers of the memory;

supplying a second supply voltage from a second charge pump to a second subset of the plurality of word line drivers, wherein the second subset includes at least one word line driver;

reading data using at least one word line driver of the second subset of the plurality of word line drivers while being supplied the second supply voltage from the second charge pump and while the first subset is being supplied the first supply voltage by the first charge pump;

performing a normal mode read operation using a word line driver of the first subset of the plurality of word line drivers while the word line driver is being supplied a supply voltage from the second charge pump.

12. The method of claim 1 1 , further comprising:

performing a normal mode write operation using a word line driver of the plurality of word line drivers while supplying a supply voltage to the word line driver from the first charge pump.

13. The method of claim 12 wherein the performing the normal mode write operation and performing the normal mode read operation are performed concurrently with different word line drivers of the plurality of word line drivers.

14. The method of claim 1 1 , wherein during the initialization mode, an output voltage of the second charge pump reaches a read voltage level faster than an output voltage of the first charge pump.

15. The method of claim 1 1 wherein the performing the reading data during the initialization mode includes performing the reading data to retrieve boot data.

16. The method of claim 1 1 wherein at least an initial portion of the reading data during the initialization mode is performed when a first charge pump output voltage is less than an output voltage of the second charge pump and is less than a required voltage level for performing a read operation by a word line driver.

17. A method of operating a memory device, comprising:

during an initialization mode: operating a write charge pump to provide a first supply voltage to a first set of a plurality of word line drivers;

operating a read charge pump to provide a second supply voltage to a

second set of the plurality of word line drivers, wherein a supply voltage input of each of the first set and the second set are charged to approximately the same voltage level when the initialization mode is complete.

18. The method of claim 17, further comprising:

during a normal mode write operation, operating the write charge pump to provide a write supply voltage to a selected set of at least one word line driver of the plurality of word line drivers.

19. The method of claim 18 wherein the write supply voltage is a higher voltage level than the same voltage level.

20. The method of claim 17, further comprising:

during a normal mode read operation, operating the read charge pump to provide a read supply voltage to the plurality of word line drivers.