CN110021668A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN110021668A
CN110021668A CN201811619564.8A CN201811619564A CN110021668A CN 110021668 A CN110021668 A CN 110021668A CN 201811619564 A CN201811619564 A CN 201811619564A CN 110021668 A CN110021668 A CN 110021668A
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China
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gate electrode
grid
partition pattern
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pattern
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CN201811619564.8A
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Inventor
李正韩
朴成哲
李允逸
金并基
全英敏
河大元
黄寅灿
朴宰贤
申宇哲
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110021668A publication Critical patent/CN110021668A/zh
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Abstract

一种半导体器件包括：多个栅电极，在衬底上交叉有源图案并沿第二方向延伸，所述多个栅电极在第一方向上彼此间隔开；栅极分隔图案，具有在第一方向上的长轴并且在所述多个栅电极中的两个栅电极之间，所述多个栅电极中的所述两个栅电极在第二方向上彼此相邻；以及多个栅极间隔物，覆盖所述多个栅电极中的相应栅电极的侧壁，栅极间隔物交叉栅极分隔图案并沿第二方向延伸。栅极分隔图案包括沿第一方向延伸的下部、从下部突出并具有第一宽度的中间部分、以及在两个相邻的栅极间隔物之间并从中间部分突出的上部，上部具有小于第一宽度的第二宽度。

Description

半导体器件
技术领域
发明构思涉及半导体器件，更具体地，涉及包括场效应晶体管的半导体器件。
背景技术
半导体器件包括由金属氧化物半导体场效应晶体管(MOSFET)构成的集成电路。随着半导体器件变得高度集成，MOSFET的按比例缩小也在加速，因而半导体器件的工作特性可能劣化。因此，已经开发了各种研究来制造这样的半导体器件，其具有优异的性能同时克服了由半导体器件的高集成度所致的限制。
发明内容
发明构思的一些示例实施方式提供了包括高度集成的场效应晶体管的半导体器件。
发明构思不限于上述内容，并且以上未提及的其它目的将由以下描述清楚。
根据发明构思的一些示例实施方式，一种半导体器件可以包括：半导体衬底，包括沿第一方向延伸的有源图案；多个栅电极，交叉有源图案并沿第二方向延伸，所述多个栅电极在第一方向上彼此间隔开；栅极分隔图案，具有在第一方向上的长轴并且在所述多个栅电极中的两个栅电极之间，所述多个栅电极中的所述两个栅电极在第二方向上彼此相邻；以及多个栅极间隔物，覆盖所述多个栅电极中的相应栅电极的侧壁，栅极间隔物交叉栅极分隔图案并沿第二方向延伸。栅极分隔图案包括沿第一方向延伸的下部、从下部突出并具有第一宽度的中间部分、以及在两个相邻的栅极间隔物之间并从中间部分突出的上部，上部具有小于第一宽度的第二宽度。
根据发明构思的一些示例实施方式，一种半导体器件可以包括：半导体衬底，包括沿第一方向延伸的有源图案；多个栅电极，交叉有源图案并沿第二方向延伸，所述多个栅电极在第一方向上彼此间隔开；栅极分隔图案，在所述多个栅电极中的至少两个栅电极之间，所述至少两个栅电极在第二方向上彼此相邻，栅极分隔图案具有在第一方向上的长轴；以及多个栅极间隔物，覆盖所述多个栅电极中的相应栅电极的侧壁，栅极间隔物交叉栅极分隔图案并沿第二方向延伸。栅极分隔图案包括在所述多个栅极间隔物中的两个相邻的栅极间隔物之间的上部、以及在栅极间隔物之下沿第一方向延伸的下部。每个栅极间隔物包括低k电介质材料，该低k电介质材料具有比栅极分隔图案的介电常数小的介电常数。
根据发明构思的一些示例实施方式，一种半导体器件可以包括：半导体衬底，包括第一有源图案和第二有源图案，第一有源图案和第二有源图案沿第一方向延伸；多个第一栅电极，交叉第一有源图案并沿第二方向延伸；多个第二栅电极，交叉第二有源图案并沿第二方向延伸，第二栅电极在第二方向上与第一栅电极间隔开；栅极分隔图案，在所述多个第一栅电极中的一个与所述多个第二栅电极中的一个之间，所述多个第一栅电极中的所述一个和所述多个第二栅电极中的所述一个在第二方向上彼此相邻；多个栅极间隔物，沿第二方向从所述多个第一栅电极和所述多个第二栅电极中的相应栅电极的侧壁延伸；多个第一外延层，在第一有源图案上并且在第一栅电极之间；以及多个第二外延层，在第二有源图案上并且在第二栅电极之间。栅极分隔图案包括：多个第一部分，每个第一部分在所述多个第一栅电极中的所述一个与所述多个第二栅电极中的所述一个之间具有第一高度；以及多个第二部分，在第一方向上连接到所述多个第一部分并在第二方向上位于所述多个第一外延层中的一个与所述多个第二外延层中的一个之间，其中每个第二部分具有小于第一高度的第二高度。
其它示例实施方式的细节被包括在说明书和附图中。
附图说明
图1示出显示了根据发明构思的一些示例实施方式的半导体器件的简化俯视图。
图2A至12A示出显示了根据发明构思的一些示例实施方式的制造半导体器件的方法的俯视图。
图2B至12B、2C至12C、2D至12D和2E至12E示出沿图2A至12A的线B-B'、C-C'、D-D'和E-E'截取的剖视图。
图10F和12F示出显示了根据发明构思的一些示例实施方式的制造半导体器件的方法的透视图。
图13、14和15示出显示了根据发明构思的一些示例实施方式的制造半导体器件的方法的剖视图和俯视图。
图16和17示出分别沿图15的线B-B'和D-D'截取的剖视图。
具体实施方式
现在将参照附图描述根据发明构思的一些示例实施方式的半导体器件制造方法和通过该方法制造的半导体器件。
图1示出显示了根据发明构思的一些示例实施方式的半导体器件的简化俯视图。
参照图1，半导体衬底100可以在其上提供有集成的标准单元SC，集成的标准单元SC包括诸如逻辑和门或逻辑乘积门的逻辑器件。例如，标准单元SC可以包括：基础单元，诸如与门、或门、或非门和反相器；复合单元，诸如OAI(或/与/反相器)门和AOI(与/或/反相器)门；和/或存储元件，诸如简单的主从触发器和锁存器。
多个标准单元SC可以沿第一方向D1和交叉第一方向D1的第二方向D2二维地布置。每个标准单元SC可以包括其中形成NMOS场效应晶体管的第一阱区域R1和其中形成PMOS场效应晶体管的第二阱区域R2。
图2A至12A示出显示了根据发明构思的一些示例实施方式的制造半导体器件的方法的俯视图。图2B至12B、2C至12C、2D至12D和2E至12E示出沿图2A至12A的线B-B'、C-C'、D-D'和E-E'的剖视图。图10F和12F示出显示了根据发明构思的一些示例实施方式的制造半导体器件的方法的透视图。
参照图1及图2A至2E，半导体衬底100可以包括第一阱区域R1和第二阱区域R2。在一些示例实施方式中，NMOS场效应晶体管可以在第一阱区域R1上，并且PMOS场效应晶体管可以在第二阱区域R2上。半导体衬底100可以是例如硅衬底、锗衬底、绝缘体上硅(SOI)衬底和/或绝缘体上锗(GOI)衬底。
半导体衬底100可以被图案化以形成有源图案101。在第一阱区域R1和第二阱区域R2的每个上，多个有源图案101可以沿第一方向D1延伸，并且可以在交叉第一方向D1的第二方向D2上彼此间隔开。在一些示例实施方式中，有源图案101可以包括形成在第一阱区域R1上的第一有源图案和形成在第二阱区域R2上的第二有源图案。
有源图案101的形成可以包括在半导体衬底100上形成掩模图案(未示出)、然后各向异性地蚀刻半导体衬底100以形成沟槽。有源图案101可以是半导体衬底100的部分，并且可以由形成在半导体衬底100上的沟槽限定。每个有源图案101可以具有其长轴沿第一方向D1延伸的线形或条形，并且可以在形状和布置上各种各样地改变。
器件隔离层103可以形成在有源图案101之间。器件隔离层103可以具有比有源图案101的顶表面低的顶表面，因而有源图案101的上部可以被暴露。器件隔离层103的形成可以包括形成绝缘层以填充沟槽、平坦化绝缘层以暴露掩模图案的顶表面、以及使绝缘层的平坦化的顶表面凹入以暴露有源图案101的上侧壁。
在形成器件隔离层103之前，缓冲绝缘层102可以被形成以共形地覆盖有源图案101的表面。缓冲绝缘层102可以由硅氧化物层、硅氮化物层和/或硅氮氧化物层形成。缓冲绝缘层102可以通过热氧化、化学气相沉积(CVD)、原子层沉积(ALD)和/或类似方法形成。
参照图3A至3E，第一虚设栅极层113可以被形成以覆盖具有有源图案101的半导体衬底100的整个表面。
第一虚设栅极层113可以填充在有源图案101之间，并且可以由对缓冲绝缘层102、器件隔离层103和有源图案101表现出蚀刻选择性的材料形成。例如，第一虚设栅极层113可以由掺杂杂质的多晶硅层、无掺杂的多晶硅层、硅锗层和/或硅碳化物层形成。第一虚设栅极层113可以通过化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)和/或类似方法形成，并且可以执行平坦化工艺以使第一虚设栅极层113具有平坦的顶表面。
第一硬掩模图案MP1可以形成在第一虚设栅极层113上。第一硬掩模图案MP1可以具有部分地暴露第一虚设栅极层113的开口。第一硬掩模图案MP1可以由硅氮化物层和/或硅氮氧化物层形成，例如包括硅氮化物层和/或硅氮氧化物层。
第一硬掩模图案MP1可以在对第一虚设栅极层113的各向异性蚀刻(其形成部分地暴露器件隔离层103的开口OP)期间用作蚀刻掩模。在用于形成开口OP的各向异性蚀刻工艺中，器件隔离层103可以用作蚀刻停止层。各向异性蚀刻工艺可以使开口OP具有上宽度以及小于上宽度的下宽度。例如，开口OP可以具有其宽度朝半导体衬底100逐渐减小的侧壁轮廓。此外，在用于形成开口OP的各向异性蚀刻工艺中，可能发生过蚀刻，使得器件隔离层103可以在暴露于开口OP的部分上被凹入。
在一些示例实施方式中，开口OP可以在第一阱区域R1与第二阱区域R2之间、以及在第二方向D2上彼此相邻的有源图案101之间。开口OP可以具有其长轴沿第一方向D1延伸的条形。开口OP在第一方向D1上的长度可以大于将在后续工艺中形成的虚设栅极图案的宽度。虽然图中仅显示了一个开口OP，但发明构思不限于此，可以提供多个开口。所述多个开口可以具有彼此不同的形状和/或尺寸。
参照图4A至4E，虚设间隔物121可以被形成以覆盖开口OP的内壁。虚设间隔物121的形成可以包括在具有开口OP的第一虚设栅极层113上共形地沉积虚设间隔物层、以及通过对虚设间隔物层执行整体各向异性蚀刻工艺而暴露器件隔离层103。虚设间隔物层可以具有小于开口OP的宽度的一半的厚度。在一些示例实施方式中，虚设间隔物121和第一虚设栅极层113可以由相同的材料形成，例如多晶硅层。或者，虚设间隔物121可以由对第一虚设栅极层113表现出蚀刻选择性的材料形成；例如，虚设间隔物121可以由硅氧化物层形成。
在形成虚设间隔物121之后，电介质栅极分隔层123可以被形成以填充开口OP。电介质栅极分隔层123可以在第一硬掩模图案MP1上形成为完全填充开口OP。
电介质栅极分隔层123可以由对第一虚设栅极层113和虚设间隔物121表现出蚀刻选择性的绝缘材料形成。电介质栅极分隔层123可以包括硅氧化物层、硅氮化物层、硅氮氧化物层和低k电介质层中的一个或更多个。电介质栅极分隔层123可以通过化学气相沉积(CVD)、原子层沉积(ALD)和/或类似方法形成。
参照图5A至5E，可以对电介质栅极分隔层123执行平坦化工艺以暴露第一虚设栅极层113，从而形成初始栅极分隔图案124。在一些示例实施方式中，第一硬掩模图案MP1可以在初始栅极分隔图案124的形成期间被去除。在形成初始栅极分隔图案124之后，第一虚设栅极层113可以具有在与虚设间隔物121和初始栅极分隔图案124的顶表面的水平基本相同的水平处的顶表面。初始栅极分隔图案124可以具有比第一虚设栅极层113的底表面或器件隔离层103的顶表面低的底表面。
初始栅极分隔图案124可以在第一阱区域R1与第二阱区域R2之间的器件隔离层103上，并且可以具有其长轴沿第一方向D1延伸的条形。虚设间隔物121可以围绕初始栅极分隔图案124的侧壁。初始栅极分隔图案124在第二方向D2上的宽度可以小于开口OP的宽度，并且可以取决于虚设间隔物121的厚度而变化。
第二虚设栅极层115可以被形成以覆盖半导体衬底100的整个表面。例如，第二虚设栅极层115可以覆盖第一虚设栅极层113、虚设间隔物121和初始栅极分隔图案124。在一些示例实施方式中，第二虚设栅极层115和第一虚设栅极层113可以包括相同的材料(例如多晶硅)。
第二虚设栅极层115可以在其上设置有第二硬掩模图案MP2，每个第二硬掩模图案MP2具有沿第二方向D2延伸的线形。第二硬掩模图案MP2中的一个或更多个可以跨越初始栅极分隔图案124。
参照图6A至6E，第二硬掩模图案MP2可以用作蚀刻掩模，以顺序地且各向异性地蚀刻第一虚设栅极层113和第二虚设栅极层115以及初始栅极分隔图案124，该蚀刻工艺可以形成虚设栅极图案DGP和栅极分隔图案125。
虚设栅极图案DGP可以在第一方向D1上彼此间隔开并沿第二方向D2延伸以交叉有源图案101。栅极分隔图案125可以使虚设栅极图案DGP中的一些在第二方向D2上彼此分开。在一些示例实施方式中，每个虚设栅极图案DGP可以包括被图案化的第一虚设栅极层113和第二虚设栅极层115。
在用于形成虚设栅极图案DGP的各向异性蚀刻工艺中，初始栅极分隔图案124可以在第二硬掩模图案MP2之间暴露的顶表面上凹入，从而可以形成栅极分隔图案125。
例如，如图6D和6E所示，栅极分隔图案125可以包括沿第一方向D1延伸并跨越至少两个虚设栅极图案DGP的下部125a，并且还包括从下部125a突出的上部125b。下部125a可以具有在比上部125b的顶表面的水平低的水平处的顶表面。因此，栅极分隔图案125可以具有在沿第二方向D2彼此相邻的虚设栅极图案DGP之间较大的高度以及在沿第一方向D1彼此相邻的虚设栅极图案DGP之间较小的高度。栅极分隔图案125的每个上部125b可以在沿第二方向D2彼此相邻的虚设栅极图案DGP之间。栅极分隔图案125的上部125b可以具有与虚设栅极图案DGP的宽度相同的宽度W1。
此外，在用于形成虚设栅极图案DGP的各向异性蚀刻工艺中，虚设间隔物121可以在其暴露于第二硬掩模图案MP2之间的部分上被蚀刻。因此，虚设间隔物图案122可以在虚设栅极图案DGP与栅极分隔图案125之间局部地形成。
参照图7A至7E，栅极间隔物130可以被形成以覆盖每个虚设栅极图案DGP的相反两侧壁。栅极间隔物130还可以形成在栅极分隔图案125的侧壁和有源图案101的侧壁上。
栅极间隔物130的形成可以包括在其上形成了有源图案101、虚设栅极图案DGP和栅极分隔图案125的半导体衬底100上共形地沉积栅极间隔物层、以及对栅极间隔物层执行整体各向异性蚀刻工艺。
栅极间隔物130可以由对有源图案101、虚设栅极图案DGP和栅极分隔图案125表现出蚀刻选择性的绝缘材料形成。在一些示例实施方式中，栅极间隔物130可以由其介电常数小于栅极分隔图案125的介电常数的低k电介质材料形成。栅极间隔物130可以包括诸如SiC、SiCN、SiOCH、SiOC和SiOF的绝缘材料。栅极间隔物130可以具有范围从大约1.0到大约3.0的介电常数，并且可以包括无机材料、有机材料和有机-无机混合材料中的一种或更多种。备选地或另外地，栅极间隔物130可以包括多孔或无孔电介质材料。
例如，栅极间隔物130可以包括第一间隔物部分130a、第二间隔物部分130b和第三间隔物部分130c。第一间隔物部分130a可以沿第二方向D2延伸并交叉栅极分隔图案125。第二间隔物部分130b可以沿第一方向D1延伸并覆盖栅极分隔图案125的下部125a的侧壁。第三间隔物部分130c可以沿第一方向D1延伸并覆盖有源图案101的侧壁。栅极间隔物130的第一间隔物部分130a可以覆盖在第一方向D1上彼此间隔开的虚设栅极图案DGP的侧壁、以及栅极分隔图案125的上部125b的侧壁。栅极间隔物130的第一间隔物部分130a可以在栅极分隔图案125的下部125a上。栅极间隔物130的第一间隔物部分130a可以具有比栅极间隔物130的第二间隔物部分130b的高度大的高度。
参照图8A至8E，在形成栅极间隔物130之后，凹陷RS可以在每个虚设栅极图案DGP的相反两侧上形成在有源图案101上。当缓冲绝缘层102在其暴露于栅极间隔物130之间的部分上被蚀刻并且有源图案101在其暴露于栅极间隔物130之间的部分上被蚀刻时，可以形成凹陷RS。凹陷RS可以通过执行各向异性和/或各向同性蚀刻工艺而形成，在各向异性和/或各向同性蚀刻工艺的每个中虚设栅极图案DGP和栅极间隔物130被用作蚀刻掩模。
如图8D和8E所示，在一些示例实施方式中，在用于形成凹陷RS的蚀刻工艺期间，还可以对栅极分隔图案125执行蚀刻工艺，使得下部125a可以在其暴露于栅极间隔物130之间的部分上被蚀刻。然后，栅极分隔图案125的下部125a的顶表面可以被凹入，以在栅极分隔图案125的下部125a和上部125b之间形成中间部分125c。栅极分隔图案125的中间部分125c可以位于栅极间隔物130的第一间隔物部分130a下面，并且可以具有比上部125b的宽度W1大的宽度W2。栅极分隔图案125的下部125a可以具有取决于形成凹陷RS的蚀刻条件的高度。在用于形成凹陷RS的蚀刻工艺中，第二硬掩模图案MP2可以被减小厚度或者可以被去除。
参照图9A至图9E，第一外延层141可以形成在第一阱区域R1的凹陷RS中，第二外延层143可以形成在第二阱区域R2的凹陷RS中。
在一些示例实施方式中，在第一外延层141的形成之后可以形成第二外延层143，并且第一外延层141可以在第二方向D2上与第二外延层143间隔开。第一外延层141和第二外延层143可以通过执行其中暴露于凹陷RS的有源图案101用作籽晶层的选择性外延生长工艺而形成。第一外延层141和第二外延层143的每个可以包括其晶格常数与半导体衬底100的晶格常数不同的半导体材料，并且可以形成为具有多外延层。第一外延层141可以用作NMOSFET的源/漏电极，第二外延层143可以用作PMOSFET的源/漏电极。例如，第一外延层141可以由能够向虚设栅极图案DGP下面的有源图案101提供拉伸应变的材料(例如硅碳化物(SiC))形成。第二外延层143可以由能够向虚设栅极图案DGP下面的有源图案101提供压缩应变的材料(例如硅锗(SiGe))形成。
可选地，第一外延层141和第二外延层143可以在其上提供有硅化物层(未示出)，诸如镍硅化物、钴硅化物、钨硅化物、钛硅化物、铌硅化物或钽硅化物。
在形成第一外延层141和第二外延层143之后，第一层间电介质层150可以被形成以填充在虚设栅极图案DGP之间。第一层间电介质层150可以具有在与虚设栅极图案DGP的顶表面的水平基本相同的水平处的顶表面。第一层间电介质层150可以包括硅氧化物层、硅氮化物层、硅氮氧化物层和低k电介质层中的一个或更多个。
参照图10A至10F，虚设栅极图案DGP可以被去除以形成由栅极间隔物130和栅极分隔图案125限定的栅极区域GR。虚设栅极图案DGP的去除可以通过执行干蚀刻工艺和/或湿蚀刻工艺来实现。
例如，虚设栅极图案DGP可以使用对虚设栅极图案DGP和栅极间隔物130表现出蚀刻选择性的蚀刻配方被湿蚀刻。当虚设栅极图案DGP由多晶硅层形成时，多晶硅可以使用其中硝酸、乙酸和氢氟酸彼此混合的蚀刻剂被湿蚀刻。
栅极区域GR可以暴露栅极间隔物130的侧壁和栅极分隔图案125的侧壁。有源图案101上的缓冲绝缘层102也可以随着虚设栅极图案DGP的去除而同时被部分地去除，结果有源图案101可以在其顶表面和侧壁上被暴露，并且器件隔离层103可以在其位于有源图案101之间的部分上被暴露。每个栅极区域GR可以具有在有源图案101上较小的垂直深度以及在器件隔离层103上较大的垂直深度。
在一些示例实施方式中，在用于形成栅极区域GR的蚀刻工艺中，第一虚设栅极层113或虚设间隔物图案122可以被不完全地蚀刻，以在栅极区域GR的下部拐角上局部地留下残余虚设栅极图案113R，如图10A和10F所示。因此，残余虚设栅极图案113R可以局部地留在栅极间隔物130与栅极分隔图案125之间以及在栅极间隔物130与有源图案101之间。
在一些示例实施方式中，当虚设间隔物图案122包括与虚设栅极图案DGP的材料相同的材料时，虚设间隔物图案122也可以在去除虚设栅极图案DGP时被去除。或者，当虚设间隔物图案122包括对虚设栅极图案DGP表现出蚀刻选择性的材料时，虚设间隔物图案122可以暴露于栅极区域GR。
参照图11A至11E，栅极结构GS可以在对应的栅极区域GR中形成。
每个栅极结构GS可以包括栅极电介质层151、栅极阻挡金属图案153、栅极金属图案155和盖绝缘图案157。其中栅极阻挡金属图案153和栅极金属图案155构成栅电极GE。
栅极电介质层151可以由高k电介质层形成，诸如铪氧化物、铪硅酸盐、锆氧化物或锆硅酸盐。可以采用原子层沉积技术来形成栅极电介质层151，栅极电介质层151共形地覆盖有源图案101的表面、栅极间隔物130的暴露于栅极区域GR的内侧壁、以及栅极分隔图案125的侧壁。或者，当有源图案101在暴露于栅极区域GR的表面上被热氧化时，可以形成栅极电介质层151。
栅极阻挡金属图案153可以在栅极电介质层151与栅极金属图案155之间，并且可以在栅极金属图案155与栅极间隔物130之间延伸。栅极阻挡金属图案153可以包括导电金属氮化物(例如钛氮化物、钽氮化物和/或钨氮化物)。栅极金属图案155可以包括金属性材料(例如钨、钛和/或钽)。盖绝缘图案157可以覆盖栅极金属图案155的顶表面。盖绝缘图案157还可以覆盖栅极分隔图案125的顶表面。盖绝缘图案157可以具有与第一层间电介质层150的顶表面基本上共面的顶表面。盖绝缘图案157可以包括例如硅氧化物、硅氮化物、硅氮氧化物、硅碳氮化物(SiCN)和硅碳氮氧化物(SiCON)中的至少一种。
栅极分隔图案125可以使栅极结构GS中的一些在第二方向D2上彼此分开。在一些示例实施方式中，因为当形成栅极区域GR时，虚设间隔物图案122随虚设栅极图案DGP一起被去除，所以栅极结构GS之间在第二方向D2上的距离可以小于虚设栅极图案DGP之间在第二方向D2上的距离。
在形成栅极结构GS之后，第二层间电介质层160可以形成在半导体衬底100的整个表面上。第二层间电介质层160可以覆盖第一层间电介质层150的顶表面和栅极结构GS的顶表面。
参照图12A至12F，第一有源接触图案170a可以被形成以与第一外延层141和第二外延层143中的对应的一个接触，并且第二有源接触图案170b可以被形成以连接第一外延层141和第二外延层143。
第一有源接触图案170a和第二有源接触图案170b可以穿透第一层间电介质层150和第二层间电介质层160。第一有源接触图案170a和第二有源接触图案170b的每个可以包括阻挡金属层171和金属层173，并且阻挡金属层171可以具有均匀的厚度并共形地覆盖第一外延层141和第二外延层143的顶表面。
第二有源接触图案170b可以沿第二方向D2从第一外延层141上延伸到第二外延层143上，并跨越栅极分隔图案125的下部125a。
第二有源接触图案170b可以具有底表面，并且栅极分隔图案125的下部125a的高度可以改变第一外延层141与第二外延层143之间的底表面的水平。在第一外延层141与第二外延层143之间，第二有源接触图案170b可以跨越栅极分隔图案125的下部125a。在另外的实施方式中，第二接触图案170b可以与栅极分隔图案125的下部125a的顶表面接触。
图13、14和15示出显示了根据发明构思的一些示例实施方式的制造半导体器件的方法的剖视图和俯视图。图16和17示出分别沿图15的线B-B'和D-D'截取的剖视图。
为了说明的简洁，可以省略对与上述半导体器件的技术特征相同的技术特征的详细描述，并且将描述其不同之处。
在图13所示的实施方式中，栅极分隔图案125可以不包括中间部分，并且包括沿第一方向D1延伸的下部125a和从下部125a突出的上部125b。每个上部125b可以具有与栅极结构GS的宽度基本相同的宽度。下部125a的顶表面可以位于比第二有源接触图案170b的底表面的水平高的水平处。
在图14所示的示例实施方式中，当执行蚀刻工艺以形成参照图8A至8E讨论的凹陷RS时，初始栅极分隔图案124的下部可以被蚀刻以暴露器件隔离层103。上述工艺可以形成在第一方向D1上彼此间隔开的栅极分隔图案125。
在如图15、16和17所示的示例实施方式中，如以上参照图4A至4E所述，虚设间隔物121可以由对第一虚设栅极层113表现出蚀刻选择性的材料形成。在这种情况下，如参照图10A至10E所述，当形成栅极区域GR时，虚设间隔物图案122可以保留而不被去除。例如，虚设间隔物图案122可以留在栅极分隔图案125与栅极结构GS之间。因此，栅极分隔图案125和虚设间隔物图案122可以在沿第二方向D2彼此相邻的栅极结构GS之间。
根据发明构思的一些示例实施方式，形成虚设栅极图案可以在形成使栅电极结构分开的栅极分隔图案之后。因此，可以增加用于形成栅极分隔图案的工艺余量。
形成栅极分隔图案可以在形成覆盖开口的侧壁的虚设间隔物之后，该顺序可以减小栅极分隔图案的宽度。在这种情况下，因为栅电极减小其间的间隔，所以半导体器件可以增加集成度。
采用低k电介质材料来形成覆盖栅电极结构的侧壁并跨越栅极分隔图案的栅极间隔物，结果，电容耦合可以在彼此相邻的栅电极结构之间被减小。
虽然已经结合附图中示出的发明构思的示例实施方式描述了发明构思，但是本领域技术人员将理解，可以进行各种改变和修改而不背离发明构思的技术精神和本质特征。对本领域技术人员将明显的是，可以对其进行各种替换、修改和改变而不背离发明构思的范围和精神。
本申请要求享有2017年12月29日在韩国知识产权局提交的韩国专利申请第10-2017-0183370号的优先权，其全部内容通过引用在此合并。

Claims (20)

1.一种半导体器件，包括：
半导体衬底，包括沿第一方向延伸的有源图案；
多个栅电极，交叉所述有源图案并且沿第二方向延伸，所述多个栅电极在所述第一方向上彼此间隔开；
栅极分隔图案，具有在所述第一方向上的长轴并且在所述多个栅电极中的两个栅电极之间，所述多个栅电极中的所述两个栅电极在所述第二方向上彼此相邻；以及
多个栅极间隔物，覆盖所述多个栅电极中的相应栅电极的侧壁，所述栅极间隔物交叉所述栅极分隔图案并且沿所述第二方向延伸，
其中所述栅极分隔图案包括：
下部，沿所述第一方向延伸；
中间部分，从所述下部突出并且具有第一宽度，以及
上部，在两个相邻的栅极间隔物之间并且从所述中间部分突出，所述上部具有小于所述第一宽度的第二宽度。
2.根据权利要求1所述的器件，其中所述多个栅电极的每个具有与所述第二宽度基本相同的宽度。
3.根据权利要求1所述的器件，其中所述多个栅极间隔物的每个包括低k电介质材料，所述低k电介质材料具有比所述栅极分隔图案的介电常数小的介电常数。
4.根据权利要求1所述的器件，其中所述多个栅极间隔物包括：
第一间隔物部分，沿所述第二方向延伸并且覆盖所述栅电极的所述侧壁和所述栅极分隔图案的所述上部的侧壁；以及
第二间隔物部分，沿所述第一方向延伸并且覆盖所述栅极分隔图案的所述下部的侧壁。
5.根据权利要求4所述的器件，其中所述第一间隔物部分的高度大于所述第二间隔物部分的高度。
6.根据权利要求1所述的器件，其中所述栅极分隔图案的所述上部的顶表面在与所述栅电极的顶表面的水平基本相同的水平处。
7.根据权利要求1所述的器件，其中所述栅极分隔图案的底表面在比所述栅电极的底表面的水平低的水平处。
8.根据权利要求1所述的器件，还包括：
多个残余虚设栅极图案，局部地位于所述栅电极的对应的下部拐角上，
其中所述残余虚设栅极图案包括与所述栅电极的材料不同的材料。
9.根据权利要求1所述的器件，其中所述多个栅电极的每个包括：
金属图案；以及
阻挡金属图案，在所述金属图案与所述有源图案之间并且在所述金属图案与所述栅极间隔物之间延伸。
10.根据权利要求1所述的器件，还包括：
多个外延层，在所述多个栅电极的相邻栅电极之间的所述有源图案上，
其中所述栅极分隔图案的一部分在所述外延层之间，所述多个外延层在所述第二方向上彼此间隔开。
11.根据权利要求10所述的器件，还包括：
连接所述多个外延层的接触图案，
其中所述接触图案的一部分跨越所述栅极分隔图案的所述下部。
12.一种半导体器件，包括：
半导体衬底，包括沿第一方向延伸的有源图案；
多个栅电极，交叉所述有源图案并且沿第二方向延伸，所述多个栅电极在所述第一方向上彼此间隔开；
栅极分隔图案，在所述多个栅电极中的至少两个栅电极之间，所述至少两个栅电极在所述第二方向上彼此相邻，所述栅极分隔图案具有在所述第一方向上的长轴；以及
多个栅极间隔物，覆盖所述多个栅电极中的相应栅电极的侧壁，所述栅极间隔物交叉所述栅极分隔图案并且沿所述第二方向延伸，
其中所述栅极分隔图案包括：
上部，在所述多个栅极间隔物中的两个相邻的栅极间隔物之间，以及
下部，在所述栅极间隔物之下沿所述第一方向延伸，
其中所述多个栅极间隔物的每个包括低k电介质材料，所述低k电介质材料具有比所述栅极分隔图案的介电常数小的介电常数。
13.根据权利要求12所述的器件，其中所述多个栅极间隔物包括：
第一间隔物部分，沿所述第二方向延伸并且覆盖所述多个栅电极中的一个栅电极的侧壁以及所述栅极分隔图案的所述上部的侧壁；以及
第二间隔物部分，沿所述第一方向延伸并且覆盖所述栅极分隔图案的所述下部的侧壁。
14.根据权利要求13所述的器件，其中所述第一间隔物部分的高度大于所述第二间隔物部分的高度。
15.根据权利要求12所述的器件，其中所述多个栅电极的每个具有与所述栅极分隔图案的所述上部的宽度基本相同的宽度。
16.根据权利要求12所述的器件，其中所述栅电极的顶表面在与所述栅极分隔图案的所述上部的顶表面的水平基本相同的水平处。
17.一种半导体器件，包括：
半导体衬底，包括第一有源图案和第二有源图案，所述第一有源图案和所述第二有源图案沿第一方向延伸；
多个第一栅电极，交叉所述第一有源图案并且沿第二方向延伸；
多个第二栅电极，交叉所述第二有源图案并且沿所述第二方向延伸，所述第二栅电极在所述第二方向上与所述第一栅电极间隔开；
栅极分隔图案，在所述多个第一栅电极中的一个与所述多个第二栅电极中的一个之间，所述多个第一栅电极中的所述一个和所述多个第二栅电极中的所述一个在所述第二方向上彼此相邻；
多个栅极间隔物，沿所述第二方向从所述多个第一栅电极和所述多个第二栅电极中的对应栅电极的侧壁延伸；
多个第一外延层，在所述第一有源图案上并且在所述第一栅电极之间；以及
多个第二外延层，在所述第二有源图案上并且在所述第二栅电极之间，
其中所述栅极分隔图案包括：
多个第一部分，每个第一部分在所述多个第一栅电极中的所述一个与所述多个第二栅电极中的所述一个之间具有第一高度，以及
多个第二部分，在所述第一方向上连接到所述多个第一部分，并且
在所述第二方向上位于所述多个第一外延层中的一个与所述多个第二外延层中的一个之间，
其中所述多个第二部分的每个具有小于所述第一高度的第二高度。
18.根据权利要求17所述的器件，还包括：
接触图案，连接所述第一外延层和所述第二外延层，
其中所述接触图案跨越所述栅极分隔图案的所述多个第二部分中的一个。
19.根据权利要求17所述的器件，其中所述多个栅极间隔物的每个包括低k电介质材料，所述低k电介质材料具有比所述栅极分隔图案的介电常数小的介电常数。
20.根据权利要求17所述的器件，其中所述栅极分隔图案的所述多个第一部分的每个包括：
上部，具有与所述第一栅电极和所述第二栅电极的宽度相同的宽度；以及
中间部分，具有比所述上部的宽度大的宽度。
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