CN109987576B - 一种用于形成集成电路器件的方法 - Google Patents

一种用于形成集成电路器件的方法 Download PDF

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CN109987576B
CN109987576B CN201910164541.0A CN201910164541A CN109987576B CN 109987576 B CN109987576 B CN 109987576B CN 201910164541 A CN201910164541 A CN 201910164541A CN 109987576 B CN109987576 B CN 109987576B
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layer
forming
cavity
dielectric layer
sacrificial
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CN109987576A (zh
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郑钧文
朱家骅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开的集成电路器件包括设置在半导体衬底上方的介电层，介电层具有形成在其中的牺牲腔体，形成到介电层上的膜层，以及在膜层上形成的覆盖层从而形成第二腔体，第二腔体通过形成在膜层内的通孔连接至牺牲腔体。本发明还公开了具有覆盖结构的MEMS器件结构。

Description

一种用于形成集成电路器件的方法
本申请是2013年12月9日提交的优先权日为2013年3月11日的申请号为201310661669.0的名称为“具有覆盖结构的MEMS器件结构”的发明专利申请的分案申请。
相关申请的交叉引用
本申请要求于2013年3月11日提交的名称为“MEMS Device Structure with aCapping Structure”的美国临时专利申请第61/775,931号的利益，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体技术领域，更具体地，涉及具有覆盖结构的MEMS 器件结构。
背景技术
微机电系统(MEMS)器件可以包括在微米级尺寸范围内的部件以及有时在纳米级尺寸范围内的部件。典型的MEMS器件可以包括处理电路、模拟电路或逻辑电路，以及用于各种类型传感器的机械部件。这些传感器可以用作射频(RF)开关、陀螺仪、加速计或运动传感器的一部分。
通常在腔室中提供MEMS器件的机械部件，在腔室中允许部件移动。通常，具有通过一个或多个通孔连接的两个腔室。形成这类腔室的一种方法为使用牺牲材料。具体地，在特定层内形成腔体。随后使用牺牲材料填充腔体。然后，可以在牺牲材料顶部上沉积随后的层。之后，形成穿过随后的层的通孔以露出牺牲材料。其后，可以通过各种化学工艺释放牺牲材料。虽然这是形成腔室的有效方法，当制造MEMS器件时，期望最小化牺牲层的数量。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种用于形成集成电路器件的方法，所述方法包括：
在衬底上方形成介电层，所述衬底包括与微机电系统(MEMS)器件相互作用的电路；
在所述介电层内形成的牺牲腔体内形成牺牲材料；
在所述介电层和牺牲材料上方形成膜层；
通过穿过所述膜层形成的至少一个通孔去除所述牺牲材料；以及
在所述膜层上形成介电覆盖结构从而形成第二腔体，所述第二腔体通过在所述膜层内形成的所述至少一个通孔连接至所述牺牲腔体。
在可选实施例中，形成所述介电覆盖结构包括将位于覆盖衬底的表面上的覆盖介电层接合至所述膜层。
在可选实施例中，所述覆盖衬底上的所述覆盖介电层熔融接合至所述膜层。
在可选实施例中，所述方法还包括：在所述接合之后，去除所述覆盖衬底的材料。
在可选实施例中，通过湿蚀刻工艺和研磨工艺中的一种去除所述覆盖衬底。
在可选实施例中，所述方法还包括：在去除所述覆盖衬底的材料之后，在保留的覆盖结构的顶部上沉积固定层。
在可选实施例中，所述方法还包括：在所述牺牲腔体的底部形成底部电极层，且在所述牺牲腔体的顶部形成顶部电极层。
在可选实施例中，所述顶部电极层的导电元件在所述牺牲腔体上方延伸。
在可选实施例中，所述方法还包括：将微机电系统(MEMS)器件放置到所述牺牲腔体和所述第二腔体内。
在可选实施例中，所述MEMS器件包括射频(RF)开关器件。
根据本发明的另一方面，还提供了一种形成集成电路器件的方法，所述方法包括：
形成包括与微机电系统(MEMS)器件相互作用的电路的半导体衬底；
在所述半导体衬底上形成底部电极层；
在所述底部电极层上形成介电层；
在所述介电层内形成的牺牲腔体内形成牺牲材料；
在所述介电层上形成顶部电极层；
在所述顶部电极层上方形成膜层；
通过穿过所述膜层形成的至少一个通孔去除所述牺牲材料；以及
在所述膜层上形成介电覆盖结构从而形成第二腔体，所述第二腔体通过在所述膜层内形成的所述至少一个通孔连接至所述牺牲腔体。
在可选实施例中，形成所述介电覆盖结构包括：在临时覆盖衬底上形成覆盖介电层；以及，将所述覆盖介电层接合至所述膜层。
在可选实施例中，所述方法还包括：在所述接合之后，去除覆盖衬底的材料。
在可选实施例中，通过湿蚀刻工艺和研磨工艺中的一种去除所述覆盖衬底。
在可选实施例中，所述方法还包括：在去除所述覆盖衬底的材料之后，在保留的覆盖结构的顶部上沉积固定层。
在可选实施例中，所述方法还包括：在形成所述膜层之前，形成将所述顶部电极层和所述底部电极层连接的通孔。
在可选实施例中，所述方法还包括：在所述牺牲腔体的底部形成底部电极层，且在所述牺牲腔体的顶部形成顶部电极层。
在可选实施例中，，所述顶部电极层的导电元件在所述牺牲腔体上方延伸。
在可选实施例中，所述方法还包括：将微机电系统(MEMS)器件放置在所述牺牲腔体和所述第二腔体内。
根据本发明的又一方面，还提供了一种集成电路器件，包括：
介电层，设置在互补金属氧化物半导体(CMOS)衬底上方，所述CMOS 衬底具有与MEMS器件相互作用的电路，所述介电层具有形成在其中的牺牲腔体；
顶部电极层，位于所述牺牲腔体的顶部；
底部电极层，位于所述牺牲腔体的底部；
膜层，形成在所述介电层上方，所述膜层具有位于所述牺牲腔体上方的通孔；以及
覆盖结构，包括设置在所述膜层上方的介电材料，其中，第二腔体设置在所述覆盖结构和所述膜层之间，所述第二腔体通过所述膜层内的所述通孔连接至所述牺牲腔体。
附图说明
根据下文的具体描述结合参考附图可以更好地理解本发明的方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制。事实上，为了清楚的讨论，各个部件的尺寸可以被任意地增大或减小。
图1A至图1H示出了根据本文描述的原理的一个实例的用于形成具有覆盖结构的MEMS器件结构的示例性工艺的图；
图2A至图2C示出了根据本文描述的原理的一个实例的用于形成可被用来形成覆盖结构的覆盖衬底的示例性工艺的图；
图3示出了根据本文描述的原理的一个实例的包括覆盖结构的示例性 MEMS器件结构的图；
图4示出了根据本文描述的原理的一个实例的用于形成具有覆盖结构的MEMS器件的示例性方法的流程图。
具体实施方式
应该理解，以下公开内容提供了许多用于实施所公开的不同特征的不同实施例或实例。以下描述部件和配置的具体实例以简化本发明。当然，这仅仅是实例，并不是用于限制本发明。而且，在以下描述中，在第二工艺之前实施第一工艺可以包括在第一工艺之后直接实施第二工艺的实施例，且也可以包括在第一工艺和第二工艺之间可以实施额外的工艺的实施例。为了简化和清楚的目的，可以以不同比例任意绘制各个部件。此外，在以下描述中，第一部件形成在第二部件上方或者之上可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且还可以包括在第一部件和第二部件之间形成另外部件，使得第一部件和第二部件不直接接触的实施例。
此外，本文可以使用诸如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等空间相对位置术语以便于描述如图中所示的一个元件或部件与另一个(或另一些)元件或部件的关系。应该理解，除了图中描述的方位外，这些空间相对位置术语旨在包括器件在使用或操作中的不同方位。例如，如果翻转附图中的器件，描述为在其他元件或部件“下方”或“之下”的元件将定向为在其他元件或部件“上方”。因此，示例性术语“在…下方”可以包括在“在…上方”和在“在…下方”两种方位。所述装置可以以其他方式进行定向(旋转90度或在其他方位上)，并相应地解释本文中使用的空间相对描述符。
图1A至图1H示出了用于形成包括覆盖结构的MEMS器件结构的示例性工艺的图。根据本实例，MEMS器件结构建立在互补金属氧化物半导体(CMOS)衬底104上。在本实例中，CMOS衬底104形成在高电阻衬底102上。高电阻衬底的电阻可以至少为1000ohm-cm。
由诸如硅的半导体材料制成CMOS衬底104。CMOS衬底可以包括用于操作MEMS器件结构内形成的MEMS器件或者与MEMS器件相互作用的电路。可以在金属、半导体和介电材料的多层中形成这种电路(未示出)。
根据本实例，金属层106形成在CMOS衬底104的顶部上。金属层用作在下文中进一步描述的将要形成的牺牲腔体的底部电极层。金属层106 可以是CMOS衬底的部分。金属层106的各种金属接触件可以通过多个通孔连接至下方的CMOS衬底金属层的金属接触件。可以通过沉积金属层、图案化该层以及然后去除将不存在金属的金属区域来形成金属层106。
图1B示出了在金属层106的顶部上形成层间介电层108。层间介电层 108存在于两个电极层之间。可以由氧化物材料制成层间介电层108。可以使用化学机械抛光(CMP)工艺以使层间介电层108平滑。然后，可以使用掩模以图案化层间介电层108内的腔体区域110。可以使用蚀刻工艺以从介电层处去除材料，从而露出下面的底部电极金属层106并形成腔体 110。
图1C示出了额外的介电层的沉积。例如，可以在层间介电层108的顶部上形成氧化物层114。在一些情形下，可以图案化这种氧化物层114使得氧化物凸块(未示出)保留在金属层108的一些金属接触件的顶部上。此外，薄介电材料116可以沉积在氧化物层114的顶部上。
根据本实例，使用诸如非晶硅(a-Si)、硅的非晶同素异形体形式的牺牲材料118填充牺牲腔体110。选择牺牲材料118以便通过干蚀刻工艺可以将其去除，其将在下文中进一步描述。在沉积牺牲材料118之后，可以使用CMP工艺以使表面平滑。
图1D示出了在介电层116和牺牲材料118的顶部上沉积额外的薄介电膜120。可以由相同的材料制成第一薄介电层116和第二介电层120。介电层将下面的层与其后形成的任意的额外层隔离开。
根据本实例，在沉积的层内形成通孔124。具体地，通孔124可以形成为穿过薄介电层116、120、氧化物层114和层间介电层108，并且停止在电极金属层106的顶部处。可以在薄介电层120顶部上形成顶部电极金属层122。当沉积金属材料时，填充通孔124使得顶部电极金属层122与底部电极金属层106电连接。尽管示出了一个通孔124，但是它可以是使用多个通孔将顶部电极金属层122的金属部件与底部电极金属层106的金属部件连接的实例。
可以使用与形成底部电极金属层108相似的方式形成顶部电极金属层 122。具体地，将金属或导电材料沉积在之前形成的层上。然后可以使用掩模图案化金属层122。之后使用蚀刻工艺从预期不使用金属的区域中去除金属。在一些实施例中，特定的金属接触件可以延伸在牺牲材料118上方。这允许金属部件形成在牺牲腔体和第二腔体之间，在下文中将进一步描述第二腔体。
图1E示出了膜层126的形成。膜层是额外的介电层。称之为膜层是为了将其与第一层间介电层108区分开。此外，膜层可以用作为RF开关膜。膜层126提供机械强度和刚性以作为MEMS器件的可移动结构的柔性悬浮膜或梁(beam)。在一些实施例中，膜层126的厚度介于约0.5微米和5 微米的范围内。
膜层126可以包括多个通孔127。通孔127可以通过标准光刻技术形成，例如使用光掩模以将光刻胶层曝光于光源下。然后显影光刻胶层并且将光刻胶材料的保留区域用于限定通孔127。之后可以使用蚀刻工艺以形成向下穿过膜层126到达下面的顶部电极金属层122的通孔。
根据本实例，在膜层126上形成第三金属层128。第三金属层可以与形成有通孔127的顶部电极金属层122相连接。也可以通过沉积金属材料，图案化金属层，并且然后蚀刻掉预期未形成金属的区域，从而形成第三金属层128。
然后在第三金属层128上沉积顶部介电层130。顶部介电层可以用于应力平衡。可以由氧化物材料制成顶部介电层130。在一些实施例中，可以去除顶部介电层的部分以露出下面的金属部件。这可以用于诸如RF开关结构的多种MEMS器件。
在形成顶部介电层130之后，形成向下通至牺牲材料118的多个通孔 132。具体地，形成穿过介电层130、膜层126和薄介电层120的通孔132。可以设置通孔132使得其不穿过第三金属层128或顶部电极金属层122的任何金属部件。
图1F示出了去除牺牲材料118以形成完整的牺牲腔体134。在一个实施例中，可以通过使用二氟化氙(XeF2)蚀刻掉牺牲材料。XeF2可用于通过通孔132蚀刻掉非晶硅牺牲材料118。也可以使用其他方法去除牺牲材料。可以使用各种干蚀刻工艺。干蚀刻包括离子轰击以去除特殊类型的材料。
可以选择牺牲材料118以及薄介电层116、120的材料使得特定的蚀刻剂将仅去除牺牲材料118而不去除介电材料。因此，在去除牺牲材料118 的蚀刻工艺完成之后，牺牲腔体134将在每个壁上具有介电层材料。介电材料本质上用作去除牺牲材料118的蚀刻工艺的停止。
图1G示出了覆盖衬底136的附接。根据本实例，覆盖衬底136用于生成第二腔体。覆盖衬底包括将成为覆盖结构的介电层140。本文中将结合图2描述单独形成的覆盖衬底136。覆盖衬底136包括腔体，使得当其接合至顶部介电层130时，形成封闭的腔体142。
将覆盖衬底136接合至顶部介电层130以便形成熔融接合138。熔融接合138涉及热退火工艺，热退火工艺熔融与顶部介电层130接触的覆盖衬底136。接合138使得其密封第二腔体142。第二腔体142通过通孔132 保持与牺牲腔体134的连接。使用本文中描述的工艺，可以在两个腔体142、 134内形成各种MEMS器件。未示出这种器件的形成。相反，附图示出了形成支持MEMS器件的衬底和电路的工艺。
图1H示出了覆盖衬底136的去除。虽然去除了覆盖衬底136本身，然而保留了形成在覆盖衬底136上的介电层140，从而形成覆盖结构144。可以通过各种工艺去除覆盖衬底136。在一个实例中，通过研磨工艺去除覆盖衬底136。在一个实例中，使用蚀刻工艺去除覆盖衬底136。蚀刻工艺可以对覆盖衬底136的材料具有选择性以完整地保留介电材料140，从而形成覆盖结构144。
图2A至图2B示出了用于形成覆盖衬底(用于形成覆盖结构)的示例性工艺200的示图。图2A单独示出了覆盖衬底202。可以由诸如硅的半导体材料制成覆盖衬底。
图2B示出了在衬底202内形成腔体204。可以使用标准光刻技术形成腔体。具体地，光刻胶层可以沉积在衬底202上，然后通过光掩模将光刻胶层曝光于光源下。之后显影将要形成的腔体204的区域，从而将衬底暴露于形成腔体204的蚀刻工艺。
图2C示出了在衬底上形成介电层206。为区分该介电层206，可以将其称为覆盖介电层206。覆盖介电层206与腔体204的形状一致。因此，将介电材料沉积在腔体204的侧壁上以及腔体和衬底202的底部。在一个实例中，使用热氧化工艺形成覆盖介电层206。
图3示出了包括覆盖结构310的示例性MEMS器件结构300的示图。图3中示出的结构300与通过图1A至图1H中示出的工艺形成的结构相似。然而，图3中的结构仅示出了形成的一些关键层，且不必示出可形成在 MEMS器件结构内体现本发明所描述的原理的所有层。
根据一些示例性实例，MEMS器件结构300包括位于CMOS衬底303 的顶部上的介电层304。在一些实例中，CMOS衬底可以沉积在标准衬底 302上。介电层304具有形成在其中的牺牲腔体306。
在介电层304的顶部上形成膜层308。覆盖结构310接合至膜层308 的顶部。覆盖结构310接合至膜层308以便形成第二腔体314。牺牲腔体 306通过多个通孔312连接至第二腔体314。
图4示出了用于形成具有覆盖衬底的MEMS器件的示例性方法的流程图。根据一些示例性实例，所述方法包括步骤402，形成介电层到CMOS 衬底上。所述方法还包括步骤404，在形成介电层内的牺牲腔体内形成牺牲材料。所述方法还包括步骤406，在介电层和牺牲材料上方形成膜层。所述方法还包括步骤408，通过穿过膜层形成的至少一个通孔去除牺牲材料。所述方法还包括步骤410，在膜层上形成覆盖结构从而形成第二腔体，第二腔体通过形成在膜层内的至少一个通孔连接至牺牲腔体。
根据一些示例性实例，一种用于形成集成电路器件的方法包括在衬底上方形成介电层，衬底包括与微机电系统(MEMS)器件相互作用的电路，在形成在介电层内的牺牲腔体内形成牺牲材料，在介电层和牺牲材料上方形成膜层，通过穿过膜层形成的至少一个通孔去除牺牲材料，以及在膜层上形成介电覆盖结构从而形成第二腔体，第二腔体通过形成在膜层内的至少一个通孔连接至牺牲腔体。
根据一些示例性实例，一种用于形成集成电路器件的方法包括形成包括与微机电系统(MEMS)器件相互作用的电路的半导体衬底，形成底部电极层到半导体衬底上，形成介电层到底部电极层上，在形成在介电层内的牺牲腔体内形成牺牲材料，在介电层上形成顶部电极层，在顶部电极层上方形成膜层，通过穿过膜层形成的至少一个通孔去除牺牲材料，以及在膜层上形成介电覆盖结构从而形成第二腔体，第二腔体通过形成在膜内的至少一个通孔连接至牺牲腔体。
根据一些示例性实例，一种集成电路器件包括设置在互补金属氧化物半导体(CMOS)衬底上方的介电层，CMOS衬底具有与MEMS器件相互作用的电路，介电层具有形成在其中的牺牲腔体。所述器件还包括位于牺牲腔体的顶部上的顶部电极层，位于牺牲腔体的底部的底部电极层，形成在介电层上方的膜层，膜层具有位于牺牲腔体上方的通孔，以及覆盖结构包括设置在膜层上方的介电材料。第二腔体设置在覆盖结构和膜层之间，第二腔体通过在膜层中的通孔连接至牺牲腔体。
应该理解，上文中列出的实施例和步骤的各种不同的组合可以以不同的顺序或同时使用，且没有特定的步骤是决定性的或必须的。此外，尽管本文中使用了术语“电极”，但应该认为术语可以包括“电极接触件”的概念。另外，以上结合一些实施例描述和论述的部件可以与以上结合其他实施例描述和论述的部件相结合。因此，所有这种修改预期包括在本发明的范围内。
上面论述了多个实施例的部件。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或修改其他用于执行与本文所介绍的实施例相同的目的和/或实现相同的优势的其他工艺和结构。本领域普通技术人员还应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以作出多种变化、替换以及改变。

Claims (17)

1.一种用于形成集成电路器件的方法，所述方法包括：
在衬底上方形成第一介电层，所述衬底包括与微机电系统(MEMS)器件相互作用的电路；
在所述第一介电层内形成的牺牲腔体内形成牺牲材料；
在所述第一介电层和牺牲材料上方形成膜层；
在所述膜层内形成第一通孔；
在所述膜层上形成第二介电层，其中，所述第二介电层覆盖所述膜层且填充在所述第一通孔内；
通过穿过所述第二介电层、所述膜层形成的至少一个第二通孔去除所述牺牲材料；以及
在去除所述牺牲材料之后，在所述第二介电层上形成介电覆盖结构从而形成第二腔体，所述第二腔体通过在所述膜层内形成的所述至少一个第二通孔连接至所述牺牲腔体；
其中，形成所述介电覆盖结构包括将位于覆盖衬底的表面上的覆盖介电层接合至所述第二介电层；
在所述接合之后，去除所述覆盖衬底的材料，
其中，所述牺牲腔体内的牺牲材料在被去除时没有经过所述第二腔体。
2.根据权利要求1所述的方法，其中，在所述牺牲腔体内形成所述牺牲材料之前，在所述第一介电层上方形成氧化物层，其中，所述氧化物层位于所述第一介电层和所述牺牲材料之间，并且所述第一介电层和所述氧化物层均与所述牺牲材料横向偏移。
3.根据权利要求1所述的方法，其中，所述覆盖衬底上的所述覆盖介电层熔融接合至所述第二介电层。
4.根据权利要求1所述的方法，其中，通过湿蚀刻工艺和研磨工艺中的一种去除所述覆盖衬底。
5.根据权利要求4所述的方法，还包括：在去除所述覆盖衬底的材料之后，在保留的覆盖结构的顶部上沉积固定层。
6.根据权利要求1所述的方法，还包括：在所述牺牲腔体的底部形成底部电极层，且在所述牺牲腔体的顶部形成顶部电极层。
7.根据权利要求6所述的方法，其中，所述顶部电极层的导电元件在所述牺牲腔体上方延伸。
8.根据权利要求1所述的方法，还包括：将微机电系统(MEMS)器件放置到所述牺牲腔体和所述第二腔体内。
9.根据权利要求8所述的方法，其中，所述微机电系统器件包括射频(RF)开关器件。
10.一种形成集成电路器件的方法，所述方法包括：
形成包括与微机电系统(MEMS)器件相互作用的电路的半导体衬底；
在所述半导体衬底上形成底部电极层；
在所述底部电极层上形成第一介电层；
在所述第一介电层内形成的牺牲腔体内形成牺牲材料；
在所述第一介电层上形成顶部电极层；
在所述顶部电极层上方形成膜层；
在所述膜层内形成第一通孔；
在所述膜层上形成第二介电层，其中，所述第二介电层覆盖所述膜层且填充在所述第一通孔内；
通过穿过所述第二介电层、所述膜层形成的至少一个第二通孔去除所述牺牲材料；以及
在去除所述牺牲材料之后，在所述膜层上形成介电覆盖结构从而形成第二腔体，所述第二腔体通过在所述膜层内形成的所述至少一个第二通孔连接至所述牺牲腔体；
其中，形成所述介电覆盖结构包括：在临时覆盖衬底上形成覆盖介电层；
将所述覆盖介电层接合至所述第二介电层；
在所述接合之后，去除所述临时覆盖衬底，
其中，所述牺牲腔体内的牺牲材料在被去除时没有经过所述第二腔体。
11.根据权利要求10所述的方法，其中，在所述牺牲腔体内形成所述牺牲材料之前，在所述第一介电层上方形成氧化物层，其中，所述氧化物层位于所述第一介电层和所述牺牲材料之间，并且所述第一介电层和所述氧化物层均与所述牺牲材料横向偏移。
12.根据权利要求10所述的方法，其中，通过湿蚀刻工艺和研磨工艺中的一种去除所述临时覆盖衬底。
13.根据权利要求10所述的方法，还包括：在去除所述临时覆盖衬底之后，在保留的覆盖结构的顶部上沉积固定层。
14.根据权利要求10所述的方法，还包括：在形成所述膜层之前，形成将所述顶部电极层和所述底部电极层连接的通孔。
15.根据权利要求10所述的方法，还包括：在所述牺牲腔体的底部形成底部电极层，且在所述牺牲腔体的顶部形成顶部电极层。
16.根据权利要求15所述的方法，其中，所述顶部电极层的导电元件在所述牺牲腔体上方延伸。
17.根据权利要求10所述的方法，还包括：将微机电系统(MEMS)器件放置在所述牺牲腔体和所述第二腔体内。
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