CN109935574A - 半导体模块和用于生产半导体模块的方法 - Google Patents
半导体模块和用于生产半导体模块的方法 Download PDFInfo
- Publication number
- CN109935574A CN109935574A CN201811535412.XA CN201811535412A CN109935574A CN 109935574 A CN109935574 A CN 109935574A CN 201811535412 A CN201811535412 A CN 201811535412A CN 109935574 A CN109935574 A CN 109935574A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- lead frame
- frame
- casting compound
- modular device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
本公开涉及半导体模块和用于生产半导体模块的方法。功率半导体模块装置包括两个或更多个独立半导体设备(21),每个半导体设备(21)包括引线框架(41)、被设置在引线框架(41)上的半导体主体(20)、以及围绕引线框架(41)的至少一部分和半导体主体(20)的成型材料(81)。功率半导体模块装置进一步包括:框架(52),框架(52)包围两个或更多个半导体设备(21);以及铸造化合物(8),铸造化合物(8)至少部分地填充框架(52)内的容积,从而至少部分地围绕两个或更多个独立半导体设备(21)。
Description
技术领域
本公开涉及一种半导体模块和用于生产半导体模块的方法。
背景技术
功率半导体模块装置通常包括被设置在外壳中的至少一个半导体衬底。包括多个可控半导体元件(例如,在半桥配置中的两个IGBT)的半导体装置被设置在至少一个衬底中的每个衬底上。每个衬底通常包括衬底层(例如,陶瓷层)、被沉积在衬底层的第一侧上的第一金属化层以及被沉积在衬底层的第二侧上的第二金属化层。例如,可控半导体元件被安装在第一金属化层上。可选地,第二金属化层可以被附接至基板。可控半导体设备通常通过焊接或烧结技术被安装至半导体衬底。然而,这种装置通常相当昂贵,而功率半导体装置的成本对于许多应用来说是至关重要的。进一步地,功率半导体模块装置可能会受到潮气的损坏,潮气可能会进入功率半导体模块装置的外壳并且损坏外壳内的半导体元件或任何其它部件。
需要一种功率半导体模块,该功率半导体模块可以以降低的成本被生产,并且同时提供提高的防潮性。
发明内容
一种功率半导体模块装置包括两个或更多个独立半导体设备,每个半导体设备包括引线框架、被设置在引线框架上的半导体主体、以及围绕引线框架的至少一部分和半导体主体的成型材料。功率半导体模块装置进一步包括:框架,该框架包围两个或更多个半导体设备;以及铸造化合物,该铸造化合物至少部分地填充框架内的容积,从而至少部分地围绕两个或更多个独立半导体设备。
一种用于生产功率半导体模块装置的方法包括:在基层上设置两个或更多个独立半导体设备,每个半导体设备包括引线框架、被设置在引线框架上的半导体主体、以及围绕引线框架的至少一部分和半导体主体的成型材料。该方法进一步包括:在基层上设置框架,使得框架包围两个或更多个半导体设备;将第一材料填充到由基层和框架形成的容积中;以及使第一材料硬化,从而形成铸造化合物,铸造化合物至少部分地填充容积,从而至少部分地围绕两个或更多个独立半导体设备。
参照以下附图和说明书可以更好地理解本发明。附图中的部件不一定按比例,而是将重点放在说明本发明的原理上。而且,在附图中,相同的附图标记在不同视图中表示对应的部分。
附图说明
图1是传统的功率半导体模块装置的横截面视图。
图2是另一传统的功率半导体模块装置的横截面视图。
图3是另一传统的功率半导体模块装置的横截面视图。
图4是功率半导体模块装置的横截面视图。
图5示意性地图示了用于生产功率半导体模块装置的方法的一个步骤。
图6示意性地图示了用于生产功率半导体模块装置的方法的一个步骤。
图7示意性地图示了用于生产功率半导体模块装置的方法的一个步骤。
图8(包括图8A和图8B)示意性地图示了用于生产功率半导体模块装置的方法的步骤。
图9(包括图9A至图9C)示意性地图示了用于生产功率半导体模块装置的方法的步骤。
图10示意性地图示了用于生产功率半导体模块装置的方法的一个步骤。
图11示意性地图示了用于生产功率半导体模块装置的方法的一个步骤。
图12示意性地图示了用于生产功率半导体模块装置的方法的一个步骤。
图13示意性地图示了用于生产功率半导体模块装置的方法的一个步骤。
图14示意性地图示了用于生产功率半导体模块装置的方法的一个步骤。
图15示意性地图示了如图9A所图示的截面平面A-A中的功率半导体模块装置的横截面视图。
图16示意性地图示了如图9A所图示的截面平面A-A中的另一功率半导体模块装置的横截面视图。
图17示意性地图示了用于形成半导体设备的成型材料的铸造模具。
具体实施方式
在以下详细描述中,参照附图。附图示出了本发明可以被实践的具体示例。要理解的是,除非另外特别注明,否则关于各种示例描述的特征和原理可以彼此组合。在说明书以及权利要求书中,将某些元件表示为“第一元件”、“第二元件”、“第三元件”等不应被理解为列举。相反,这种表示仅用于处理不同的“元件”。即,例如,存在“第三元件”不需要存在“第一元件”和“第二元件”。本文描述的电线路或电连接可以是单个导电元件,或者包括串联和/或并联连接的至少两个独立导电元件。电线路和电连接可以包括金属和/或半导体材料,并且可以是永久导电的(即,不可切换的)。本文描述的半导体主体可以由(掺杂的)半导体材料制成,并且可以是半导体芯片或者被包括在半导体芯片中。半导体主体具有电连接焊盘,并且包括具有电极的至少一个半导体元件。
参照图1,图示了功率半导体模块装置的横截面视图。该功率半导体模块装置包括半导体衬底10。半导体衬底10包括介电绝缘层11、被附接至介电绝缘层11的第一(结构化的)金属化层111以及被附接至介电绝缘层11的第二(结构化的)金属化层112。介电绝缘层11被设置在第一金属化层111与第二金属化层112之间。
半导体衬底10被设置在外壳5中。在图1所图示的装置中,半导体衬底10形成外壳5的地表面,而外壳5本身仅包括侧壁。然而,这仅是示例。也有可能的是,外壳5进一步包括地表面和/或盖子,并且半导体衬底10被设置在外壳5内。
一个或多个半导体主体20可以被设置在半导体衬底10上。一个或多个半导体主体20可以在半导体衬底10上形成半导体装置。在图1中,仅示例性地图示了两个半导体主体20。图1中的半导体衬底10的第二金属化层112是连续层。第一金属化层111是图1所图示的装置中的结构化层。“结构化层”意味着第一金属化层111不是连续层,而是在层的不同部分之间包括凹口。在图1中示意性地图示了这种凹口。该装置中的第一金属化层111包括三个不同部分。不同的半导体主体20可以被安装至第一金属化层111的相同或不同部分。第一金属化层的不同部分可以不具有电连接,或者可以使用电连接3(诸如,例如,结合接线)被电连接至一个或多个其它部分。例如,仅举数例,电连接3还可以包括连接板或者导体轨。一个或多个半导体主体20可以通过导电连接层30被电连接和机械连接至半导体衬底10。例如,这种导电连接层30可以是焊料层、导电粘合剂层、或者烧结金属粉末(例如,烧结银粉)层。
功率半导体模块装置进一步包括端子元件4。端子元件4被电连接至第一金属化层111,并且提供在外壳5的内部与外部之间的电连接。端子元件4可以利用第一端被电连接至第一金属化层111,而端子元件4的第二端从外壳5突出。可以在端子元件4的第二端处,从外部电接触端子元件4。
例如,端子元件4的第二端可以被机械连接和电连接至印刷电路板(PCB)7。印刷电路板7可以形成外壳的盖子,并且可以包括通孔。端子元件4可以被插入到印刷电路板7的通孔中。印刷电路板7可以包括导电轨道(未示出),并且端子元件4可以借助于PCB 7上的一个或多个这种导电轨道被电耦合至一个或多个其它端子元件4。通过这种方式,可以在第一金属化层111的不同部分之间、在不同的半导体主体20之间、和/或在被设置在衬底10上的任何其它部件之间,提供电连接。端子元件4可以被焊接至印刷电路板7,例如,以提供永久且坚固的连接。然而,这仅是示例。根据另一示例,引线框架41可以在其第二端处包括压配销,压配销被插入到印刷电路板7的对应的对应物中。任何其它合适的连接也是可能的。
外壳5可能至少部分地用密封树脂8填充。例如,密封树脂8可以包括(填充)环氧树脂、有机硅凝胶或其它树脂材料。密封树脂8被配置为密封功率半导体模块的部件,诸如,半导体衬底10(具体地,由第一金属化层111形成的金属图案)、半导体主体20、电连接3和端子元件4,以提供对设备的绝缘和保护。例如,密封树脂8可以保护部件免受某些环境条件的影响,并且保护部件免受机械损坏。密封树脂8可以至少部分地填充外壳5的内部,从而覆盖被设置在半导体衬底10上的部件和电连接。端子元件4可以部分地被嵌入在密封树脂8中。然而,至少端子元件4的第二端未被密封树脂8覆盖,并且从密封树脂8突出到外壳5的外部。
功率半导体模块可以进一步包括散热器6。半导体衬底10可以经由连接层(未示出)被连接至散热器。例如,这种连接层可以是焊料层、粘合剂层、或者烧结金属粉末(例如,烧结银粉)层。
图1示意性地图示了没有基板的功率半导体装置。然而,半导体衬底10也可以被安装在基板9上。基板9可以被设置在散热器6上,使得基板9被设置在散热器6与半导体衬底10之间。在一些功率半导体模块装置100中,多于一个的半导体衬底101、102被设置在单个基板9上。这在图2中示例性地图示了。例如,然后基板9(而不是半导体衬底10)可以形成外壳5的地表面。半导体主体20可以被设置在半导体衬底101、102中的一个或多个半导体衬底上。
然而,如上面已经参照图1和图2描述的这种功率半导体模块比较昂贵。降低功率半导体模块的成本的压力通常较大。因此,包括分立半导体设备21的其它功率半导体模块装置是已知的。这种分立半导体设备21各自包括用成型材料81独立成型的半导体主体20。如在图3中示意性地图示的,独立半导体设备21的半导体主体20被设置在电载体或引线框架41上。例如,引线框架41可以包括诸如铜的金属。引线框架41可以至少部分地被成型到成型材料81中,并且可以形成半导体设备21的底侧。在图3中,引线框架41被图示为L形连接元件。在L的第一腿部上,设置了半导体主体20。半导体主体20可以使用导电层被附接至引线框架41。例如,这种导电层可以是焊料层、导电粘合剂层或者烧结金属粉末(例如,烧结银粉)层。可替代地或者附加地,例如,半导体主体20可以使用电连接(诸如,结合接线3)被电连接至引线框架41。引线框架41的第二腿部可以被机械连接和电连接至印刷电路板7。如上面已经关于图1描述的,印刷电路板7可以提供在被连接至同一印刷电路板7的两个或更多个半导体设备21之间的电连接。每个半导体设备21被设置在独立散热器6上。
因此,与已经关于图1和图2描述的装置相比,包括多个分立半导体设备21的这种功率半导体模块装置的安装工作量较大。在图3的装置中,每个半导体设备21必须被独立装配,并且随后被连接至印刷电路板7和独立散热器6。通常,电隔离材料层(未示出)被设置在每个半导体设备21的引线框架41与相应的散热器6之间。通常,必须在散热器6被安装至引线框架41之前应用电隔离材料层。当被出售给最终顾客时,具有安装在其上的半导体主体20的引线框架41通常未配备有这种隔离层。这进一步地增加了最终顾客的安装工作量,因为他需要执行在半导体设备21与散热器6之间形成隔离层的额外步骤。此外,这种介电隔离层通常具有差的耐热性。更进一步地,比起图1和图2的装置,如图3所图示的装置只是稍微更有成本效益。这是因为,比起图1的半导体设备20的安装工艺,针对图3的装置的半导体设备21的安装工艺更加成本密集。然而,图3的装置的半导体设备的包装成本比图1的装置的半导体设备的安装成本便宜多倍。
现在参照图4,示例性地图示了功率半导体模块装置。该功率半导体模块装置包括两个或更多个分立半导体设备21。每个分立半导体设备21包括半导体主体20和引线框架41。半导体主体20中的每个半导体主体20可以包括二极管、IGBT(绝缘栅双极晶体管)、MOSFET(金属氧化物半导体场效应晶体管)、JFET(结型场效应晶体管)、HEMT(高电子迁移率晶体管)或者任何其它合适的可控半导体元件。如上面已经关于图3所解释的,例如,引线框架41可以具有L形。这意味着引线框架41可以包括第一腿部和第二腿部。第一腿部可以被设置为基本上垂直于第二腿部。然而,这仅是示例。引线框架41通常可以具有任何其它合适的形状。
一个半导体主体20被设置在引线框架41上,例如,在L形引线框架41的第一腿部上。半导体主体20可以使用导电层被附接至引线框架41。例如,这种导电层可以是焊料层、导电粘合剂层或者烧结金属粉末(例如,烧结银粉)层。然而,半导体主体20也可以经由非导电层被安装至引线框架41。代替导电层或者除了导电层之外,例如,半导体主体20可以使用电连接(诸如,结合接线3)被电连接至引线框架41。引线框架41(例如,引线框架41的第二腿部)可以被机械连接和电连接至印刷电路板7。印刷电路板7可以提供在被连接至同一印刷电路板7的两个或更多个半导体设备21之间的电连接。当L形引线框架41被连接至印刷电路板7时,引线框架41的第一腿部可以与印刷电路板7的主表面基本上平行,并且引线框架41的第二腿部可以基本上垂直于印刷电路板7的主表面和引线框架41的第一腿部。不同的独立引线框架41的第一腿部可以被设置在相同平面中。这意味着,不同的引线框架41的第一腿部与印刷电路板7之间的距离基本上相等。如上面已经参照图1所描述的,引线框架41与印刷电路板7之间的连接可以包括焊料连接、压配连接或者任何其它合适的连接。
半导体主体20、半导体设备21的任何电连接3、以及安装半导体主体20的对应引线框架41的至少一部分可以被成型到成型材料81中。例如,成型材料81可以是硬封装材料。这意味着,成型材料81在被硬化时具有一定硬度。引线框架41的第一腿部可以形成半导体设备21的底侧。半导体主体20的底侧可以被设置在引线框架41上并且被连接至引线框架41。半导体主体20的所有其它表面可以被成型材料81包围。
两个或更多个分立半导体设备21被设置在外壳5内。如在图4中示例性地图示的,外壳5可以至少包括侧壁。外壳5的侧壁可以形成框架。可选地,外壳5还可以包括地表面和/或盖子。独立半导体设备21被设置在外壳5内,使得引线框架41在限定位置处从外壳5突出。通过这种方式,印刷电路板7可以在后期被容易地连接至引线框架41。在图4所图示的示例中,独立半导体设备21被安装在散热器6上。与图3的装置相比,所有独立半导体设备21都被安装至同一散热器6。因此,散热器6在所图示的示例中形成外壳5的连续地表面。隔离材料层92可以被设置在散热器6上。独立半导体设备21可以被设置在隔离材料层92上,使得隔离材料层92被设置在独立半导体设备21与散热器6之间。当半导体设备21被安装在散热器6上时,单独的引线框架41被设置在相应的半导体主体20与隔离材料层92之间。散热器6通常包括金属或其它导电材料。隔离材料层92将半导体设备21与散热器6介电隔离,因此,也将半导体设备21彼此介电隔离。通过这种方式,不同的半导体设备21之间的任何不想要的电连接都可以被阻止。例如,独立半导体设备21之间的电连接仅可以经由印刷电路板7被提供。
由外壳5和散热器6形成的容积可以至少部分地用铸造化合物8填充。例如,铸造化合物8可以包括(填充)环氧树脂、有机硅、聚合物或者任何其它合适的铸造材料。例如,铸造化合物8可以包括:包括诸如Al2O3、Si2O、BrN或AlN的填充物的材料。铸造化合物8可以具有在成型材料81的硬度的范围内的硬度,或者比成型材料81的硬度小的硬度。例如,成型材料81还可以包括诸如Al2O3、Si2O、BrN或AlN的填充物。通常,成型材料81和铸造化合物8的材料可以是相同的和/或包括相同的填充物,但是可以在其硬度上彼此不同。通过用铸造化合物8填充其中设置有半导体设备21的外壳5,通过成型材料81和附加的铸造化合物8,来很好地保护半导体主体20免受任何环境影响以及环境条件的影响。此外,功率半导体模块装置可以以比较有成本效益的方式被制造。例如,印刷电路板7可以在形成铸造化合物8之后被设置在半导体模块装置上。
现在参照图5,示意性地图示了在将其安装至印刷电路板和散热器之前的功率半导体模块装置。例如,独立半导体设备21首先可以被设置在基层94上。例如,基层94可以是粘合箔或者可以包括粘合箔。当被设置在粘合箔上时,半导体设备21可以粘合至箔,因此,可以被保持在基层94上的适当位置。框架52可以被设置为包围半导体设备21。由框架52和基层94形成的容积然后可以至少部分地用铸造化合物8填充。当将形成铸造化合物8的材料填充到框架52内的容积中时,例如,该材料可以具有液体、粘性或凝胶状稠度。在之后的硬化步骤中,可以从材料中去除流体中的至少一些流体,从而使铸造化合物8硬化。然而,这仅是示例。形成铸造化合物8的材料可以包括在硬化步骤中至少部分地被去除的溶剂。根据另一示例,形成铸造化合物8的材料不包括任何溶剂,并且硬化步骤包括执行聚合物反应。
根据另一示例,基层94不包括粘合箔。如果半导体设备21未粘合至基层94,则当形成铸造化合物8的材料被填充到框架52内的容积中时,半导体设备21可能会移位并且可能未被保持在适当位置。因此,保持设备72可以被用于将半导体设备21保持在适当位置。这在图6中示例性地图示了。保持设备72可以被配置为将半导体设备21按压至基层94,从而将半导体设备21保持在其相应位置中。如上面已经关于图5解释的,形成铸造化合物8的材料可以被填充到由框架52和基层94形成的容积中,并且随后可以被硬化。
然而,也有可能的是,框架52和基层94未被设置为如已经关于图5和图6所描述的单独部件。如在图7中示意性地图示的,框架52和基层94可以形成连续模具。这意味着框架52和基层94由相同材料一体式形成。半导体设备21可以在形成铸造化合物8的同时被设置在该模具内。例如,模具可以包括底部(基层94)和侧壁(框架52)。半导体设备21可以被设置在模具的底部上,并且可以借助于保持设备72被保持在其相应位置中,如上面已经关于图6解释的。形成铸造化合物8的材料可以被填充到由模具形成的容积中。在将材料填充到容积中之后,该材料随后可以被硬化以形成铸造化合物8。然后可以从模具中去除包括其中成型有半导体设备21的硬化的铸造化合物8的装置。
图5至图7示例性地图示了用于形成铸造化合物8的不同替代方式。在图8中图示了再一示例性方法。半导体设备21可以被设置在基层94上。该示例中的框架5和铸造化合物8由所谓的筑坝填充(Dam and Fill)工艺形成。如在图8A中示意性地图示的,坝或壁54可以在第一步骤中被形成。坝54可以包围被设置在基层94上的半导体设备21。坝54对应于图5至图7的示例中的框架5。这意味着容积由坝54和基层94形成。半导体设备21被设置在该容积内的基层94上。例如,坝54可以包括任何合适的筑坝填充材料,诸如,填充环氧树脂。坝54可以包括单个材料层,或者可以包括被设置在彼此顶部上的多个材料层,如在图8中示意性地图示的。在形成坝54之后的随后步骤中,由坝54和基层94形成的容积用形成铸造化合物8的材料填充,如在图8B中示意性地图示的。如上面已经参照图5至图7描述的,在将材料填充到容积中之后,该材料随后可以被硬化,以形成其中成型有半导体设备21的铸造化合物8。在筑坝填充工艺期间,保持设备72可以被用于将半导体设备21保持在基层94上的适当位置。然而,也有可能的是,如上面已经关于图5描述的,基层94包括粘合箔,因此,不需要保持设备72来将半导体设备21保持在适当位置。
在形成铸造化合物8时,尤其是在使容积内的材料硬化时,铸造化合物8的底表面可能会变形。这意味着,在使铸造化合物8硬化之后,底表面可能不是完全平面的并且可能具有一定偏转。也有可能的是,在操作功率半导体模块装置期间,在后期发生铸造化合物8的偏转。为了防止功率半导体模块装置的这种偏转,铸造化合物8可以具有与成型材料81的膨胀系数类似的膨胀系数。例如,成型材料81的膨胀系数和铸造化合物8的膨胀系数可以例如在5与40ppm/K之间或者在10与20ppm/K之间。
现在参照图9,基层94可以在形成铸造化合物8之后被去除。图9A示例性地图示了图5的装置,其中,基层94已经被去除。框架52也可以被去除(未示出),或者如图9A所图示的,框架52可以仍然被附接至铸造化合物8。图9B示例性地图示了图8的装置,其中,基层94已经被去除,并且其中,坝54依然被附接至铸造化合物8。图9C示例性地图示了图6的装置,其中,基层94已经被去除。如在图9C所图示的示例中可以看到的,铸造化合物8可以包括凹口74。这是因为保持设备72在形成铸造化合物8之后被去除。在形成铸造化合物8的步骤期间,没有材料可以到达保持设备72被设置的那些地方。然而,当半导体主体20被独立成型在成型材料81中时,凹口74不一定必须在去除保持设备72之后用材料填充。半导体主体20可以受到成型材料81以及覆盖半导体设备21的外部表面的大部分的铸造化合物8的足够保护。然而,如果期望的话,凹口74随后可以用材料填充。被用于填充凹口74的材料可以是与形成铸造化合物8的材料相同的材料。
如上面已经描述的,用于生产功率半导体模块的方法可以包括以下步骤。在第一步骤中,半导体设备21可以被设置在基层94上,并且框架52可以被设置为包围基层94上的半导体设备21。例如,框架52可以包括坝54或模具的侧壁。一般而言,框架52可以是适合于与基层94一起形成容积并且保持形成铸造化合物8的材料的任何结构。在随后步骤中,形成铸造化合物8的材料被填充到由框架52和基层94形成的容积中。该材料至少部分地填充容积。在之后步骤中,材料被硬化以形成铸造化合物8。当铸造化合物8已经硬化时,基层94可以被去除。然而,也有可能的是,基层94依然被附接至功率半导体模块装置。框架52可以被去除,或者可以依然被附接至功率半导体模块装置。例如,如果框架52在形成铸造化合物8之后被去除,则其中成型有半导体设备21的铸造化合物8随后可以被设置在另一框架或外壳5中。如果框架52未被去除,则框架52本身随后可以形成功率半导体模块装置的外壳5。
现在参照图10,示例性地图示了功率半导体模块装置。在图10的功率半导体模块装置中,被成型在铸造化合物8中的半导体设备21被设置在外壳56内。紧固元件62可以被附接至外壳56。紧固元件62可以被用于将功率半导体模块装置附接至散热器(未在图10中被图示)。例如,紧固元件62可以各自包括螺纹孔。螺钉可以被插入到螺纹孔中的每个螺纹孔中,以将该装置固定在散热器上。散热器可以包括可以插入螺钉的对应螺纹孔。然而,功率半导体模块装置可以以任何其它合适的方式被附接并固定至散热器。紧固元件62可以在形成铸造化合物8之前或之后被附接至外壳56。如在图10的示例中所图示的,紧固元件62可以被附接至外壳56的外部。例如,紧固元件62可以被胶合至或被拧至外壳56。然而,紧固元件62也可以与外壳56一体式形成。然而,这些仅是示例。紧固元件62可以以任何其它合适的方式被附接至外壳56(或框架52)。
参照图11,示例性地图示了已经使用筑坝填充工艺(如上面已经关于图8所描述的)形成的功率半导体模块装置。该示例中的紧固元件62包括被成型到铸造化合物8中的第一部分以及被配置为被连接至散热器的第二部分。当铸造化合物8被形成时,紧固元件62可以被成型到铸造化合物8中。紧固元件62可以环绕框架或坝54,使得紧固元件62的一个部分被设置在由框架或坝54和基层94形成的容积中,并且紧固元件62的第二部分被设置在框架或坝54的另一侧。当形成铸造化合物8的材料被填充到容积中时,紧固元件62的第一部分可以突出到材料中,使得它在使材料硬化时被成型到铸造化合物8中。在图11中,针对包括坝54的装置,示例性地图示了这种装置。然而,这仅是示例。如图11所描述的紧固元件62可以与任何其它种类的框架52或模具组合。
如果筑坝填充工艺被用于形成铸造化合物8,则紧固元件62还可以被设置为突出穿过坝54,如在图12中示例性地图示的。例如,紧固元件62可以在形成坝54的同时被放置在其预期位置中。例如,一个或多个材料层可以被沉积在基层94上。然后,在沉积另外的材料层以完成坝54之前,紧固元件62可以被放置在仅部分完成的坝54上。通过这种方式,紧固元件62至少部分地被嵌入在形成坝54的材料中。紧固元件62的第一部分可以突出并且可以被成型到铸造化合物8中。紧固元件62的第二部分可以突出到装置的外部并且可以被配置为被附接至散热器。
如图11和图12所描述的紧固元件62还可以包括螺纹孔。螺钉可以被插入到螺纹孔中以将该装置固定在散热器上。散热器可以包括可以插入螺钉的对应螺纹孔。然而,功率半导体模块装置可以以任何其它合适的方式被附接并固定至散热器。
现在参照图13,功率半导体模块装置可以进一步包括接触式集电器设备。例如,接触式集电器设备可以包括金属片72。金属片72可以被成型到铸造化合物8中,并且可以电接触引线框架41中的一个或多个引线框架。接触式集电器设备72可以进一步包括连接器销74。连接器销74可以被配置为从外部电接触金属片72。因此,连接器销74的第一端可以被电连接和机械连接至金属片72,并且可以被成型到铸造化合物8中。连接器销74的第二端可以从铸造化合物8突出,以允许电接触金属片72。例如,连接器销74可以被设置为基本上平行于引线框架41的第二腿部。因此,接触式集电器设备被配置为提供在两个或更多个半导体设备21之间的电连接。在图13中,示例性地图示了一个接触式集电器设备。然而,功率半导体模块装置还可以包括多于一个的接触式集电器设备,每个接触式集电器设备电耦合两个或更多个半导体设备21。例如,接触式集电器设备可以包括栅极集电器或者发射极集电器。例如,栅极集电器可以被配置为电连接两个或更多个半导体设备21的栅极端子。例如,发射极集电器可以被配置为电连接两个或更多个半导体设备21的发射极端子。
现在参照图14,功率半导体模块装置可以包括电子板76。电子板76可以被配置为提供在两个或更多个半导体设备21之间的电连接。类似于已经关于图13所描述的接触式集电器设备,连接器销78可以被连接至电子板76。连接器销78可以被配置为提供端子以电接触电子板76。连接器销78可以被设置为基本上平行于引线框架41的第二腿部。电子板76可以包括电子线路(未示出),该电子线路被配置为将两个或更多个半导体设备21彼此电连接。电子板76可以被成型到铸造化合物8中(未示出),或者可以被设置在铸造化合物8的上表面上。当被设置在铸造化合物8的上表面上时,电子板76可以形成功率半导体模块装置的盖。驱动器设备24可以被安装至电子板76。驱动器设备24可以经由电子板76被电连接至半导体设备21中的至少一个半导体设备,并且可以被配置为控制该至少一个半导体设备21。然而,这仅是示例。可替代地,驱动器设备可以是外部设备,并且可以经由连接器销78和电子板76被连接至半导体设备21。
现在参照图15,引线框架41可以包括多于一个的第一腿部和多于一个的第二腿部。图15示例性地图示了截面平面A-A中的图9A的装置。如在图15中所图示的,引线框架41可以包括多于一个的引线框架部件。在图15的示例中,示例性地图示了三个不同的引线框架部件411、412、413。例如,半导体设备21可以包括IGBT。第一引线框架部件411可以电接触IGBT的栅极,第二引线框架部件412可以电接触IGBT的发射极,并且第三引线框架部件413可以电接触IGBT的集电极。例如,在半导体主体20与引线框架设备411、412、413之间的电连接3可以包括结合接线。引线框架设备411、412、413可以被设置为基本上彼此平行。引线框架设备411、412、413可以不彼此电连接。然而,一个半导体设备21的一个引线框架设备411、412、413可以被电连接至另一半导体设备21的引线框架设备411、412、413。例如,这种电连接可以包括接触式集电器设备或者电子板。
引线框架设备可以被设置在距相邻的引线框架设备一定距离a处。在图15中,针对第一引线框架设备411和第二引线框架设备412,示例性地图示了这一点。在图15中,引线框架设备411、412、413的第二腿部在垂直于铸造化合物8和半导体主体20的主表面的方向上基本上是直的。然而,这仅是示例。为了增加两个相邻的引线框架设备411、412、413之间的爬电距离和气隙,一个或多个引线框架设备411、412、413可以被弯曲。例如,引线框架设备411的第二腿部可以被弯曲,使得引线框架设备411的第二端与相邻的引线框架设备412的第二端之间的距离b大于原始距离a。这在图16中示例性地图示了。引线框架设备411的弯曲点可以被成型到铸造化合物8中。
功率半导体模块装置随后可以被安装至散热器6。一些半导体设备21已经提供介电隔离层92。这种介电隔离层可以被设置在半导体设备21的底侧上。这是当被安装至散热器6时半导体设备21面向散热器6的一侧。然而,其它半导体设备21不提供这种介电隔离层92。那么可以在将功率半导体装置安装在散热器6上之前,形成介电隔离层92。介电隔离层92可以被形成在散热器6上,并且功率半导体模块随后可以被设置在散热器6上,使得介电隔离层92被设置在功率半导体模块装置与散热器6之间。然而,也有可能的是,介电隔离层92被形成在功率半导体装置的底侧上,然后功率半导体装置被设置在散热器6上,使得介电隔离层92被设置在功率半导体装置与散热器6之间。介电隔离层92可以以任何合适的方式被形成。例如,介电隔离层92可以包括箔,该箔被层压或胶合至功率半导体模块装置和/或散热器6。介电隔离层92也可以被喷射到功率半导体模块装置或散热器6上,或者被成型至功率半导体模块装置或散热器6。例如,介电隔离层92可以包括绝缘漆。
在形成铸造化合物8并且从功率半导体模块装置去除基层94之后,功率半导体模块装置的底侧可能不是完全平面的。功率半导体模块装置的底侧是当功率半导体模块装置被安装至散热器6时面向散热器6的一侧。如果底侧不是完全平面的,则功率半导体模块装置与散热器6之间的连接可能不稳定。腔可能被形成在功率半导体模块装置与散热器6之间。这可能会对功率半导体模块装置与散热器6之间的传热产生不利影响。因此,在将功率半导体模块装置安装至散热器6之前,可以对功率半导体模块装置的底侧进行抛光。
通常,在将形成铸造化合物8的材料填充到由框架52和基层94形成的容积中之前,半导体设备21的成型材料81可以完全硬化。然而,也有可能的是,在将它们设置在半导体装置中之前,以及在将形成铸造化合物8的材料填充到由框架52和基层94形成的容积中之前,成型材料81仅被预硬化。即,成型材料81可能不会完全硬化。成型材料81可以在铸造化合物8被硬化的同时完全硬化(成型后固化)。因此,在一个单硬化步骤中,铸造化合物8和被预硬化的成型材料81可以被硬化。
例如,半导体设备21可以具有粗糙或粗化的外部表面。半导体设备21的外部表面是直接与铸造化合物8接触的表面。具体地,成型材料81的外部表面可以是粗糙的。即,外部表面不是完全平滑的。通过这种方式,半导体设备21与铸造化合物8之间的附着性可以被增加。例如,半导体设备21的外部表面可以具有例如≥16的平均表面粗糙度Rz。为了使半导体设备21的表面粗化,半导体设备21可以在将它们设置在半导体模块中之前被处理。处理半导体设备21可以包括喷砂、化学粗化或者形成从成型材料81突出的结构。例如,这种结构可以在形成成型材料81时被形成。图17(左侧)示例性地图示了铸造模具90。铸造模具90在至少一侧上包括凸起或突出部。当在其上设置有半导体主体20的引线框架41被放置在铸造模具90中(图17,中间)并且铸造模具90被填充有成型材料81时,这导致成型材料81在至少一侧上具有突出部或结构(图17,右侧)。铸造模具90可以包括具有凸起或突出部91的仅一侧。然而,铸造模具90还可以包括具有凸起或突出部91的不止一侧。然而,这种结构可能不是必须与成型材料81同时被形成,而是也可以在后期被形成。
基层94可以包括第一箔。例如,第一箔可以包括诸如填充环氧树脂的材料。第一箔可以具有大约50至大约300μm的厚度。第一箔可以具有一定的粘合性。例如,第一箔可以被设置在载体箔上。例如,载体箔可以包括诸如聚合物的材料。然而,也有可能的是,例如,载体箔包括诸如铜的金属。例如,载体箔可以具有大约30至大约100μm的厚度。半导体设备21可以被设置在包括第一层和载体层的基层94上,使得第一层被设置在半导体设备21与载体层之间。如上面已经关于图5所描述的,例如,框架52可以被设置为包围被设置在基层94上的半导体设备21。然后由框架52和基层94形成的容积可以被填充有形成铸造化合物8的材料。硬化步骤可以随后,以硬化铸造化合物8,如上面已经描述的。在硬化步骤期间,第一箔的粘合性质可以被提高。例如,在将半导体设备21设置在第一箔上时,第一箔可以仅被预硬化。当硬化铸造化合物8时,第一箔也可以被硬化。这可以改变第一箔的粘合性质。因此,半导体设备21很好地粘合至基层94。为了进一步提高半导体设备21与基层94之间的粘合性,半导体设备21的下表面可以被粗化。例如,使半导体主体21粗化可以包括喷砂、化学粗化或者形成从半导体设备21突出的结构。
Claims (15)
1.一种功率半导体模块装置,包括:
两个或更多个独立半导体设备(21),每个半导体设备(21)包括引线框架(41)、被设置在所述引线框架(41)上的半导体主体(20)、以及围绕所述引线框架(41)的至少一部分和所述半导体主体(20)的成型材料(81);
框架(52),所述框架(52)包围所述两个或更多个半导体设备(21);以及
铸造化合物(8),所述铸造化合物(8)至少部分地填充所述框架(52)内的容积,从而至少部分地围绕所述两个或更多个独立半导体设备(21)。
2.根据权利要求1所述的功率半导体模块装置,进一步包括散热器(6),其中:
其中围绕有所述半导体设备(21)的所述铸造化合物(8)被安装至所述散热器(6);以及
所述散热器(6)和所述框架(52)一起形成所述功率半导体模块装置的外壳,其中所述散热器(6)形成所述外壳的底部并且所述框架(52)形成所述外壳的侧壁。
3.根据权利要求2所述的功率半导体模块装置,进一步包括被设置在所述引线框架(41)与所述散热器(6)之间的电隔离材料层(92)。
4.根据权利要求1、2或3所述的功率半导体模块装置,其中:
每个引线框架(41)包括第一腿部和第二腿部;
每个半导体设备(21)的所述半导体主体(20)被设置在相应的所述引线框架(41)的所述第一腿部上;以及
所述引线框架(41)的所述第二腿部基本上垂直于所述第一腿部。
5.根据权利要求4所述的功率半导体模块装置,其中独立的所述引线框架(41)的所述第二腿部从所述铸造化合物(8)突出。
6.根据权利要求4或5所述的功率半导体模块装置,其中所述引线框架(41)的所述第二腿部被配置为被耦合至印刷电路板(7)、接触式集电器设备或者电子板(76)。
7.根据权利要求6所述的功率半导体模块装置,其中所述印刷电路板(7)、所述接触式集电器设备和所述电子板(76)被配置为提供在两个或更多个半导体设备(21)之间的电连接。
8.根据前述权利要求中任一项所述的功率半导体模块装置,其中所述铸造化合物(8)包括环氧树脂、有机硅或者聚合物。
9.根据前述权利要求中任一项所述的功率半导体模块装置,其中:
所述成型材料(81)具有在5ppm/K与40ppm/K之间的膨胀系数;以及
所述铸造化合物(8)具有在5ppm/K与40ppm/K之间的膨胀系数。
10.根据权利要求9所述的功率半导体模块装置,其中:
所述成型材料(81)具有在10ppm/K与20ppm/K之间的膨胀系数;以及
所述铸造化合物(8)具有在10ppm/K与20ppm/K之间的膨胀系数。
11.根据前述权利要求中任一项所述的功率半导体模块装置,进一步包括至少一个紧固元件(62),其中所述至少一个紧固元件(62)被配置为将所述功率半导体模块装置附接至散热器(6)。
12.根据前述权利要求中任一项所述的功率半导体模块装置,其中所述半导体设备(21)中的至少一个半导体设备的至少一个外部表面包括至少16的平均表面粗糙度(Rz)。
13.一种用于生产功率半导体模块装置的方法,所述方法包括:
在基层(94)上设置两个或更多个独立半导体设备(21),每个半导体设备(21)包括引线框架(41)、被设置在所述引线框架(41)上的半导体主体(20)、以及围绕所述引线框架(41)的至少一部分和所述半导体主体(20)的成型材料(81);
在所述基层(94)上设置框架(52),使得所述框架(52)包围所述两个或更多个半导体设备(21);
将第一材料填充到由所述基层(94)和所述框架(52)形成的容积中;以及
使所述第一材料硬化,从而形成铸造化合物(8),所述铸造化合物(8)至少部分地填充所述容积,从而至少部分地围绕所述两个或更多个独立半导体设备(21)。
14.根据权利要求13所述的方法,进一步包括以下中的至少一个:
在形成所述铸造化合物(8)之后,去除所述基层(94);
在形成所述铸造化合物(8)之后,去除所述框架(52);
将所述引线框架(41)连接至印刷电路板(7);
在所述引线框架(41)的底侧上形成电隔离材料层(92);以及
将其中围绕有所述半导体设备(21)的所述铸造化合物(8)设置在散热器(6)上。
15.根据权利要求13或14所述的方法,其中所述基层(94)包括第一层和载体层,其中所述两个或更多个半导体设备(21)被设置在所述基层(94)上,使得所述第一层被设置在所述半导体设备(21)与所述载体层之间,并且其中使所述铸造化合物(8)硬化的步骤进一步包括使第一箔硬化,从而改变所述第一箔的粘合性质。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP17207680.4A EP3499560B1 (en) | 2017-12-15 | 2017-12-15 | Semiconductor module and method for producing the same |
EP17207680.4 | 2017-12-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109935574A true CN109935574A (zh) | 2019-06-25 |
CN109935574B CN109935574B (zh) | 2023-07-04 |
Family
ID=60673686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811535412.XA Active CN109935574B (zh) | 2017-12-15 | 2018-12-14 | 半导体模块和用于生产半导体模块的方法 |
Country Status (3)
Country | Link |
---|---|
US (3) | US10867902B2 (zh) |
EP (1) | EP3499560B1 (zh) |
CN (1) | CN109935574B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220359365A1 (en) * | 2017-12-15 | 2022-11-10 | Infineon Technologies Ag | Power semiconductor module arrangement |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6180646B1 (ja) * | 2016-02-25 | 2017-08-16 | 三菱電機株式会社 | 半導体パッケージ、及びモジュール |
JP7199921B2 (ja) * | 2018-11-07 | 2023-01-06 | ローム株式会社 | 半導体装置 |
DE102019206523A1 (de) * | 2019-05-07 | 2020-11-12 | Zf Friedrichshafen Ag | Leistungsmodul mit gehäusten Leistungshalbleitern zur steuerbaren elektrischen Leistungsversorgung eines Verbrauchers |
KR102562315B1 (ko) * | 2019-10-14 | 2023-08-01 | 삼성전자주식회사 | 반도체 패키지 |
EP3896726A1 (de) * | 2020-04-17 | 2021-10-20 | Siemens Aktiengesellschaft | Halbleitermodul mit einem gehäuse |
US11404336B2 (en) * | 2020-06-29 | 2022-08-02 | Infineon Technologies Austria Ag | Power module with metal substrate |
EP3958305B1 (en) * | 2020-08-17 | 2023-09-27 | Infineon Technologies AG | Power semiconductor module arrangement and method for producing the same |
EP3961703A1 (de) * | 2020-08-25 | 2022-03-02 | Siemens Aktiengesellschaft | Halbleitermodul und halbleiteranordnung |
JP2022125612A (ja) * | 2021-02-17 | 2022-08-29 | 株式会社東芝 | パワーモジュール |
TWI769761B (zh) * | 2021-03-26 | 2022-07-01 | 艾姆勒車電股份有限公司 | 絕緣導熱基材 |
TWI771259B (zh) * | 2021-03-26 | 2022-07-11 | 艾姆勒車電股份有限公司 | 絕緣導熱基材 |
DE102022207435A1 (de) | 2022-07-21 | 2024-02-01 | Zf Friedrichshafen Ag | Leistungselektronikmodul |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5362775A (en) * | 1991-03-27 | 1994-11-08 | Nippondenso Co., Ltd. | Epoxy resin composition and cured product thereof |
US20050045369A1 (en) * | 2003-08-28 | 2005-03-03 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for manufacturing the same |
US20060202323A1 (en) * | 2005-03-09 | 2006-09-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor module |
JP2013058812A (ja) * | 2005-05-11 | 2013-03-28 | Toshiba Corp | 半導体装置 |
US20130161801A1 (en) * | 2011-12-23 | 2013-06-27 | Infineon Technologies Ag | Module Including a Discrete Device Mounted on a DCB Substrate |
US20140001613A1 (en) * | 2012-06-29 | 2014-01-02 | Samsung Electro-Mechanic Co., Ltd. | Semiconductor package |
DE102016202067A1 (de) * | 2015-03-16 | 2016-10-13 | Mitsubishi Electric Corporation | Leistungshalbleitervorrichtung |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19639025C2 (de) * | 1996-09-23 | 1999-10-28 | Siemens Ag | Chipmodul und Verfahren zur Herstellung eines Chipmoduls |
DE10017741A1 (de) * | 2000-04-10 | 2001-10-25 | Infineon Technologies Ag | Gehäuse für Halbleiterchips |
TWI275189B (en) * | 2003-12-30 | 2007-03-01 | Osram Opto Semiconductors Gmbh | Radiation-emitting and/or radiation-receiving semiconductor component and method for producing such component |
DE102005038443A1 (de) * | 2005-08-16 | 2007-02-22 | Robert Bosch Gmbh | Sensoranordnung mit einem Substrat und mit einem Gehäuse und Verfahren zur Herstellung einer Sensoranordnung |
DE102005054631A1 (de) * | 2005-11-16 | 2007-05-24 | Robert Bosch Gmbh | Sensoranordnung mit einem Substrat und mit einem Gehäuse und Verfahren zur Herstellung einer Sensoranordnung |
US7906794B2 (en) * | 2006-07-05 | 2011-03-15 | Koninklijke Philips Electronics N.V. | Light emitting device package with frame and optically transmissive element |
JP2011060927A (ja) * | 2009-09-09 | 2011-03-24 | Hitachi Ltd | 半導体装置 |
US20130203895A1 (en) * | 2009-11-20 | 2013-08-08 | Designer Molecules, Inc. | Curing agents for epoxy resins |
DE102010002945A1 (de) * | 2010-03-17 | 2011-09-22 | Robert Bosch Gmbh | Schaltungsanordnung und zugehöriges steuergerät für ein kraftfahrzeug |
DE102010012039A1 (de) * | 2010-03-19 | 2011-09-22 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zu dessen Herstellung |
WO2015037349A1 (ja) * | 2013-09-13 | 2015-03-19 | 富士電機株式会社 | 半導体装置 |
US9159701B2 (en) * | 2013-09-17 | 2015-10-13 | Infineon Technologies Ag | Method of manufacturing a chip package, chip package, method of manufacturing a chip assembly and chip assembly |
DE102013220880B4 (de) * | 2013-10-15 | 2016-08-18 | Infineon Technologies Ag | Elektronisches Halbleitergehäuse mit einer elektrisch isolierenden, thermischen Schnittstellenstruktur auf einer Diskontinuität einer Verkapselungsstruktur sowie ein Herstellungsverfahren dafür und eine elektronische Anordung dies aufweisend |
US9349709B2 (en) * | 2013-12-04 | 2016-05-24 | Infineon Technologies Ag | Electronic component with sheet-like redistribution structure |
DE102016106137B4 (de) * | 2016-04-04 | 2023-12-28 | Infineon Technologies Ag | Elektronikvorrichtungsgehäuse umfassend eine dielektrische Schicht und ein Kapselungsmaterial |
US9985082B2 (en) * | 2016-07-06 | 2018-05-29 | Lg Display Co., Ltd. | Organic light emitting display device comprising multi-type thin film transistor and method of manufacturing the same |
US10211147B2 (en) * | 2017-07-06 | 2019-02-19 | Globalfoundries Inc. | Metal-insulator-metal capacitors with dielectric inner spacers |
EP3499560B1 (en) * | 2017-12-15 | 2021-08-18 | Infineon Technologies AG | Semiconductor module and method for producing the same |
EP3736855A1 (en) * | 2019-05-06 | 2020-11-11 | Infineon Technologies AG | Power semiconductor module arrangement and method for producing the same |
EP3913665A1 (en) * | 2020-05-18 | 2021-11-24 | Infineon Technologies AG | A power semiconductor module and a method for producing a power semiconductor module |
EP3929973B1 (en) * | 2020-06-22 | 2022-10-26 | Infineon Technologies AG | A power semiconductor module and a method for producing a power semiconductor module |
EP4187596A1 (en) * | 2021-11-29 | 2023-05-31 | Infineon Technologies AG | Power semiconductor module, method for assembling a power semiconductor module and housing for a power semiconductor module |
-
2017
- 2017-12-15 EP EP17207680.4A patent/EP3499560B1/en active Active
-
2018
- 2018-12-14 CN CN201811535412.XA patent/CN109935574B/zh active Active
- 2018-12-14 US US16/220,956 patent/US10867902B2/en active Active
-
2020
- 2020-11-18 US US16/951,556 patent/US11437311B2/en active Active
-
2022
- 2022-07-25 US US17/872,255 patent/US11978700B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5362775A (en) * | 1991-03-27 | 1994-11-08 | Nippondenso Co., Ltd. | Epoxy resin composition and cured product thereof |
US20050045369A1 (en) * | 2003-08-28 | 2005-03-03 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for manufacturing the same |
US20060202323A1 (en) * | 2005-03-09 | 2006-09-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor module |
JP2013058812A (ja) * | 2005-05-11 | 2013-03-28 | Toshiba Corp | 半導体装置 |
US20130161801A1 (en) * | 2011-12-23 | 2013-06-27 | Infineon Technologies Ag | Module Including a Discrete Device Mounted on a DCB Substrate |
US20140001613A1 (en) * | 2012-06-29 | 2014-01-02 | Samsung Electro-Mechanic Co., Ltd. | Semiconductor package |
DE102016202067A1 (de) * | 2015-03-16 | 2016-10-13 | Mitsubishi Electric Corporation | Leistungshalbleitervorrichtung |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220359365A1 (en) * | 2017-12-15 | 2022-11-10 | Infineon Technologies Ag | Power semiconductor module arrangement |
US11978700B2 (en) * | 2017-12-15 | 2024-05-07 | Infineon Technologies Ag | Power semiconductor module arrangement |
Also Published As
Publication number | Publication date |
---|---|
EP3499560A1 (en) | 2019-06-19 |
EP3499560B1 (en) | 2021-08-18 |
US20190189553A1 (en) | 2019-06-20 |
US20210074624A1 (en) | 2021-03-11 |
US11978700B2 (en) | 2024-05-07 |
CN109935574B (zh) | 2023-07-04 |
US10867902B2 (en) | 2020-12-15 |
US20220359365A1 (en) | 2022-11-10 |
US11437311B2 (en) | 2022-09-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109935574A (zh) | 半导体模块和用于生产半导体模块的方法 | |
CN205452265U (zh) | 电子功率模块 | |
CN105612613B (zh) | 半导体装置 | |
JP6530498B2 (ja) | メカトロニクスコンポーネントおよびその製造方法 | |
CN107665867B (zh) | 双包封的功率半导体模块及其制造方法 | |
US11581230B2 (en) | Power semiconductor module and a method for producing a power semiconductor module | |
EP2804209A1 (en) | Moulded electronics module | |
CN106298700A (zh) | 半导体装置 | |
CN111900134A (zh) | 功率半导体模块装置及其制造方法 | |
CN101689538B (zh) | 制造固定功率模块的方法 | |
CN107431067A (zh) | 功率模块 | |
CN112750804A (zh) | 半导体设备封装和其制造方法 | |
JP3169578B2 (ja) | 電子部品用基板 | |
CN116190320A (zh) | 功率半导体模块、用于组装功率半导体模块的方法以及用于功率半导体模块的壳体 | |
US10381283B2 (en) | Power semiconductor module | |
US20210166986A1 (en) | Package with encapsulant under compressive stress | |
CN115312476A (zh) | 具有防刮层的半导体封装及其制造方法 | |
CN104425398A (zh) | 半导体封装、制造半导体封装的方法和叠层式半导体封装 | |
CN111769090A (zh) | 塑封功率模块、塑封模具及塑封方法 | |
KR100991226B1 (ko) | 금속 캡을 구비하는 칩 패키지 조립체 및 그 제조 방법 | |
KR102304909B1 (ko) | 전력 모듈 및 그 제조 방법 | |
CN109712944A (zh) | 具有被部分涂覆的电源端子的功率半导体模块 | |
US11749638B2 (en) | Method for contacting and packetising a semiconductor chip | |
US11404392B1 (en) | Molded semiconductor module for PCB embedding | |
CN219759566U (zh) | 绝缘基板及功率器件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |