CN115312476A - 具有防刮层的半导体封装及其制造方法 - Google Patents
具有防刮层的半导体封装及其制造方法 Download PDFInfo
- Publication number
- CN115312476A CN115312476A CN202210479717.3A CN202210479717A CN115312476A CN 115312476 A CN115312476 A CN 115312476A CN 202210479717 A CN202210479717 A CN 202210479717A CN 115312476 A CN115312476 A CN 115312476A
- Authority
- CN
- China
- Prior art keywords
- thermal conductor
- resistant layer
- semiconductor package
- carrier
- scratch resistant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 230000003678 scratch resistant effect Effects 0.000 title claims description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000002470 thermal conductor Substances 0.000 claims abstract description 68
- 239000004020 conductor Substances 0.000 claims abstract description 48
- 238000005538 encapsulation Methods 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 45
- 229920000642 polymer Polymers 0.000 claims description 12
- 239000002243 precursor Substances 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- 229910010272 inorganic material Inorganic materials 0.000 claims description 8
- 239000011147 inorganic material Substances 0.000 claims description 8
- 239000000945 filler Substances 0.000 claims description 7
- 239000002245 particle Substances 0.000 claims description 6
- 230000032683 aging Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 229920001296 polysiloxane Polymers 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- 238000007598 dipping method Methods 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 150000004756 silanes Chemical class 0.000 claims description 3
- 230000002265 prevention Effects 0.000 abstract description 8
- 239000008393 encapsulating agent Substances 0.000 description 16
- 239000012705 liquid precursor Substances 0.000 description 8
- 239000004519 grease Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 238000006748 scratching Methods 0.000 description 2
- 230000002393 scratching effect Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002894 chemical waste Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 229920000592 inorganic polymer Polymers 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一种半导体封装,包括:载体,包括第一侧和相对的第二侧;半导体管芯,布置在所述载体的所述第一侧上;热导体部件,布置在所述载体的所述第二侧上;包封体,包封所述半导体管芯,其中,所述热导体部件从所述包封体暴露,并且其中,所述热导体部件具有与所述包封体不同的材料成分;以及防刮层,覆盖所述热导体部件,其中,所述防刮层具有的硬度是所述热导体部件的硬度的至少五倍。
Description
技术领域
本公开总体上涉及半导体封装,特别是涉及具有防刮层的半导体封装,以及用于制造这种半导体封装的方法。
背景技术
半导体封装可以是被配置为以高电压和/或高电流操作的高功率器件。特别是这种类型的半导体封装可能需要具有特别低的热阻的散热方案。这样的方案可以例如包括将由封装的半导体管芯产生的热传递到管芯载体并且从管芯载体传递到半导体封装所耦合到的专用散热器或PCB。在不显著增大热路径的热阻的情况下,可能需要将管芯载体与散热器或PCB电绝缘。为此目的,特定的电介质热导体部件可以布置在管芯载体和散热器或PCB之间。然而,这样的热导体部件可能具有相对较低的机械鲁棒性并且因此可能容易受到损坏,例如在客户处理半导体封装的过程中受到刮擦。改进的半导体封装以及用于制造半导体封装的改进方法可以帮助解决这些和其他问题。
本发明所基于的问题由独立权利要求的特征解决。在从属权利要求中描述了进一步的有利示例。
发明内容
各个方面涉及一种半导体封装,包括:包括第一侧和相对的第二侧的载体;布置在载体的第一侧上的半导体管芯;布置在载体的第二侧上的热导体部件;包封半导体管芯的包封体,其中,热导体部件从包封体暴露,并且其中,热导体部件具有与包封体不同的材料成分;以及覆盖热导体部件的防刮层,其中,防刮层具有的硬度至少是热导体部件的硬度的五倍。
各个方面涉及一种用于制造半导体封装的方法,其中该方法包括:提供具有第一侧和相对的第二侧的载体;在载体的第一侧上布置半导体管芯;在载体的第二侧上布置热导体部件;以包封体包封半导体管芯,使得热导体部件从包封体暴露,其中,热导体部件具有与包封体不同的材料成分;以及利用防刮层覆盖热导体部件,其中,防刮层具有的硬度是热导体部件的硬度的至少五倍。
附图说明
附图示出了示例并且与描述一起用于解释本公开的原理。鉴于以下详细描述,将容易理解本公开的其他示例和许多预期优点。附图的要素不必相对于彼此成比例。相同的参考数字表示对应的类似部分。
图1示出了具有布置在热导体部件上的防刮层的半导体封装的截面图。
图2A和2B示出了用于制造防刮层的两种不同的示例性方法。
图3A到3F示出了根据用于制造半导体封装的示例性方法的在制造的各个阶段中包括防刮层的又一半导体封装。
图4是用于制造半导体封装的示例性方法的流程图。
具体实施方式
在以下详细描述中,参考描述的图(单个或多个)的取向使用方向术语,诸如“顶部”、“底部”、“左”、“右”、“上”、“下”等。因为本公开的组件可以以多个不同的取向安置,所以方向术语仅用于说明的目的。
此外,虽然示例的特定特征或方面可以仅相对于若干实施方式中的一个而被公开,但是在对于任何给定的或特定的应用有利或期望时,这样的特征或方面可以与其他实施方式的一个或多个其他特征或方面组合,除非另有特别说明或除非技术上受到限制。此外,就在详细描述或权利要求中使用术语“包含”、“具有”、“带有”或其其他变体而言,这些术语旨在以类似于术语“包括”的方式而是内含的。可以使用术语“耦合”和“连接”及其派生词。应当理解,这些术语可用于表示两个元件彼此协作或相互作用,无论它们是直接物理接触或是电接触,还是它们彼此不直接接触;中间元件或层可以设置在“接合的”、“附接的”或“连接的”元件之间。然而,“接合的”、“附接的”或“连接的”元件彼此直接接触也是可能的。此外,术语“示例性”仅意为示例,而非最佳或最优。
下面描述的半导体封装的示例可以使用各种类型的半导体管芯或结合在半导体管芯中的电路,其中包括AC/DC或DC/DC转换器电路、功率MOS晶体管、功率肖特基二极管、JFET(结栅场效应晶体管)、功率双极晶体管、逻辑集成电路等。半导体管芯(单个或多个)可以具有允许与包括在半导体管芯(单个或多个)中的集成电路进行电接触的接触焊盘(或电极)。电极可以全部布置在半导体管芯(单个或多个)的仅一个主面上或半导体管芯(单个或多个)的两个主面上。
高效的半导体封装以及用于制造半导体封装的改进方法可以例如减少材料消耗、欧姆损耗、化学废物等,并且因此可以使得能够实现能量和/或资源节约。如本说明书中所指定的,改进的半导体封装以及用于制造半导体封装的改进方法可以因此至少间接地有助于绿色技术解决方案,即提供减少能源和/或资源使用的气候友好型解决方案。
图1示出了半导体封装100,其包括载体110、半导体管芯120、热导体部件130、包封体140和防刮层150。
载体110包括第一侧111和相对的第二侧112,其中半导体管芯120布置在载体110的第一侧111上并且热导体部件130布置在第二侧112上。
包封体140包封半导体管芯120,使得热导体部件130从包封体140暴露。热导体部件130特别是具有与包封体140不同的材料成分。
防刮层150覆盖热导体部件130,特别是热导体部件130的外表面。此外,防刮层150的硬度是热导体部件130的硬度的至少五倍。
在本文上下中,术语“硬度”可以指可以例如根据莫氏标度测量的刮擦硬度,或者可以指可以例如根据洛氏、维氏、肖氏或布氏标度测量的压痕硬度。
半导体封装100例如可以是功率半导体封装,被配置为以高电压和/或高电流操作。半导体封装100可以是通孔器件(THD),例如根据TO247规范的封装,或者它可以是表面贴装器件(SMD)。
载体110可以是任何合适类型的管芯载体,例如引线框部件、印刷电路板(PCB)、直接铜接合(DCB)、直接铝接合(DAB)等。载体110可以例如包含Al、Cu或Fe或由Al、Cu或Fe组成。载体110可以至少部分地被包封体140包封。载体110可以被配置为将热从半导体管芯120向热导体部件130传递。
半导体管芯120可以是功率半导体管芯。半导体管芯120可以包括背对载体110的第一侧121和面对载体110的相对的第二侧122。半导体管芯120可以包括位于其第一侧121上的第一功率电极(例如源极、漏极、发射极或集电极电极),并且它可以包括在其第二侧122上的第二功率电极。第二功率电极可以例如通过焊点电耦合到载体110。
根据示例,半导体封装100包括一个以上的半导体管芯120,其可以是相同的管芯或不同类型的管芯。附加管芯(单个或多个)也可以布置在管芯载体110上或一个或多个附加管芯载体上。半导体管芯120可以电耦合以形成电路,例如半桥电路、逆变器电路等。
热导体部件130可以被配置为布置在外部散热器或PCB上并且被配置为允许从载体110到散热器或PCB的热传递。此外,热导体部件130可以被配置为使载体110与散热器或PCB电绝缘。
根据示例,热导体部件130包括硅树脂垫或环氧树脂垫或由硅树脂垫或环氧树脂垫组成,或者它包括任何其他合适的电介质材料的垫或由任何其他合适的电介质材料的垫组成。使用这种垫代替导热油脂(thermal grease)层可能有几个优点。例如,垫材料可以充当“软垫”,当半导体封装100耦合到散热器或PCB时,该软垫被压缩。与导热油脂层相比,压缩垫可以提供降低的热阻。热导体部件130特别是可以是单个连续组件(“垫”)而不是油脂层。
热导体部件130可以包括填料颗粒,特别是被配置为提高热导体部件130的热传递能力的填料颗粒。填料颗粒可以例如包括AlO、BN、AlN和MgO中的一种或多种,或是由AlO、BN、AlN和MgO中的一种或多种组成。热导体部件130可以具有50%或更多、或70%或更多、或甚至90%或更多的填料颗粒含量。
热导体部件130可以例如具有在面向载体110的下侧和相对的上侧之间测量的在2μm至50μm的范围内的厚度,例如约10μm、约20μm、约30μm或约40μm。热导体部件130可以完全或部分地覆盖载体110的第二侧112,例如第二侧112的50%或更多、或70%或更多、或90%或更多可以被热导体部件130覆盖。
包封体140可以具有第一侧141和相对的第二侧142,其中热导体部件130布置在第二侧142处。热导体部件130可以从第二侧142突出,如图1的示例中所示。热导体部件130可以例如突出10μm或更多、或20μm或更多、或30μm或更多(突出量是垂直于第二侧142测量的)。
热导体部件130和包封体140的第二侧142可以构成半导体封装100的背面。热导体部件130可以占背面的表面积的30%或更多、或50%或更多、或70%或更多、或90%或更多。
根据示例,热导体部件130直接布置在载体110的第二侧112上,而没有任何中间层或组件。
包封体140可以例如是包括任何合适的模制材料或由任何合适的模制材料组成的模制体。与热导体部件130相比,包封体140可以是基本上不可压缩的。特别地,包封体140在用于将散热器或PCB压到热导体部件130的压力量下可以是尺寸稳定的。
根据示例,载体110部分地从包封体140暴露。例如,载体110的外部接触部分可以被暴露。
防刮层150可以完全覆盖热导体部件130的上侧。防刮层150可以具有任何合适的厚度,例如在0.2μm至20μm的范围内的厚度,例如约1μm、约5μm、约10μm或约15μm。
根据示例,防刮层150包括无机材料。防刮层150的无机材料的含量可以相对高于热导体部件130的无机材料的含量。无机材料可以负责防刮层150的硬度。根据示例,防刮层150具有68MPa的硬度或甚至200MPa的硬度。相比之下,热导体部件130可以例如具有大约10MPa的硬度。
根据示例,防刮层150包括有机-无机杂化聚合物或由有机-无机杂化聚合物组成。合适的有机-无机杂化聚合物例如从在DE4303570A1和DE3828098A1中详细描述的所谓的ORMOCER化合物获得。这些化合物可以包括硅烷,其可以允许防刮擦层150与热导体部件130的强粘附(特别是在热导体部件130包括有机硅或由有机硅组成的情况下)。
有机-无机杂化聚合物可以根据各种要求进行定制。一种特殊的该要求是制造特别薄但鲁棒的防刮层。根据示例,防刮层150因此可以具有如此小的厚度,以致其基本上不会抑制从半导体管芯120到布置在热导体部件130上方的散热器或PCB的热传递。
图2A和2B示出了用于将防刮层150施加到热导体部件130上的两种示例性方法。
如图2A中所示,冲压设备200可用于将防刮层150的液体前体210转移到热导体部件130的上侧。液体前体210例如可以是ORMOCER漆。
根据示例,在热导体部件130已经完全固化之前施加液体前体210。换言之,当施加液体前体210时,热导体部件130本身仍可为半流体。这可以提高防刮层150和热导体部件130之间的粘附性。在已经施加液体前体210之后,可以执行共同的固化工艺以固化热导体部件130和液体前体210(从而形成防刮层150)。根据另一示例,在热导体部件130已经固化之后施加液体前体210。
作为图2A中所示的印刷工艺的替代,喷涂、浸渍、喷射或任何其他合适的方法可用于将液体前体210施加到热导体部件130。
图2B示出了用于制造防刮层150的替代技术。代替将一些附加材料转移到热导体部件130上并固化该附加材料,防刮层150可以替代地由热导体部件130本身制造。特别地,热导体部件130的上侧可以暴露于“快速老化”处理,这可以降低有机材料的相对含量并因此增大上侧处的无机(填料)材料的相对量。这种处理可以例如包括暴露于热、UV光和/或等离子体220。
可以选择快速老化处理的条件(例如,暴露时间、温度、电场强度等),使得形成防刮层150但同时避免对半导体管芯120、载体110和包封体140的损坏。
图3A到3F示出了根据用于制造半导体封装的示例性方法的处于制造的各个阶段的半导体封装300。类似的方法可以用于制造半导体封装100。半导体封装300可以类似于半导体封装100。
如图3A中所示,提供载体110。载体110可以例如布置在临时载体310(例如胶带)上,使得载体110的第二侧112面向临时载体310。
如图3B中所示,半导体管芯120布置在载体110的第一侧111上。这还可以包括将半导体管芯120电耦合到载体110。
如图3C中所示,半导体管芯120被以包封体140包封。载体110也可以被至少部分地包封。包封体140例如可以是模制体,其使用例如传递模制或压缩模制的模制技术形成。
包封体140可以包括开口143,其中载体110在开口143内从包封体140暴露出来。开口143可以例如在模制工艺期间制造,或者它可以通过在模制工艺之后去除材料来制造。
如图3D中所示,热导体部件130布置在载体110上。热导体部件130可以特别地布置在开口143中并且它可以完全填充开口143。热导体部件130可以从包封体140的第二侧142突出。
将热导体部件130布置在载体110上可以例如包括施加流体前体并固化前体以获得热导体部件130。替代地,可以通过拾取和放置工艺以固化形式沉积热导体部件130。
可以在已经形成包封体140之后将热导体部件130布置在载体110上,如图3C和3D中所示。然而,根据另一示例,在已经形成热导体部件130之后制造包封体140也是可能的。
如图3E中所示,热导体部件130,特别是其上侧,覆盖有防刮层150。这可以包括沉积前体,例如关于图2A所述,或者它可以包括老化热导体部件130的上侧,如关于图2B所述。
防刮层150可以被配置为在半导体封装300的进一步处理期间保护热导体部件130免受损坏。对热导体部件130的损坏,例如刮擦,可能导致载体110不再是适当地电绝缘的。
如图3F中所示,半导体封装300可以耦合到外部部件320,例如散热器或PCB,使得外部部件320布置在防刮层150上。由此,热导体部件130可以被压缩,使得其不再从包封体140突出。压缩的热导体部件130和相对薄的防刮层150在载体110和外部部件320之间提供了具有低热阻的热路径。
图4是用于制造半导体封装的示例性方法400的流程图。方法400可以例如用于制造半导体封装100和300。
方法400包括:在401处提供具有第一侧和相对的第二侧的载体的动作;在402处将半导体管芯布置在载体的第一侧上的动作;在403处将热导体部件布置在载体的第二侧上的动作;在404用包封体包封半导体管芯使得热导体部件从包封体暴露的动作,其中热导体部件具有与包封体不同的材料成分;以及在405,用防刮层覆盖热导体部件的动作,其中防刮层具有的硬度是热导体部件的硬度的至少五倍。
示例
在下文中,使用具体示例进一步解释半导体封装以及用于制造半导体封装的方法。
示例1是一种半导体封装,包括:载体,包括第一侧和相对的第二侧;半导体管芯,布置在所述载体的所述第一侧上;热导体部件,布置在所述载体的所述第二侧上;包封体,包封所述半导体管芯,其中,所述热导体部件从所述包封体暴露,并且其中,所述热导体部件具有与所述包封体不同的材料成分;以及防刮层,覆盖所述热导体部件,其中,所述防刮层具有的硬度是所述热导体部件的硬度的至少五倍。
示例2是示例1所述的半导体封装,其中,所述防刮层具有比所述热导体部件相对更高的无机材料含量。
示例3是示例1或2所述的半导体封装,其中,所述防刮层包括有机-无机杂化聚合物或由有机-无机杂化聚合物组成。
示例4是示例3所述的半导体封装,其中,所述有机-无机杂化聚合物包括一种或多种硅烷。
示例5是前述示例中任一个所述的半导体封装,其中,所述热导体部件包括硅树脂垫或由硅树脂垫组成。
示例6是前述示例中任一个所述的半导体封装,其中,所述防刮层具有在0.2μm至20μm的范围内的厚度。
示例7是前述示例中任一个所述的半导体封装,其中,所述热导体部件从所述包封体的外表面突出。
示例8是前述示例中任一个所述的半导体封装,其中,所述热导体部件包括被配置为增大其热导率的填料颗粒。
示例9是一种用于制造半导体封装的方法,其中,所述方法包括:提供具有第一侧和相对的第二侧的载体;在所述载体的所述第一侧上布置半导体管芯;在所述载体的所述第二侧上布置热导体部件;用包封体包封所述半导体管芯,使得所述热导体部件从所述包封体暴露,其中,所述热导体部件具有与所述包封体不同的材料成分;以及用防刮层覆盖所述热导体部件,其中,所述防刮层具有的硬度是所述热导体部件的硬度的至少五倍。
示例10是示例9所述的方法,其中,所述覆盖包括在所述热导体部件上沉积有机-无机杂化聚合物前体。
示例11是示例10所述的方法,其中,所述沉积包括将所述有机-无机杂化聚合物前体喷涂、浸渍、印刷或喷射到所述热导体部件上。
示例12是示例10或11所述的方法,还包括:固化所述有机-无机杂化聚合物前体以形成所述防刮层。
示例13是示例9至12中任一个所述的方法,其中,所述防刮层具有比所述热导体部件相对更高的无机材料含量。
示例14是示例9所述的方法,其中,所述覆盖包括老化所述热导体部件以形成所述防刮层。
示例15是示例14所述的方法,其中,通过热施加工艺或通过等离子体施加工艺对所述热导体部件进行老化。
示例16是一种设备,包括用于执行根据示例9至15中任一个的方法的模块。
尽管已经针对一种或多种实施方式说明和描述了本公开,但是在不背离所附权利要求的精神和范围的情况下,可以对说明的示例进行改变和/或修改。特别是关于由上述组件或结构(组合件、器件、电路、系统等)执行的各种功能,除非另有说明,用于描述此类组件的术语(包括对“模块”的引用)旨在对应于执行所描述的组件的特定功能的任何组件或结构(例如,其功能上等同),即使在结构上不等同于执行在此说明的本公开的示例性实施方式中的功能的所公开的结构。
Claims (15)
1.一种半导体封装,包括:
载体,包括第一侧和相对的第二侧,
半导体管芯,布置在所述载体的所述第一侧上,
热导体部件,布置在所述载体的所述第二侧上,
包封体,包封所述半导体管芯,其中,所述热导体部件从所述包封体暴露,并且其中,所述热导体部件具有与所述包封体不同的材料成分,以及
防刮层,覆盖所述热导体部件,其中,所述防刮层具有的硬度是所述热导体部件的硬度的至少五倍。
2.如权利要求1所述的半导体封装,其中,所述防刮层具有比所述热导体部件相对更高的无机材料含量。
3.如权利要求1或2所述的半导体封装,其中,所述防刮层包括有机-无机杂化聚合物或由有机-无机杂化聚合物组成。
4.如权利要求3所述的半导体封装,其中,所述有机-无机杂化聚合物包括一种或多种硅烷。
5.如前述权利要求中任一项所述的半导体封装,其中,所述热导体部件包括硅树脂垫或由硅树脂垫组成。
6.如前述权利要求中任一项所述的半导体封装,其中,所述防刮层具有在0.2μm至20μm的范围内的厚度。
7.如前述权利要求中任一项所述的半导体封装,其中,所述热导体部件从所述包封体的外表面突出。
8.如前述权利要求中任一项所述的半导体封装,其中,所述热导体部件包括被配置为增大其热导率的填料颗粒。
9.一种用于制造半导体封装的方法,其中,所述方法包括:
提供具有第一侧和相对的第二侧的载体,
在所述载体的所述第一侧上布置半导体管芯,
在所述载体的所述第二侧上布置热导体部件,
用包封体包封所述半导体管芯,使得所述热导体部件从所述包封体暴露,其中,所述热导体部件具有与所述包封体不同的材料成分,以及
用防刮层覆盖所述热导体部件,其中,所述防刮层具有的硬度是所述热导体部件的硬度的至少五倍。
10.如权利要求9所述的方法,其中,所述覆盖包括在所述热导体部件上沉积有机-无机杂化聚合物前体。
11.如权利要求10所述的方法,其中,所述沉积包括将所述有机-无机杂化聚合物前体喷涂、浸渍、印刷或喷射到所述热导体部件上。
12.如权利要求10或11所述的方法,还包括:
固化所述有机-无机杂化聚合物前体以形成所述防刮层。
13.如权利要求9至12中任一项所述的方法,其中,所述防刮层具有比所述热导体部件相对更高的无机材料含量。
14.如权利要求9所述的方法,其中,所述覆盖包括老化所述热导体部件以形成所述防刮层。
15.如权利要求14所述的方法,其中,通过热施加工艺或通过等离子体施加工艺对所述热导体部件进行老化。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP21172812.6A EP4086949A1 (en) | 2021-05-07 | 2021-05-07 | Semiconductor package with a scratch protection layer and method of fabrication |
EP21172812.6 | 2021-05-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN115312476A true CN115312476A (zh) | 2022-11-08 |
Family
ID=75887821
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202210479717.3A Pending CN115312476A (zh) | 2021-05-07 | 2022-05-05 | 具有防刮层的半导体封装及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20220359432A1 (zh) |
EP (1) | EP4086949A1 (zh) |
CN (1) | CN115312476A (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN216162757U (zh) * | 2021-05-25 | 2022-04-01 | 三赢科技(深圳)有限公司 | 镜头模组及电子装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3828098A1 (de) | 1988-08-18 | 1990-03-08 | Fraunhofer Ges Forschung | Verfahren und zusammensetzung zur herstellung von kratzfesten materialien |
DE4303570C2 (de) | 1993-02-08 | 1997-03-20 | Fraunhofer Ges Forschung | Verfahren zur Herstellung von funktionellen Beschichtungen, beschichtete Substrate und Beschichtungsmaterial |
JP3581268B2 (ja) * | 1999-03-05 | 2004-10-27 | 株式会社東芝 | ヒートシンク付半導体装置およびその製造方法 |
JP6301602B2 (ja) * | 2013-07-22 | 2018-03-28 | ローム株式会社 | パワーモジュールおよびその製造方法 |
DE102015118245B4 (de) * | 2015-10-26 | 2024-10-10 | Infineon Technologies Austria Ag | Elektronische Komponente mit einem thermischen Schnittstellenmaterial, Herstellungsverfahren für eine elektronische Komponente, Wärmeabfuhrkörper mit einem thermischen Schnittstellenmaterial und thermisches Schnittstellenmaterial |
JP6893084B2 (ja) * | 2016-10-19 | 2021-06-23 | 日東シンコー株式会社 | 熱硬化性接着シート |
-
2021
- 2021-05-07 EP EP21172812.6A patent/EP4086949A1/en active Pending
-
2022
- 2022-05-02 US US17/734,168 patent/US20220359432A1/en active Pending
- 2022-05-05 CN CN202210479717.3A patent/CN115312476A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
EP4086949A1 (en) | 2022-11-09 |
US20220359432A1 (en) | 2022-11-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10734250B2 (en) | Method of manufacturing a package having a power semiconductor chip | |
US20200083207A1 (en) | Method of Manufacturing a Multi-Chip Semiconductor Power Device | |
US10727151B2 (en) | Semiconductor chip package having a cooling surface and method of manufacturing a semiconductor package | |
CN107946258B (zh) | 具有延伸到导热电介质片外的导电层的芯片载体 | |
US8916474B2 (en) | Semiconductor modules and methods of formation thereof | |
CN109216313A (zh) | 具有包括钎焊的导电层的芯片载体的模制封装 | |
CN108735689B (zh) | 具有空间限制的导热安装体的芯片模块 | |
KR101519062B1 (ko) | 반도체 소자 패키지 | |
US7944044B2 (en) | Semiconductor package structure having enhanced thermal dissipation characteristics | |
US11056447B2 (en) | Power module having at least one power semiconductor | |
US8766430B2 (en) | Semiconductor modules and methods of formation thereof | |
CN111276447B (zh) | 双侧冷却功率模块及其制造方法 | |
US20160286655A1 (en) | Semiconductor Package with Integrated Output Inductor on a Printed Circuit Board | |
WO2018141813A1 (en) | Power semiconductor module | |
US20220359432A1 (en) | Semiconductor package with a scratch protection layer and method of fabrication | |
CN104037152A (zh) | 芯片载体结构、芯片封装及其制造方法 | |
US9379050B2 (en) | Electronic device | |
CN216413085U (zh) | 半导体电路 | |
US20130001758A1 (en) | Power Semiconductor Package | |
US9263421B2 (en) | Semiconductor device having multiple chips mounted to a carrier | |
KR20150048459A (ko) | 전력 모듈 패키지 | |
US20240243031A1 (en) | Thermal Enhanced Power Semiconductor Package | |
US20240332102A1 (en) | Package with encapsulant and further encapsulant thereon | |
CN115602634A (zh) | 具有阴刻形表面形状的封装外壳的半导体封装及其制造方法 | |
CN118016625A (zh) | 功率半导体封装及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |