CN115602634A - 具有阴刻形表面形状的封装外壳的半导体封装及其制造方法 - Google Patents

具有阴刻形表面形状的封装外壳的半导体封装及其制造方法 Download PDF

Info

Publication number
CN115602634A
CN115602634A CN202210544193.1A CN202210544193A CN115602634A CN 115602634 A CN115602634 A CN 115602634A CN 202210544193 A CN202210544193 A CN 202210544193A CN 115602634 A CN115602634 A CN 115602634A
Authority
CN
China
Prior art keywords
package
substrate
semiconductor
package housing
negative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210544193.1A
Other languages
English (en)
Inventor
崔伦华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jmj Korea Co ltd
Original Assignee
Jmj Korea Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jmj Korea Co ltd filed Critical Jmj Korea Co ltd
Publication of CN115602634A publication Critical patent/CN115602634A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16052—Shape in top view
    • H01L2224/16055—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16196—Cap forming a cavity, e.g. being a curved metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/1631—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/16315—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/1632—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明提供一种具有阴刻形表面形状的封装外壳的半导体封装及其制造方法，可通过激光阴刻加工的止动件而能够调整用于与散热器的接合及热传送的热传送接合部件的厚度，并且，能够恒定地维持而防止剥离现象，提高热传送效率。

Description

具有阴刻形表面形状的封装外壳的半导体封装及其制造方法
技术领域
本发明涉及一种可通过激光阴刻加工的止动件而能够调整用于与散热器的接合及热传送的热传送接合部件的厚度，并且，能够恒定地维持而防止剥离现象，提高热传送效率的具有阴刻形表面形状的封装外壳的半导体封装及其制造方法。
背景技术
众所周知，电气及电子部件，尤其，半导体部件在运行时发生热量，因此，要通过散热器预防过热，而维持其性能。
尤其，在高电力应用领域应用的半导体部件通过循环冷却剂的散热器而防止过热，并且，向散热器插入与循环的冷却剂接触的冷却部件，而冷却从半导体部件向冷却部件传送的热。
并且，图1表示了以往技术的半导体封装的截面结构，参照该图，通过下部模塑模具(未图示)和上部模塑模具(未图示)，覆盖下部基板21和上部基板22而模塑密封材料，形成封装外壳30，但，因模塑模具的误差，发生密封材料的二次成型(over molding)。
为了介入粘接剂40而将散热器50与下部基板21或上部基板22的裸露面(A)接合，要通过磨轮(grinding wheel)11将下部基板(21)或上部基板22上部的二次成型的密封材料去除。
但，如上述地通过磨轮去除密封材料时，密封材料的消耗量增加，并且，在使用磨轮研磨密封材料时，可能使得构成基板的金属层被磨削而在陶瓷等绝缘层上发生裂纹，因此，如果为了防止裂纹的发生而使得金属层的厚度较厚地形成，存在费用上升的问题，并且，研磨时的金属颗粒残留在密封材料之间，而可能发生绝缘电压的问题，并且，因向半导体封装施加的压力，可能发生层间剥离(delamination)现象。
并且，在涂覆用于与散热器接合的粘接剂时，在基板表面与密封材料之间未形成有阶梯差，因此，无法恒定地维持粘接剂的厚度,尤其在粘接剂的两末端的厚度，从而，降低热传送效率，而发生剥离现象。
【先行技术文献】
【专利文献】
(专利文献0001)韩国登录专利公报第10-2231769号(用于高热传导的散热器裸露型半导体封装及其制造方法,2021.04.01.公告)
(专利文献0002)韩国登录专利公报第10-1239117号(电力半导体封装及其制造方法,2013.03.06.公告)
(专利文献0003)韩国登录专利公报第10-2172689号(半导体封装及其制造方法,2020.11.02.公告)
发明内容
发明要解决的技术问题
本发明要解决的技术问题是提供一种具有阴刻形表面形状的封装外壳的半导体封装及其制造方法，可通过激光阴刻加工的止动件而能够调整用于与散热器的接合及热传送的热传送接合部件的厚度，并且，能够恒定地维持而防止剥离现象，提高热传送效率。
解决问题的技术方案
为了实现上述目的，本发明的一实施例提供一种具有阴刻形表面形状的封装外壳的半导体封装，包括：一个以上的基板，其搭载一个以上的半导体芯片；一个以上的端子引线，其与所述基板电性连接；电性连接部件，其将所述半导体芯片和所述基板或所述端子引线连接；封装外壳，其包裹所述半导体芯片、所述电性连接部件、所述一个以上的基板；一个以上的止动件，其由与所述封装外壳相同的材料形成，相比所述基板的裸露面以既定高度更高地形成，并且，在所述基板的裸露面上形成，或覆盖所述基板的裸露面的至少一部分而形成；及一个以上的散热器，其传送从所述半导体芯片的发热而进行散热，并且，所述一个以上的基板的裸露面的至少一部分在所述封装外壳的上面或下面或上下面形成，所述一个以上的基板的裸露面和所述散热器介入热传送接合部件而接合。
本发明的另一实施例一种具有阴刻形表面形状的封装外壳的半导体封装，包括：一个以上的基板，其搭载一个以上的半导体芯片；一个以上的端子引线，其与所述基板电性连接；电性连接部件，其将所述半导体芯片和所述基板或所述端子引线连接；封装外壳，其包裹所述半导体芯片、所述电性连接部件、所述一个以上的基板；一个以上的止动件，其由与所述封装外壳相同的材料形成，相比所述基板的裸露面以既定高度更高地形成，并且，未与所述基板的裸露面重叠地形成；及一个以上的散热器，其传送从所述半导体芯片的发热而进行散热，并且，所述一个以上的基板的裸露面的至少一部分在所述封装外壳的上面或下面或上下面形成，所述一个以上的基板的裸露面和所述散热器介入热传送接合部件而接合。
在此，所述基板为金属基板，或包括一个以上的绝缘层。
并且，所述止动件的高度为1μm至1mm。
并且，所述止动件以圆形、四角形及多角形中某一个以上的平面形状较高地形成。
并且，所述一个以上的止动件是使用激光将所述封装外壳的表面一部分进行阴刻加工而形成。
并且，所述一个以上的止动件的高度根据未进行阴刻加工的所述封装外壳的表面一部分决定。
并且，所述电性连接部件由Au,Ag,Al及Cu中某一个单一金属形成，或含有50重量％以上的Au,Ag,Al及Cu中某一个以上的金属的合金形成。
并且，所述电性连接部件是六面体形状或圆筒形形状的导电性隔片。
并且，所述隔片的一侧面与第1基板上的所述半导体芯片通过导电性粘接剂电性接合，所述隔片的另一侧面与第2基板通过导电性粘接剂电性接合。
并且，所述电性连接部件是在所述一个以上的半导体芯片与所述基板之间电性地连接。
并且，所述半导体芯片搭载于上部基板或下部基板上。
并且，在所述止动件的壁面形成有一个以上的球形状的颗粒，或一个以上的球形状的圆形沟。
并且，所述颗粒的直径或所述圆形沟的深度为1μm至100μm。
并且，所述散热器的一面是一个以上的金属层或一个以上的陶瓷层。
并且，在所述散热器的一面与所述一个以上的基板的裸露面之间形成的所述热传送接合部件的厚度为1μm至1mm。
并且，所述热传送接合部件的热传输率为1W/m-k至400W/m-k。
并且，所述热传送接合部件是在所述止动件、所述基板的裸露面及所述散热器的一面的内部60％以上聚集。
并且，所述一个以上的半导体芯片在下部基板的一面上通过粘接剂结构性地连接，在所述下部基板的另一面未形成有所述一个以上的止动件，所述一个以上的止动件在上部基板的一面形成，所述上部基板的另一面通过所述电性连接部件与所述半导体芯片电性连接。
并且，所述一个以上的半导体芯片在下部基板的一面上通过粘接剂结构性地连接，在所述下部基板的另一面形成有所述一个以上的止动件，所述一个以上的止动件在上部基板的一面形成，所述上部基板的另一面通过所述电性连接部件与所述半导体芯片电性连接。
本发明的又另一实施例提供一种具有阴刻形表面形状的封装外壳的半导体封装制造方法，包括如下步骤：准备要搭载一个以上的半导体芯片的下部基板和上部基板、电性连接部件及一个以上的端子引线；介入导电性粘接剂而将所述下部基板、所述上部基板、所述半导体芯片及所述电性连接部件结构性地连接；包裹所述半导体芯片、所述电性连接部件、所述下部基板及所述上部基板的贴装面整体和裸露面的至少一部分而形成封装外壳；将所述封装外壳的表面一部分使用激光进行阴刻加工，相比所述下部基板或所述上部基板的裸露面以既定高度更高地形成止动件；及所述一个以上的基板的裸露面与散热器介入热传送接合部件而接合。
在此，所述止动件的高度为1μm至1mm。
发明的效果
根据本发明，具有如下效果：可通过激光阴刻加工的止动件而能够调整用于与散热器的接合及热传送的热传送接合部件的厚度，并且，能够恒定地维持而防止剥离现象，提高热传送效率。
并且，具有如下效果：相比以往的通过磨轮的止动件结构及形成方法，能够最小化用于封装外壳的模塑的密封材料的消耗量，防止构成基板的绝缘层的陶瓷的裂纹，最小化形成有基板的裸露面的金属层的厚度，阻断在研磨时生成的金属颗粒残留在封装外壳之间而发生的绝缘电压异常，最小化向半导体封装施加的压力，而防止层间剥离。
附图说明
图1表示以往技术的半导体封装的截面结构；
图2表示本发明的具有阴刻形表面形状的封装外壳的半导体封装的截面结构；
图3表示图2的一实施例的基板上部的止动件结构；
图4表示根据图2的另一实施例的基板上部的止动件结构；
图5表示结合散热器的半导体封装的截面结构；
图6示例本发明的具有阴刻形表面形状的封装外壳的半导体封装的止动件侧面的SEM照片；
图7表示本发明的又另一实施例的具有阴刻形表面形状的封装外壳的半导体封装的制造方法。
附图符号标记
110:半导体芯片 111:粘接剂
112:粘接剂 121:下部基板
122:上部基板 123:导电性粘接剂
130:端子引线 141:隔片
142:金属线 150:封装外壳
160:止动件 161:颗粒
162:圆形沟 170:散热器
171:热传送接合部件 172:一面
173:金属冷却柱 A:裸露面
H:高度
具体实施方式
以下，参照附图更详细地说明具有上述特征的本发明的实施例。
本发明分别涉及一种具有与封装外壳150上的基板121,122的裸露面(A)重叠形成的止动件160的一实施例的具有阴刻形表面形状的封装外壳的半导体封装；具有未与基板121,122的裸露面(A)重叠形成的止动件160的另一实施例的具有阴刻形表面形状的封装外壳的半导体封装；及通过激光10的阴刻加工而形成止动件160的具有阴刻形表面形状的封装外壳的半导体封装的制造方法。
参照图2及图3，根据本发明的一实施例的具有阴刻形表面形状的封装外壳的半导体封装的要旨，包括：搭载一个以上的半导体芯片110的一个以上的基板121,122；与基板121,122电性连接的一个以上的端子引线130；将半导体芯片110与基板121,122或端子引线130连接的电性连接部件；包裹半导体芯片110和电性连接部件和一个以上的基板121,122的封装外壳150；由与封装外壳150相同的材料形成，相比基板121,122的裸露面(A)以既定高度更高地形成，位于基板121,122的裸露面(A)上或覆盖基板121,122的裸露面(A)的至少一部分而形成的一个以上的止动件160；及将从半导体芯片110的发热传送散热的一个以上的散热器170，并且，一个以上的基板121,122的裸露面(A)的至少一部分是在封装外壳150的上面或下面或上下面形成，一个以上的基板121,122的裸露面(A)与散热器170是介入热传送接合部件171而接合，恒定地维持热传送接合部件171的整体厚度。
参照图2及图4，根据本发明的另一实施例的具有阴刻形表面形状的封装外壳的半导体封装的要旨，包括：搭载一个以上的半导体芯片110的一个以上的基板121,122；与基板121,122电性连接的一个以上的端子引线130；将半导体芯片110与基板121,122或端子引线130连接的电性连接部件；包裹半导体芯片110和电性连接部件和一个以上的基板121,122的封装外壳150；由与封装外壳150相同的材料形成，相比基板121,122的裸露面(A)以既定高度更高地形成，未与基板121,122的裸露面(A)重叠地形成的一个以上的止动件160；及将从半导体芯片110的发热传送散热的一个以上的散热器170，并且，一个以上的基板121,122的裸露面(A)的至少一部分在封装外壳150的上面或下面或上下面形成，一个以上的基板121,122的裸露面(A)与散热器170是介入热传送接合部件171而接合，既定地维持热传送接合部件171的整体厚度。
首先，基板由一个以上形成，而搭载一个以上的半导体芯片110。
基板可为金属基板，或基板可包括由陶瓷形成的一个以上的绝缘层，如图2所示，可由一层以上的金属层121a,122a；在金属层121a,122a上部形成的绝缘层121b,122b；在绝缘层121b,122b上部形成，而形成金属图案的一层以上的金属层121c,122c形成的层积结构形成。
例如，基板可根据单面基板结构或两面基板结构，向封装外壳150的一面或两面裸露，由贴装半导体芯片110的下部基板121和与下部基板121分隔的上部基板122形成，并且，在半导体芯片110与上部基板122之间通过电性连接部件即隔片141以面接合方式电性连接，并且，在半导体芯片110与电性连接部件之间填充粘接剂111。
并且，半导体芯片110可搭载于下部基板121或上部基板122上，可为二极管、半导体闸流管(thyristor)、IGBT(Insulated Gate Bipolar Transistor)或MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)，尤其，适用于变换或控制电力的逆变器(inverter)或转换器(converter)或OBC(On Board Charger)等装置，而将电力变换为特定电流、特定电压或特定频率等其他电力。
然后，端子引线130由一个以上形成，而与下部基板121及/或上部基板122电性连接，并且，向封装外壳150外部裸露，而向半导体芯片110提供电性信号。
在此，端子引线130可由含有80重量％以上的Cu或含有60重量％以上的Al的金属形成。
然后，电性连接部件将半导体芯片110和基板121,122或端子引线130电性连接,由Au,Ag,Al及Cu中某一个单一金属形成，或含有50重量％以上的Au,Ag,Al及Cu中某一个以上的金属的合金形成。
例如，如图2所示，电性连接部件可为将下部基板121或上部基板122上的半导体芯片110和上部基板122或下部基板121电性连接的六面体形状或圆筒形形状的导电性隔片141，或在一个以上的半导体芯片110与基板121,122之间电性连接地，将半导体芯片110与端子引线130电性连接的金属线142或金属夹片。
在此，隔片141的一侧面与第1基板,即下部基板121上的半导体芯片110通过导电性粘接剂111电性接合，隔片141的另一侧面与第2基板,即上部基板122通过导电性粘接剂123电性接合。
然后，封装外壳150是将半导体芯片110和电性连接部件和一个以上的基板121,122包裹保护的半导体电路保护用绝缘体，其可为EMC(Epoxy Molding Compound)，但，也可为非环氧基系列的PPS(Poly Phenylene Sulfide)或PBT(Poly Butylene Terephtalate)等复合材料。
然后，一个以上的止动件160由与封装外壳150相同的材料形成，相比基板121,122的裸露面(A)以既定高度更高地形成，而调整用于与散热器170接合的热传送接合部件171的厚度，而使得热传送接合部件171的两终端的厚度恒定均匀地维持。
为此，如图7的b及c所示，在以既定高度覆盖基板121,122的封装外壳150上，使用激光10将封装外壳150的表面一部分进行阴刻加工而形成一个以上的止动件160，并且，如一实施例所示，止动件160与基板121,122的裸露面(A)重叠地形成，或如另一实施例所示，非重叠地形成。
即，图3表示图2的一实施例的基板上部的止动件结构，图4表示图2的另一实施例的基板上部的止动件结构。
更详细地，参照图3及图5，一实施例的基板121,122上部的止动件160，在基板121,122的裸露面(A)上形成，或覆盖基板121,122的裸露面(A)的至少一部分而形成，从而，使得止动件160与热传送接合部件171之间的接触面积扩大，抑制热传送接合部件171的剥离现象，提高与散热器170的接合力，并且，通过均匀的厚度的热传送接合部件171能够向散热器170均匀地热传输。
或者,参照图4及图5，根据另一实施例的基板121,122上部的止动件160，与基板121,122的裸露面(A)非重叠而形成，使得止动件160与热传送接合部件171之间的接触面积扩大，抑制热传送接合部件171的剥离现象，提高与散热器170的接合力，并且，通过均匀厚度的热传送接合部件171能够向散热器170均匀地热传输。
并且，如图3及图4所示，止动件160的高度(H)，可相同地形成1μm至1mm，并且，止动件160可以圆形、四角形及多角形中某一个以上的平面形状更高地形成。
并且，一个以上的止动件160的高度(H)根据未使用激光10进行阴刻加工的封装外壳150的表面一部分而决定。即，止动件160的高度(H)以从基板121,122的裸露面(A)至未进行阴刻加工的封装外壳150的表面一部分的高度而决定。
并且，如图5所示，一个以上的半导体芯片110在下部基板121的一面上通过粘接剂112而结构性连接，在下部基板121的另一面未形成止动件160，一个以上的止动件160在上部基板122的一面形成，上部基板122的另一面通过电性连接部件即隔片141与半导体芯片110电性连接。
或者,如图2所示，一个以上的半导体芯片110在下部基板121的一面上通过粘接剂112而结构性连接，在下部基板121的另一面形成止动件160，一个以上的止动件160在上部基板122的一面形成，上部基板122的另一面通过电性连接部件即隔片141与半导体芯片110电性连接。
并且，参照图6，在止动件160的壁面形成有一个以上的球形状的颗粒161，或者，一个以上的球形状的圆形沟162，而更加提高与热传送接合部件171的接合力，优选地，颗粒161的直径或圆形沟162的深度可为1μm至100μm。
然后，散热器170由一个以上形成，使得冷却剂循环，而传送散热从半导体芯片110的发热。
例如，在散热器170的内侧空间由冷却剂流动方向排列一个以上的金属冷却柱173，从而，通过与金属冷却柱173直接接触的冷却剂而能够有效地对半导体封装散热。
在此，如图5所示，散热器170的一面172可为一个以上的金属层或一个以上的陶瓷层，在散热器170的一面172与一个以上的基板121,122的裸露面(A)之间形成的热传送接合部件171的厚度与止动件160的高度(H)相应地形成1μm至1mm。
并且，热传送接合部件171的热传输率为1W/m-k至400W/m-k。
并且，热传送接合部件171可在止动件160、基板121,122的裸露面(A)及散热器170的一面172内部填充60％以上而聚集(trap)。
从而，一个以上的基板121,122的裸露面(A)的至少一部分在封装外壳150的上面或下面或上下面形成，一个以上的基板121,122的裸露面(A)与散热器170是介入热传送接合部件171而接合，并通过止动件160而既定地维持热传送接合部件171的整体厚度。
图7表示本发明的又另一实施例的具有阴刻形表面形状的封装外壳的半导体封装的制造方法，参照该图，本发明的又另一实施例的具有阴刻形表面形状的封装外壳的半导体封装制造方法，包括：准备要搭载一个以上的半导体芯片110的下部基板121和上部基板122,电性连接部件141,142及一个以上的端子引线130，并介入导电性粘接剂111,112,123将下部基板121、上部基板122、半导体芯片110及电性连接部件141,142结构性地连接的步骤(A)；包裹半导体芯片110、电性连接部件141,142、下部基板121及上部基板122的半导体芯片贴装面整体和裸露面(A)的至少一部分地形成封装外壳150的步骤(b)；及将封装外壳150的表面一部分使用激光10进行阴刻加工，并且，使得止动件160相比下部基板121或上部基板122的裸露面(A)以既定高度更高地形成的步骤(c)。
在此，止动件160的高度(H)可为1μm至1mm，并通过止动件160调整用于与散热器170的接合的热传送接合部件171的厚度，使得热传送接合部件171的两终端的厚度恒定均匀地维持。
并且，参照图7的d，一个以上的基板121,122的裸露面(A)与散热器170介入热传送接合部件171而接合，一个以上的基板121,122的裸露面(A)的至少一部分在封装外壳150的上面或下面或上下面形成，一个以上的基板121,122的裸露面(A)与散热器170介入热传送接合部件171而结合，从而，恒定地维持热传送接合部件171的整体厚度。
由此，通过上述的具有阴刻形表面形状的封装外壳的半导体封装及其制造方法，通过使用激光阴刻加工的止动件而能够调整用于与散热器的接合及热传送的热传送接合部件的厚度，并恒定维持，从而，能够抑制剥离现象，提高热传送效率，并且，相比以往的通过磨轮的止动件结构及形成方法，能够最小化用于封装外壳的模塑的密封材料的消耗量，防止构成基板的绝缘层的陶瓷的裂纹，最小化具有基板的裸露面的金属层的厚度，并且，能够阻断在研磨时生成的金属颗粒残留于封装外壳之间而发生的绝缘电压异常，最小化向半导体封装施加的压力，而防止层间剥离(delamination)。
本说明书上记载的实施例和附图中表示的构成只是本发明的最优选的一实施例，并非全部代言本发明的技术思想，因此，应当理解本发明的申请可存在可代替其的各种均等物和变形例。

Claims (22)

1.一种具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，包括：
一个以上的基板，其搭载一个以上的半导体芯片；
一个以上的端子引线，其与所述基板电性连接；
电性连接部件，其将所述半导体芯片和所述基板或所述端子引线连接；
封装外壳，其包裹所述半导体芯片、所述电性连接部件、所述一个以上的基板；
一个以上的止动件，其由与所述封装外壳相同的材料形成，相比所述基板的裸露面以既定高度更高地形成，并且，在所述基板的裸露面上形成，或覆盖所述基板的裸露面的至少一部分而形成；及
一个以上的散热器，其传送从所述半导体芯片的发热而进行散热，
并且，所述一个以上的基板的裸露面的至少一部分在所述封装外壳的上面或下面或上下面形成，
所述一个以上的基板的裸露面和所述散热器介入热传送接合部件而接合。
2.一种具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，包括：
一个以上的基板，其搭载一个以上的半导体芯片；
一个以上的端子引线，其与所述基板电性连接；
电性连接部件，其将所述半导体芯片和所述基板或所述端子引线连接；
封装外壳，其包裹所述半导体芯片、所述电性连接部件、所述一个以上的基板；
一个以上的止动件，其由与所述封装外壳相同的材料形成，相比所述基板的裸露面以既定高度更高地形成，并且，未与所述基板的裸露面重叠地形成；及
一个以上的散热器，其传送从所述半导体芯片的发热而进行散热，
并且，所述一个以上的基板的裸露面的至少一部分在所述封装外壳的上面或下面或上下面形成，
所述一个以上的基板的裸露面和所述散热器介入热传送接合部件而接合。
3.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述基板为金属基板，或包括一个以上的绝缘层。
4.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述止动件的高度为1μm至1mm。
5.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述止动件以圆形、四角形及多角形中某一个以上的平面形状较高地形成。
6.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述一个以上的止动件是使用激光将所述封装外壳的表面一部分进行阴刻加工而形成。
7.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述一个以上的止动件的高度根据未进行阴刻加工的所述封装外壳的表面一部分决定。
8.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述电性连接部件由Au,Ag,Al及Cu中某一个单一金属形成，或含有50重量％以上的Au,Ag,Al及Cu中某一个以上的金属的合金形成。
9.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述电性连接部件是六面体形状或圆筒形形状的导电性隔片。
10.根据权利要求9所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述隔片的一侧面与第1基板上的所述半导体芯片通过导电性粘接剂电性接合，
所述隔片的另一侧面与第2基板通过导电性粘接剂电性接合。
11.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述电性连接部件是在所述一个以上的半导体芯片与所述基板之间电性地连接。
12.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述半导体芯片搭载于上部基板或下部基板上。
13.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
在所述止动件的壁面形成有一个以上的球形状的颗粒，或一个以上的球形状的圆形沟。
14.根据权利要求13所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述颗粒的直径或所述圆形沟的深度为1μm至100μm。
15.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述散热器的一面是一个以上的金属层或一个以上的陶瓷层。
16.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
在所述散热器的一面与所述一个以上的基板的裸露面之间形成的所述热传送接合部件的厚度为1μm至1mm。
17.根据权利要求16所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述热传送接合部件的热传输率为1W/m-k至400W/m-k。
18.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述热传送接合部件是在所述止动件、所述基板的裸露面及所述散热器的一面的内部60％以上聚集。
19.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述一个以上的半导体芯片在下部基板的一面上通过粘接剂结构性地连接，在所述下部基板的另一面未形成有所述一个以上的止动件，
所述一个以上的止动件在上部基板的一面形成，所述上部基板的另一面通过所述电性连接部件与所述半导体芯片电性连接。
20.根据权利要求1或2所述的具有阴刻形表面形状的封装外壳的半导体封装，其特征在于，
所述一个以上的半导体芯片在下部基板的一面上通过粘接剂结构性地连接，在所述下部基板的另一面形成有所述一个以上的止动件，
所述一个以上的止动件在上部基板的一面形成，所述上部基板的另一面通过所述电性连接部件与所述半导体芯片电性连接。
21.一种具有阴刻形表面形状的封装外壳的半导体封装制造方法，其特征在于，包括如下步骤：
准备要搭载一个以上的半导体芯片的下部基板和上部基板、电性连接部件及一个以上的端子引线；
介入导电性粘接剂而将所述下部基板、所述上部基板、所述半导体芯片及所述电性连接部件结构性地连接；
包裹所述半导体芯片、所述电性连接部件、所述下部基板及所述上部基板的贴装面整体和裸露面的至少一部分而形成封装外壳；
将所述封装外壳的表面一部分使用激光进行阴刻加工，相比所述下部基板或所述上部基板的裸露面以既定高度更高地形成止动件；及
所述一个以上的基板的裸露面与散热器介入热传送接合部件而接合。
22.根据权利要求21所述的一种具有阴刻形表面形状的封装外壳的半导体封装制造方法，其特征在于，
所述止动件的高度为1μm至1mm。
CN202210544193.1A 2021-07-09 2022-05-19 具有阴刻形表面形状的封装外壳的半导体封装及其制造方法 Pending CN115602634A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020210090542A KR102510878B1 (ko) 2021-07-09 2021-07-09 음각형 표면 형상의 패키지 하우징 구비한 반도체 패키지
KR10-2021-0090542 2021-07-09

Publications (1)

Publication Number Publication Date
CN115602634A true CN115602634A (zh) 2023-01-13

Family

ID=84798653

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210544193.1A Pending CN115602634A (zh) 2021-07-09 2022-05-19 具有阴刻形表面形状的封装外壳的半导体封装及其制造方法

Country Status (3)

Country Link
US (1) US20230011694A1 (zh)
KR (1) KR102510878B1 (zh)
CN (1) CN115602634A (zh)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008124430A (ja) * 2006-10-18 2008-05-29 Hitachi Ltd パワー半導体モジュール
JP2008141140A (ja) * 2006-12-05 2008-06-19 Denso Corp 半導体装置
KR101239117B1 (ko) 2011-04-15 2013-03-06 (주)엔하이앤시 전력 반도체 패키지 및 그 제조방법
CN110959189A (zh) 2017-08-01 2020-04-03 株式会社村田制作所 高频模块
JP2021022603A (ja) * 2019-07-25 2021-02-18 三菱電機株式会社 半導体装置および半導体装置の製造方法
KR102231769B1 (ko) 2019-08-20 2021-04-01 제엠제코(주) 고열전도를 위한 히트싱크 노출형 반도체 패키지 및 그 제조방법
KR102172689B1 (ko) 2020-02-07 2020-11-02 제엠제코(주) 반도체 패키지 및 그 제조방법

Also Published As

Publication number Publication date
US20230011694A1 (en) 2023-01-12
KR20230009754A (ko) 2023-01-17
KR102510878B1 (ko) 2023-03-17

Similar Documents

Publication Publication Date Title
CN107946258B (zh) 具有延伸到导热电介质片外的导电层的芯片载体
US10204882B2 (en) Stacked package module having an exposed heat sink surface from the packaging
US7875970B2 (en) Integrated circuit package having a castellated heatspreader
US10727151B2 (en) Semiconductor chip package having a cooling surface and method of manufacturing a semiconductor package
US11387159B2 (en) Chip package
EP3026701B1 (en) Power module and manufacturing method thereof
CN110021590B (zh) 电源芯片集成模块、其制造方法及双面散热电源模块封装
US11056447B2 (en) Power module having at least one power semiconductor
US10418313B2 (en) Electronic module comprising a plurality of encapsulation layers and a method for producing it
US8766430B2 (en) Semiconductor modules and methods of formation thereof
US20160365296A1 (en) Electronic Devices with Increased Creepage Distances
US9437508B2 (en) Method for manufacturing semiconductor device and semiconductor device
KR102172689B1 (ko) 반도체 패키지 및 그 제조방법
US9620438B2 (en) Electronic device with heat dissipater
CN111276447B (zh) 双侧冷却功率模块及其制造方法
CN113097173A (zh) 半导体封装及其制造方法
JP2016181536A (ja) パワー半導体装置
US10937767B2 (en) Chip packaging method and device with packaged chips
KR101994727B1 (ko) 전력 모듈 패키지 및 그 제조방법
CN115312476A (zh) 具有防刮层的半导体封装及其制造方法
CN115602634A (zh) 具有阴刻形表面形状的封装外壳的半导体封装及其制造方法
CN112582386B (zh) 功率模块及其制备方法、电器设备
TWI784778B (zh) 二極體封裝結構及方法
US20220377901A1 (en) Electronic device with castellated board
JP7006015B2 (ja) 半導体モジュールの製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination