CN109712944A - 具有被部分涂覆的电源端子的功率半导体模块 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 239000004033 plastic Substances 0.000 claims abstract description 78
- 229920003023 plastic Polymers 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000000576 coating method Methods 0.000 claims abstract description 53
- 239000011248 coating agent Substances 0.000 claims abstract description 51
- 150000001875 compounds Chemical class 0.000 claims abstract description 39
- 238000004382 potting Methods 0.000 claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 22
- 239000011810 insulating material Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 18
- 239000003973 paint Substances 0.000 claims description 7
- 239000000843 powder Substances 0.000 claims description 5
- 239000002313 adhesive film Substances 0.000 claims description 3
- 239000002390 adhesive tape Substances 0.000 claims description 3
- 239000004922 lacquer Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 238000000935 solvent evaporation Methods 0.000 claims description 2
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 claims 2
- 229920001721 polyimide Polymers 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000001465 metallisation Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 229910010293 ceramic material Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000000017 hydrogel Substances 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10252—Germanium [Ge]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H01L2924/181—Encapsulation
- H01L2924/186—Material
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Abstract
本申请涉及具有被部分涂覆的电源端子的功率半导体模块。功率半导体模块包括:一个或多个功率半导体裸片,被附接到衬底的第一主面;塑料壳体,被附接到衬底,塑料壳体和衬底一起包封一个或多个功率半导体裸片;多个电源端子,在第一端处被附接到衬底的第一主面,并且在第二端处延伸穿过塑料壳体,以为一个或多个功率半导体裸片提供外部电连接点;灌封化合物,包埋一个或多个功率半导体裸片、衬底的第一主面和多个电源端子的第一端的至少一部分;和绝缘涂层,仅施加到多个电源端子的安置在塑料壳体内且只与空气接触的部分。还提供相应的制造方法。
Description
技术领域
本申请涉及功率半导体模块,尤其涉及具有被部分涂覆的电源端子的功率半导体模块。
背景技术
功率半导体模块为若干功率半导体器件提供物理容纳,功率半导体器件诸如一个或多个功率MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极晶体管)、BJT(双极结型晶体管)、晶闸管、JFET(结型场效应晶体管)、二极管等。功率半导体器件通常被制造在一个或多个半导体裸片中,所述半导体裸片被附接到功率电子衬底。塑料壳体与衬底一起包封功率半导体器件。
在功率半导体模块内,必须实现电势之间的足够隔离距离以确保适当的性能、安全性和可靠性。由于功率半导体模块的内部体积中的有限空间,自由空气在电压下没有提供部件之间的足够隔离。
通常使用软灌封隔离化合物来电绝缘所有需要电绝缘的暴露区域。功率半导体模块内的灌封化合物的填充高度直接取决于模块的内部构造。在制造功率半导体模块期间满足如塑料壳体的可制造性、可加工性和与现有生产工艺的兼容性的所有其他要求的需要通常导致灌封化合物的更高填充高度,这不利地影响模块的寿命性能。例如,灌封材料的热膨胀会在具有不同热膨胀系数的部件之间引起显著的机械相互作用,并且甚至在灌封材料自身中引起显著的热机械应力。在基于IGBT的功率半导体模块的应用条件下,灌封材料中的裂缝的传播是会导致模块的绝缘失效的真正问题。
因此,需要一种具有更可靠的电绝缘的功率半导体模块。
发明内容
根据功率半导体模块的实施例,所述功率半导体模块包括:一个或多个功率半导体裸片,被附接到衬底的第一主面;塑料壳体,被附接到衬底,所述塑料壳体和所述衬底一起包封所述一个或多个功率半导体裸片;多个电源端子,在第一端处被附接到所述衬底的第一主面,并且在第二端处延伸穿过所述塑料壳体,以为所述一个或多个功率半导体裸片提供外部电连接点;灌封化合物,包埋所述一个或多个功率半导体裸片、所述衬底的第一主面和所述多个电源端子的第一端的至少一部分;和绝缘涂层,仅施加到多个电源端子的安置在塑料壳体内且只与空气接触的部分。
根据一种制造功率半导体模块的方法的实施例,所述方法包括:将一个或多个功率半导体裸片附接到衬底的第一主面;将塑料壳体附接到所述衬底,所述塑料壳体和所述衬底一起包封所述一个或多个功率半导体裸片;在第一端处将多个电源端子附接到所述衬底的第一主面,每个电源端子在第二端处延伸穿过所述塑料壳体,以为所述一个或多个功率半导体裸片提供外部电连接;将一个或多个功率半导体裸片、所述衬底的第一主面和所述多个电源端子的第一端的至少一部分包埋在灌封化合物中;和在将所述多个电源端子附接到衬底的第一主面之前,将绝缘涂层仅施加到多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分。
在阅读以下详细描述并查看附图之后,本领域技术人员将认识到附加的特征和优点。
附图说明
附图的元素不一定相对于彼此按比例绘制。相同的附图标记表示相应的类似部分。可以组合各种所图示的实施例的特征,除非它们彼此排斥。在附图中描绘实施例,并且在后续的描述中详述实施例。
图1图示了具有被部分地涂覆有绝缘材料的电源端子的功率半导体模块的实施例的透视图。
图2图示了沿着图1中标记为A-A'的线的功率半导体模块的横截面视图。
图3图示了图1中的功率半导体模块的透视图,其中为了便于图示而未示出壳体、内部灌封化合物和一些内部电连接。
图4图示了具有被部分地涂覆有绝缘材料的电源端子的功率半导体模块的另一实施例的横截面视图。
图5图示了制造功率半导体模块的方法的实施例。
具体实施方式
本文描述的实施例提供具有被部分地涂覆有绝缘材料的电源端子的功率半导体模块,以及相应的制造方法。为了实现模块内和到外部母线的电气接触,从电源端子的那些区域省略绝缘涂层。附加地,直接接触模块中包括的灌封化合物或者由模块壳体的塑料部件电隔离的电源端子的区域也没有被涂覆有绝缘材料。这样,可以相对于模块的层厚度和物理条件来选择性地优化绝缘材料到电源端子的施加。此外,可以减小模块内部的灌封化合物的高度,降低模块内的灌封化合物的热机械损坏的可能性。
图1图示了具有被部分地涂覆有绝缘材料的电源端子的功率半导体模块的实施例的透视图。
图2图示了沿着图1中标记为A-A'的线的功率半导体模块的横截面视图。
图3图示了功率半导体模块的透视图,其中为了便于图示而未示出壳体、内部灌封化合物和一些内部电连接。
功率半导体模块包括基板100和多个衬底102,每个衬底102具有例如经由焊接、钎焊材料等附接到基板100的底部金属化侧(视图外)。基板100是导热的,并且可以是导电的或绝缘的。例如,基板100可以是金属块或陶瓷,诸如Al2O3或AlN。
每个衬底102具有相对的顶部金属化侧104,顶部金属化侧104可以包括与底部金属化侧相同或不同的材料。例如,每个衬底102可以是标准DCB(直接铜键合)、DAB(直接铝键合)、AMB(活性金属钎焊)或IMS(绝缘金属衬底)衬底。标准的DCB衬底包括施加到诸如Al2O3或AlN陶瓷材料之类的隔离材料的顶部和底部区域的铜表面。标准的DAB衬底包括施加到陶瓷材料的顶部和底部区域的铝表面。标准的AMB衬底包括钎焊到诸如AlN陶瓷材料之类的隔离材料的相对侧的金属箔。标准的IMS衬底包括直接连接到基板100的诸如聚合物之类的隔离材料。在每种情况下,每个衬底102的顶部金属化侧104可以被图案化,使得多于一个的功率半导体裸片106可以附接到顶部金属化侧104。代替多个衬底,可以将所有的功率半导体裸片106附接到单个衬底的顶部金属化侧104。
功率半导体裸片106中的至少一些裸片包括一个或多个功率半导体器件,诸如功率MOSFET、IGBT、BJT、晶闸管、JFET、二极管等。功率半导体裸片106中的其他裸片可以是无源器件,诸如电容器裸片和/或电感器裸片。功率半导体裸片106可以从任何类型的半导体材料制造,诸如单元素半导体(例如,Si、Ge等)、绝缘体上硅半导体、二元半导体(例如,SiC、GaN、GaAs等)、具有或不具有(一个或多个)外延层的三元半导体等。
功率半导体器件在模块内电连接以形成功率电路,诸如降压转换器、升压转换器、半桥、全桥、三相桥、开关模式电源、双向功率转换器、同步整流器等。形成所需功率电路的内部电连接可以由模块内部的电连接件107提供,电连接件107诸如引线键合、金属夹、金属带等。为了便于说明,大多数内部电连接未在图中示出。
功率半导体模块还包括塑料壳体108,塑料壳体108被附接到每个衬底102和/或基板100。塑料壳体108可以通过注塑或其他合适的工艺形成,并且被胶合到每个衬底102和/或基板100的外围。在一个实施例中,塑料壳体108是聚合物盖件。塑料壳体108和衬底102一起包封功率半导体裸片106。
功率半导体模块还包括多个电源端子110,多个电源端子110在第一端112处附接到至少一些衬底102的顶部主面104。电源端子110在第二端114处延伸穿过塑料壳体108,以为利用模块包封的功率半导体裸片106提供外部电连接点。电源端子110在图中被图示为金属板,但是可以被成形为类似销、柱等的形状。在金属板的情况下,每个金属板116安置在相应的电源端子110的第一端112和第二端114之间,并且在大致垂直于(一个或多个)衬底102的顶部主面106的方向上延伸。电源端子110的第二端114在图1和图2中被示出为弯曲,并且在图3中被示出在弯曲之前。电源端子110的第二端114例如在金属销和柱的情况下不需要弯曲。该模块可以包括附加端子118,诸如输入信号端子、输出信号端子等。
功率半导体模块还包括灌封化合物120,其中包埋有功率半导体裸片106、每个衬底102的顶部主面104和每个电源端子110的第一端112的至少一部分。可以使用适用于高功率半导体应用的任何标准灌封化合物,例如,诸如热固性塑料、硅凝胶等。灌封化合物120的高度由图2和图3中标记为“B”的虚线表示。根据图2和图3所图示的实施例,灌封化合物覆盖标记为“B”的虚线下方的每个端子金属板116的下部。一般来说,灌封化合物120可具有任何所需高度。灌封化合物120未在图3中示出,使得在该图示中本发明的其他方面更加明显。
功率半导体模块还包括绝缘涂层122,绝缘涂层122仅施加到安置在塑料壳体108内部并且只与空气接触的电源端子110的部分。这样,绝缘涂层122不会施加到安置在塑料壳体108外部的电源端子110的任何部分。绝缘涂层122也不会施加到安置在塑料壳体108内部并且与灌封化合物120或塑料壳体108接触的电源端子110的任何部分。
在图2和图3中图示的实施例中,每个端子金属板116的上部与塑料壳体108接触,并且每个端子金属板116的下部被包埋在灌封化合物120中。在图2和图3中标记为“C”的虚线是分界线,在该分界线之下塑料壳体108不接触端子金属板116。同样,图2和3中标记为“B”的虚线是分界线,在该分界线之上灌封化合物120不接触端子金属板116。安置在线“A”和“B”之间的端子金属板116的区域只与空气接触并因此被涂覆有绝缘材料122。绝缘涂层122不施加到与塑料壳体108接触的每个端子金属板116的上部(图2和图3中的线“C”之上),或者不施加到被包埋在灌封化合物120中的每个端子金属板116的下部(图2和图3中的线“B”之下)。此外,根据该实施例,绝缘涂层122不施加到每个电源端子110的第一端112和第二端114。
图4图示了具有被部分地涂覆有绝缘材料的电源端子的功率半导体模块的另一实施例的横截面视图。图4中所示的实施例类似于图2中所图示的实施例。然而,不同的是,灌封化合物120在到达每个电源端子110的金属板116之前终止。这样,功率半导体模块的每个端子金属板116完全未被灌封化合物120覆盖。根据该实施例,绝缘涂层122被施加到最靠近灌封化合物120的每个端子金属板116的(下部)部分,而不施加到与塑料壳体108接触的每个端子金属板116的(上部)部分。在图4中标记为“C”的虚线是分界线,在该分界线之下塑料壳体108不接触端子金属板116。同样,图4中标记为“B”的虚线是分界线,在该分界线之上灌封化合物120不接触端子金属板116。安置在图4中的线“A”和“B”之间的端子金属板116的区域只与空气接触并因此被涂覆有绝缘材料122。还考虑其他灌封化合物填充水平(高度)。
图5图示了制造图1至图4中所图示的功率半导体模块的方法的实施例。该方法包括将一个或多个功率半导体裸片附接到衬底的顶部主面(框200)。将塑料壳体附接到衬底(框202)。塑料壳体和衬底一起包封一个或多个功率半导体裸片。将多个电源端子在第一端处附接到衬底的顶部主面(框204)。每个电源端子在第二端处延伸穿过塑料壳体,以为一个或多个功率半导体裸片提供外部电连接点。将每个功率半导体裸片、衬底的顶部主面和每个电源端子的第一端的至少一部分包埋在灌封化合物中(框206)。在将电源端子附接到衬底的第一主面之前,将绝缘涂层仅施加到电源端子的将安置在塑料壳体内且只与空气接触的部分(框208)。
本文所述的选择性施加的绝缘涂层可以包括一层或多层电绝缘材料。在一个实施例中,绝缘涂层包括仅施加到电源端子的将安置在塑料壳体内且只与空气接触的部分的聚酰亚胺。
附加地或备选地,绝缘涂层包括干涂料、塑料材料或干漆。根据该实施例,该涂料、塑料材料或漆仅被施加到每个电源端子的将安置在塑料壳体内且只与空气接触的部分。然后,通过溶剂蒸发或固化工艺来干燥该涂料、塑料材料或漆。
附加地或备选地,绝缘涂层包括仅被施加到电源端子的将安置在塑料壳体内且只与空气接触的部分的粘合带或膜。
附加地或备选地,绝缘涂层通过粉末涂覆仅被施加到电源端子的将安置在塑料壳体内且只与空气接触的部分。
取决于绝缘涂层的类型,还可以使用其他涂覆方法。
在绝缘材料作为溶剂被施加并且然后被干燥的情况下,诸如涂料、塑料材料、喷涂漆等的情况下,可以在施加绝缘材料之前掩蔽电源端子的不被涂覆的部分。在施加掩模之后将绝缘材料的毯式覆盖层施加到电源端子,然后在绝缘材料施加到掩模上的情况下去除掩模。在另一实施例中,绝缘材料可以被毯式沉积在电源端子上,然后被选择性地从电源端子的将安置在塑料壳体内并与塑料壳体或灌封化合物接触的部分去除。在又一实施例中,绝缘材料可以通过转印工艺被选择性地仅施加到电源端子的将安置在塑料壳体内且只与空气接触的部分上。
在绝缘材料作为胶水或箔片被施加的情况下,诸如聚酰亚胺带之类的带或粘合膜可以仅被胶合到电源端子的将安置在塑料壳体内且只与空气接触的部分。粘合促进剂可以被用来增加绝缘涂层和电源端子之间的粘接。
在通过粉末涂覆施加绝缘材料的情况下,可以使用任何标准粉末涂覆工艺。
通常,可以转移到电源端子的表面并具有应用所需的绝缘特性的任何材料都可以被用作本文所述的绝缘涂层。
为了便于描述,使用诸如“在……下方”、“在……之下”、“下部”、“在……之上”、“上部”等的空间相对术语来解释一个元件相对于第二元件的定位。除了与图中所描绘的定向不同的定向之外,这些术语旨在涵盖器件的不同定向。此外,诸如“第一”、“第二”等术语也用于描述各种元件、区域、区段等,并且也不旨在进行限制。类似的术语在整个说明书中指代相同的元件。
如本文所用,术语“具有”、“含有”、“包括”、“包含”等是开放式术语,其指示所述元件或特征的存在,但不排除附加元件或特征。除非上下文另有明确说明,否则冠词“一”、“一个”和“该”旨在包括复数以及单数。
考虑到上述变化和应用的范围,应该理解,本发明不受前述描述的限制,也不受附图的限制。而是本发明仅受随附权利要求及其合法等同物的限制。
Claims (22)
1.一种功率半导体模块,包括:
一个或多个功率半导体裸片,被附接到衬底的第一主面;
塑料壳体,被附接到所述衬底,所述塑料壳体和所述衬底一起包封所述一个或多个功率半导体裸片;
多个电源端子,在第一端处被附接到所述衬底的第一主面,并且在第二端处延伸穿过所述塑料壳体,以为所述一个或多个功率半导体裸片提供外部电连接点;
灌封化合物,包埋所述一个或多个功率半导体裸片、所述衬底的第一主面和所述多个电源端子的第一端的至少一部分;和
绝缘涂层,仅被施加到所述多个电源端子的安置在所述塑料壳体内且只与空气接触的部分。
2.根据权利要求1所述的功率半导体模块,其中,所述灌封化合物包括热固性塑料或硅凝胶。
3.根据权利要求1所述的功率半导体模块,其中,所述绝缘涂层包括聚酰亚胺。
4.根据权利要求1所述的功率半导体模块,其中,所述绝缘涂层包括干涂料、塑料材料或干漆。
5.根据权利要求1所述的功率半导体模块,其中,所述绝缘涂层包括粘合带或膜。
6.根据权利要求1所述的功率半导体模块,其中,所述绝缘涂层包括粉末涂层。
7.根据权利要求1所述的功率半导体模块,其中,所述多个电源端子中的每个电源端子包括在所述电源端子的所述第一端和所述第二端之间的金属板,所述金属板沿大致垂直于所述衬底的第一主面的方向延伸。
8.根据权利要求7所述的功率半导体模块,其中,所述灌封化合物在到达所述多个电源端子中的每个电源端子的所述金属板之前终止,使得每个金属板完全未被所述灌封化合物覆盖。
9.根据权利要求8所述的功率半导体模块,其中,所述绝缘涂层被施加到每个金属板的最靠近所述灌封化合物的第一部分,但不施加到每个金属板的在所述第一部分之上且与所述塑料壳体接触的第二部分。
10.根据权利要求7所述的功率半导体模块,其中,所述绝缘涂层被施加到每个金属板的最靠近所述灌封化合物的第一部分,但不施加到每个金属板的在所述第一部分之上且与所述塑料壳体接触的第二部分。
11.一种制造功率半导体模块的方法,该方法包括:
将一个或多个功率半导体裸片附接到衬底的第一主面;
将塑料壳体附接到所述衬底,所述塑料壳体和所述衬底一起包封所述一个或多个功率半导体裸片;
将多个电源端子在第一端处附接到所述衬底的第一主面,每个电源端子在第二端处延伸穿过所述塑料壳体,以为所述一个或多个功率半导体裸片提供外部电连接点;
将所述一个或多个功率半导体裸片、所述衬底的第一主面和所述多个电源端子的第一端的至少一部分包埋在灌封化合物中;以及
在将所述多个电源端子附接到所述衬底的第一主面之前,将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分。
12.根据权利要求11所述的方法,其中将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分包括:
将聚酰亚胺仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的所述部分。
13.根据权利要求11所述的方法,其中,将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分包括:
将涂料、塑料材料或漆仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的所述部分;以及
通过溶剂蒸发或固化工艺来干燥所述涂料、塑料材料或漆。
14.根据权利要求11所述的方法,其中,将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分包括:
将粘合带或膜仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的所述部分。
15.根据权利要求11所述的方法,其中,将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分包括:
仅粉末涂覆所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的所述部分。
16.根据权利要求11所述的方法,其中,将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分包括:
将绝缘材料的毯式覆盖层施加到所述多个电源端子;以及
从所述多个电源端子的将安置在所述塑料壳体内且与所述塑料壳体或所述灌封化合物接触的部分中去除所述绝缘材料。
17.根据权利要求11所述的方法,其中,将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分包括:
将掩模施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的所述部分;
在施加所述掩模之后,将绝缘材料的毯式覆盖层施加到所述多个电源端子;以及
在所述绝缘材料被施加到所述掩模的情况下去除所述掩模。
18.根据权利要求11所述的方法,其中,将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分包括:
将绝缘材料仅转印到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的所述部分上。
19.根据权利要求11所述的方法,其中,所述多个电源端子中的每个电源端子包括在所述电源端子的所述第一端和所述第二端之间的金属板,所述金属板沿大致垂直于所述衬底的第一主面的方向延伸。
20.根据权利要求19所述的方法,还包括:
在所述灌封化合物到达所述多个电源端子中的每个电源端子的所述金属板之前终止所述灌封化合物,使得每个金属板完全未被所述灌封化合物覆盖。
21.根据权利要求11所述的方法,其中,将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分包括:
将所述绝缘涂层施加到每个金属板的将安置成最靠近所述灌封化合物的第一部分,而不施加到每个金属板的在所述第一部分之上且与所述塑料壳体接触的第二部分。
22.根据权利要求19所述的方法,其中,将绝缘涂层仅施加到所述多个电源端子的将安置在所述塑料壳体内且只与空气接触的部分包括:
将所述绝缘涂层施加到每个金属板的将安置成最靠近所述灌封化合物的第一部分,而不施加到每个金属板的在所述第一部分之上且与所述塑料壳体接触的第二部分。
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