CN113241330A - 耦合半导体封装 - Google Patents

耦合半导体封装 Download PDF

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Publication number
CN113241330A
CN113241330A CN202110512159.1A CN202110512159A CN113241330A CN 113241330 A CN113241330 A CN 113241330A CN 202110512159 A CN202110512159 A CN 202110512159A CN 113241330 A CN113241330 A CN 113241330A
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China
Prior art keywords
semiconductor package
substrate
substrate pads
coupled semiconductor
package
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CN202110512159.1A
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English (en)
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崔伦华
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Jmj Korea Co ltd
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Jmj Korea Co ltd
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Priority claimed from KR1020200101183A external-priority patent/KR102228938B1/ko
Application filed by Jmj Korea Co ltd filed Critical Jmj Korea Co ltd
Publication of CN113241330A publication Critical patent/CN113241330A/zh
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Abstract

本发明公开一种耦合半导体封装,包括：两个以上的基板垫(110)；在各个基板垫(110)上安装的一个以上的半导体芯片(120)；与各个基板垫(110)和各个半导体芯片(120)分别电性连接的一个以上的终端端子(130)；及覆盖一个以上的半导体芯片(120)和一个以上的终端端子(130)的一部分的封装外壳(140)，并且，一个以上的基板垫(110)的底面电性地导通，另一个以上的基板垫(110)的底面电性绝缘，从而，无需在散热设备涂覆绝缘物质，而在与散热设备的接合时形成部分的绝缘。

Description

耦合半导体封装
技术领域
本发明涉及一种一个以上的基板垫的底面电性导通，另一个以上的基板垫的底面电性绝缘，从而，无需在散热设备涂覆绝缘物质，而在与散热设备接合时能够部分地形成绝缘的耦合半导体封装。
背景技术
一般而言，封装型电力半导体装置因在驱动中发散的电力形成所需以上的高温环境，因此，重要的一点是释放热量使其以既定水准冷却而将热阻抗最小化。
并且，作为与其相关的散热结构，如图1所示例，由封装型电力半导体装置10和绝缘垫12和散热设备14构成，半导体芯片附着在金属磨带21，用密封材料20密封，通过介入绝缘垫12而附着的散热设备14发散热量。
如上述地，为了与散热设备结合，各个半导体装置要分别具备单独的绝缘垫或涂覆绝缘物质。
因此，为了改善上述的问题，需要一种以更加经济性的方法无需在散热设备上涂覆绝缘物质而在与散热设备接合时能够形成部分的绝缘的技术。
【先行技术文献】
【专利文献】
韩国登录专利公报第10-1448850号(半导体封装及其制造方法,2014.10.14)
韩国登录专利公报第10-0685253号(封装型电力半导体装置,2007.02.22.)
发明内容
发明要解决的技术问题
本发明的思想要解决的技术问题是提供一种一个以上的基板垫的底面电性导通，另一个以上的基板垫的底面电性绝缘形成，从而，无需在散热设备上涂覆绝缘物质，而在与散热设备接合时能够形成部分的绝缘的耦合半导体封装。
解决问题的技术方案
为了实现上述目的，本发明提供一种耦合半导体封装，包括：两个以上的基板垫；一个以上的半导体芯片，其在各个所述基板垫上安装；一个以上的终端端子，其与各个所述基板垫和各个所述半导体芯片分别电性连接；及封装外壳，其覆盖一个以上的所述半导体芯片和一个以上的所述终端端子的一部分，并且，一个以上的所述基板垫的底面电性导通,另一个以上的所述基板垫的底面电性绝缘。
并且，一个以上的所述基板垫的底面一部分或全部向所述封装外壳的一面外部裸露而电性导通,另一个以上的所述基板垫的底面未向所述封装外壳的外部裸露而电性绝缘。
并且，所述基板垫由导电金属形成。
并且，一个以上的所述基板垫由导电金属形成,底面一部分或全部向所述封装外壳的一面外部裸露而电性导通,另一个以上的所述基板垫由形成有绝缘层的绝缘基板形成，所述绝缘基板的底面一部分或全部向所述封装外壳的一面外部裸露而电性绝缘。
并且，所述封装外壳由EMC形成。
并且，另一个以上的所述基板垫由顺次地层积形成的一个以上的金属层和一个以上的绝缘层和一个以上的金属层形成。
并且，所述绝缘层包含陶瓷(Al2O3)、AlN或Si3N4。
并且，一个以上的所述基板垫和一个以上的所述终端端子由相同材质形成而以一体型连接形成。
并且，一个以上的所述基板垫和一个以上的所述终端端子分别分离而形成，并通过超音波熔接、焊接或激光焊接而相互接合。
并且，所述终端端子对于所述终端端子的整体重量含有40重量％以上的Al。
并且，在所述封装外壳形成有一个以上的贯通孔。
并且，在一个以上的所述基板垫形成有与一个以上的所述贯通孔对应的孔。
并且，还包括：散热设备，其借助于贯通所述贯通孔和所述孔的结合部件而结合。
并且，一个以上的所述基板垫的底面相比底面面积以90％以上裸露在所述封装外壳的一面外部。
并且，一个以上的所述半导体芯片和一个以上的所述终端端子以Au、Al或Cu单一材质形成电性连接，或以包含Au、Al及Cu中某一个以上的复合材质形成电性连接。
并且，一个以上的所述半导体芯片和一个以上的所述终端端子的电性连接通过导电金属线形成。
并且，一个以上的所述半导体芯片和一个以上的所述终端端子的电性连接通过金属夹形成。
发明的效果
根据本发明，具有如下效果：将两个以上的基板垫在单一结构的封装外壳模塑，使得一部分基板垫裸露，使得另一部分基板垫未裸露，由此，无需在散热设备涂覆绝缘物质，而在与散热设备接合时节约性地形成部分的绝缘。
并且，具有如下效果：将一部分基板垫以绝缘基板或DBC基板使用，使得两个以上的基板垫裸露，从而，无需在散热设备涂覆绝缘物质，而在与散热设备接合时节约性地形成部分的绝缘。
附图说明
图1示例以往技术的半导体封装；
图2图示本发明的耦合半导体封装的第1实施例；
图3表示图2的耦合半导体封装的分解立体图；
图4表示本发明的耦合半导体封装的第2实施例；
图5表示图4的耦合半导体封装的分解立体图；
图6表示本发明的耦合半导体封装的第3实施例；
图7及图8表示图6的耦合半导体封装的分解立体图。
附图标记说明
110:基板垫 110a,110c:金属层
110b:绝缘层 111:孔
112:绝缘层 120:半导体芯片
130:终端端子 131:第1终端端子
132:第2终端端子 140:封装外壳
具体实施方式
以下，参照附图详细说明本发明的实施例，以便本发明的所述技术领域的普通技术人员容易实施。本发明可以各种不同的形态实施，并非限定于如下说明的实施例。
本发明的耦合半导体封装的要旨为，整体上包括：两个以上的基板垫110；在各个基板垫110上安装的一个以上的半导体芯片120；与各个基板垫110和各个半导体芯片120分别电性连接的一个以上的终端端子130；及覆盖一个以上的半导体芯片120和一个以上的终端端子130的一部分的封装外壳140，并且，一个以上的基板垫110的底面电性地导通，另一个以上的基板垫110的底面电性绝缘，从而，无需在散热设备涂覆绝缘物质，而在与散热设备的接合时形成部分的绝缘。
以下，将上述构成的耦合半导体封装根据基板垫110的种类按裸露在封装外壳140外部的结构，分别详细说明第1实施例至第3实施例。
参照图2及图3，详细说明第1实施例的耦合半导体封装。
首先，基板垫110是安装半导体芯片120的引线框架，在封装外壳140内以单独垫方式模塑两个以上，一个以上的基板垫110的底面电性导通，另一个以上的基板垫110的底面电性绝缘形成。
如图2的b所示，基板垫110由导电金属形成，一个以上的基板垫110的底面裸露在封装外壳140的一面外部而电性导通，另一个以上的基板垫110的底面未向封装外壳140的外部裸露，而电性绝缘，因此，在与散热设备未图示接合时形成部分绝缘。
一个以上的基板垫110的底面一部分或全部向封装外壳140的外部裸露，并且，一个以上的基板垫110的底面与底面面积相比以90％以上裸露在封装外壳140的一面外部，从而，最大化散热效果。
因此，需要与散热设备绝缘时，也无需将另外的绝缘物质涂覆在散热设备形成绝缘,而更加单一化半导体封装的制造工艺。
半导体芯片120在各个基板垫110上介入导电粘合剂而安装一个以上。
作为参考，导电粘合剂含有40％以上的Sn,或含有50％以上的Ag或Cu，但，并非限定于此。并且，半导体芯片120可适用硅控整流器(SCR)、电力晶体管、绝缘栅双极晶体管(IGBT)、金属氧化物半导体场效应晶体管(MOSFET)、电力整流器、电力调节器、或其组合体的电力半导体。
然后，终端端子130分别与各个基板垫110和各个半导体芯片120电性连接而形成，并且，可细分化为与基板垫110电性连接的第1终端端子131和与半导体芯片120电性连接的第2终端端子132。
并且，作为向基板垫110提供电性信号的引线端子的第1终端端子131与基板垫110电性连接，并且，一个以上的基板垫110和一个以上的终端端子130由相同的材质形成，而以一体型连接形成，或一个以上的基板垫110和一个以上的终端端子130分别分离形成，并通过超音波熔接、焊接或激光焊接而相互接合。
在此，终端端子130对于终端端子130的整体重量含有40重量％以上的Al，从而，形成轻量化并提高导电性。
并且，一个以上的半导体芯片120和一个以上的终端端子130由Au、Al或Cu单一材质形成电性连接，或由Au、Al及Cu中某一个以上的复合材质形成电性连接，并且，此时的电性连接可例如为金属线。
或者,一个以上的半导体芯片120和一个以上的终端端子130的电性连接也可通过金属夹子形成，而确保电性稳定性。
然后，封装外壳140作为半导体电路保护用绝缘体，覆盖一个以上的半导体芯片120和一个以上的终端端子130的一部分，可由EMC(Epoxy Molding Compound)形成，但，并非限定于此，也可由PPS(PolyPhenylene Sulfide)或PBT(PolyButylene Terephtalate)材质形成。
并且，在封装外壳140形成有一个以上的贯通孔141，在基板垫110形成与贯通孔141对应的孔111，而与散热设备通过螺丝连接而结合。
参照图4及图5，如下详细说明第2实施例的耦合半导体封装。
首先，基板垫110作为安装半导体芯片120的引线框架，在封装外壳140内以单独垫方式模塑两个以上，并且，一个以上的基板垫110的底面电性导通，另一个以上的基板垫110的底面电性绝缘而形成。
即，如图4的b所示,一个以上的基板垫110由导电金属形成，导电金属的底面向封装外壳140的一面外部裸露而电性导通，另一个以上的基板垫110由形成绝缘层112的绝缘基板形成，绝缘基板的底面向封装外壳140的一面外部裸露而电性绝缘，从而，在与散热设备(未图示)接合时形成部分的绝缘。
一个以上的基板垫110的底面一部分或全部向封装外壳140的外力裸露，例如，一个以上的基板垫110的底面以相比底面面积90％以上向封装外壳140的一面外部裸露，而使得散热效果最大化。
从而，需要与散热设备绝缘时，也无需将另外的绝缘物质涂覆在散热设备而形成绝缘,而更加单一化半导体封装的制造工艺。
然后，半导体芯片120在各个基板垫110上介入导电粘合剂而安装一个以上。
作为参考，导电粘合剂含有40％以上的Sn,或含有50％以上的Ag或Cu，但，并非限定于此。并且，半导体芯片120可适用硅控整流器(SCR)、电力晶体管、绝缘栅双极晶体管(IGBT)、金属氧化物半导体场效应晶体管(MOSFET)、电力整流器、电力调节器、或其组合体的电力半导体。
然后，终端端子130分别与各个基板垫110和各个半导体芯片120电性连接而形成，并且，可细分化为与基板垫110电性连接的第1终端端子131和与半导体芯片120电性连接的第2终端端子132。
并且，作为向基板垫110提供电性信号的引线端子的第1终端端子131与基板垫110电性连接，并且，一个以上的基板垫110和一个以上的终端端子130由相同的材质形成，而以一体型连接形成，或一个以上的基板垫110和一个以上的终端端子130分别分离形成，并通过超音波熔接、焊接或激光焊接而相互接合。
在此，终端端子130对于终端端子130的整体重量含有40重量％以上的Al，从而，形成轻量化并提高导电性。
并且，一个以上的半导体芯片120和一个以上的终端端子130由Au、Al或Cu单一材质形成电性连接，或由Au、Al及Cu中某一个以上的复合材质形成电性连接，并且，此时的电性连接可例如为金属线。
或者,一个以上的半导体芯片120和一个以上的终端端子130的电性连接也可通过金属夹子形成，而确保电性稳定性。
然后，封装外壳140作为半导体电路保护用绝缘体，覆盖一个以上的半导体芯片120和一个以上的终端端子130的一部分，可由EMC形成，但，并非限定于此，也可由PPS或PBT材质形成。
并且，在封装外壳140形成有一个以上的贯通孔141，在基板垫110形成与贯通孔141对应的孔111，而与散热设备通过螺丝连接而结合。
参照图6至图8，如下详细说明第3实施例的耦合半导体封装。
首先，基板垫110作为安装半导体芯片120的引线框架，在封装外壳140内以单独垫方式模塑两个以上，并且，一个以上的基板垫110的底面电性导通，另一个以上的基板垫110的底面电性绝缘而形成。
即，如图6的b及图8所示,一个以上的基板垫110由导电金属形成，导电金属的底面向封装外壳140的一面外部裸露而电性导通，另一个以上的基板垫110由顺次地层积形成的金属层110a和绝缘层110b和金属层110c,例如DBC(Direct Bonded Copper)基板构成，从而，基板垫110的底面向封装外壳140的一面外部裸露而电性绝缘，在与散热设备(未图示)接合时形成部分的绝缘。
在此，绝缘层110b包括陶瓷(Al2O3)或AlN或Si3N4而形成，在金属层110a与金属层110c之间提供绝缘结构。
并且，一个以上的基板垫110的底面一部分或全部向封装外壳140的外部裸露，例如，一个以上的基板垫110的底面以相比底面面积90％以上向封装外壳140的一面外部裸露，而使得散热效果最大化。
从而，需要与散热设备绝缘时，也无需将另外的绝缘物质涂覆在散热设备而形成绝缘,而更加单一化半导体封装的制造工艺。
然后，半导体芯片120在各个基板垫110上介入导电粘合剂而安装一个以上。
作为参考，导电粘合剂含有40％以上的Sn,或含有50％以上的Ag或Cu，但，并非限定于此。并且，半导体芯片120可适用硅控整流器(SCR)、电力晶体管、绝缘栅双极晶体管(IGBT)、金属氧化物半导体场效应晶体管(MOSFET)、电力整流器、电力调节器、或其组合体的电力半导体。
然后，终端端子130分别与各个基板垫110和各个半导体芯片120电性连接而形成，并且，可细分化为与基板垫110电性连接的第1终端端子131和与半导体芯片120电性连接的第2终端端子132。
并且，作为向基板垫110提供电性信号的引线端子的第1终端端子131与基板垫110电性连接，并且，一个以上的基板垫110和一个以上的终端端子130由相同的材质形成，而以一体型连接形成，或一个以上的基板垫110和一个以上的终端端子130分别分离形成，并通过超音波熔接、焊接或激光焊接而相互接合。
在此，终端端子130对于终端端子130的整体重量含有40重量％以上的Al，从而，形成轻量化并提高导电性。
并且，一个以上的半导体芯片120和一个以上的终端端子130由Au、Al或Cu单一材质形成电性连接，或由Au、Al及Cu中某一个以上的复合材质形成电性连接，并且，此时的电性连接可例如为金属线。
或者,一个以上的半导体芯片120和一个以上的终端端子130的电性连接也可通过金属夹子形成，而确保电性稳定性。
然后，封装外壳140作为半导体电路保护用绝缘体，覆盖一个以上的半导体芯片120和一个以上的终端端子130的一部分，可由EMC形成，但，并非限定于此，也可由PPS或PBT材质形成。
并且，在封装外壳140形成有一个以上的贯通孔141，在基板垫110形成与贯通孔141对应的孔111，而与散热设备通过螺丝连接而结合。
从而，通过上述的耦合半导体封装的构成，将两个以上的基板垫在单一结构的封装外壳模塑，使得一部分基板垫裸露，使得另一部分基板垫未裸露，由此，无需在散热设备涂覆绝缘物质，而在与散热设备接合时节约性地形成部分的绝缘，并且，将一部分基板垫以绝缘基板或DBC基板使用，使得两个以上的基板垫裸露，从而，无需在散热设备涂覆绝缘物质，而在与散热设备接合时节约性地形成部分的绝缘。
以上,参照附图中图示的实施例说明了本发明。但，本发明并非限定于此，本发明的技术领域的普通技术人员可在与本发明均等的范围内进行各种变形例或其他实施例。因此，本发明的真正的保护范围应当根据权利要求范围定义。

Claims (17)

1.一种耦合半导体封装，其特征在于，包括：
两个以上的基板垫；
一个以上的半导体芯片，其在各个所述基板垫上安装；
一个以上的终端端子，其与各个所述基板垫和各个所述半导体芯片分别电性连接；及
封装外壳，其覆盖一个以上的所述半导体芯片和一个以上的所述终端端子的一部分，
并且，一个以上的所述基板垫的底面电性导通,另一个以上的所述基板垫的底面电性绝缘。
2.根据权利要求1所述的耦合半导体封装，其特征在于，
一个以上的所述基板垫的底面一部分或全部向所述封装外壳的一面外部裸露而电性导通,
另一个以上的所述基板垫的底面未向所述封装外壳的外部裸露而电性绝缘。
3.根据权利要求2所述的耦合半导体封装，其特征在于，
所述基板垫由导电金属形成。
4.根据权利要求1所述的耦合半导体封装，其特征在于，
一个以上的所述基板垫由导电金属形成,底面一部分或全部向所述封装外壳的一面外部裸露而电性导通,
另一个以上的所述基板垫由形成有绝缘层的绝缘基板形成，所述绝缘基板的底面一部分或全部向所述封装外壳的一面外部裸露而电性绝缘。
5.根据权利要求1所述的耦合半导体封装，其特征在于，
所述封装外壳由EMC形成。
6.根据权利要求1所述的耦合半导体封装，其特征在于，
另一个以上的所述基板垫由顺次地层积形成的一个以上的金属层和一个以上的绝缘层和一个以上的金属层形成。
7.根据权利要求6所述的耦合半导体封装，其特征在于，
所述绝缘层包含陶瓷(Al2O3)、AlN或Si3N4。
8.根据权利要求1所述的耦合半导体封装，其特征在于，
一个以上的所述基板垫和一个以上的所述终端端子由相同材质形成而以一体型连接形成。
9.根据权利要求1所述的耦合半导体封装，其特征在于，
一个以上的所述基板垫和一个以上的所述终端端子分别分离而形成，并通过超音波熔接、焊接或激光焊接而相互接合。
10.根据权利要求1所述的耦合半导体封装，其特征在于，
所述终端端子对于所述终端端子的整体重量含有40重量％以上的Al。
11.根据权利要求1所述的耦合半导体封装，其特征在于，
在所述封装外壳形成有一个以上的贯通孔。
12.根据权利要求11所述的耦合半导体封装，其特征在于，
在一个以上的所述基板垫形成有与一个以上的所述贯通孔对应的孔。
13.根据权利要求12所述的耦合半导体封装，其特征在于，
还包括：散热设备，其借助于贯通所述贯通孔和所述孔的结合部件而结合。
14.根据权利要求1所述的耦合半导体封装，其特征在于，
一个以上的所述基板垫的底面相比底面面积以90％以上裸露在所述封装外壳的一面外部。
15.根据权利要求1所述的耦合半导体封装，其特征在于，
一个以上的所述半导体芯片和一个以上的所述终端端子以Au、Al或Cu单一材质形成电性连接，或以包含Au、Al及Cu中某一个以上的复合材质形成电性连接。
16.根据权利要求1所述的耦合半导体封装，其特征在于，
一个以上的所述半导体芯片和一个以上的所述终端端子的电性连接通过导电金属线形成。
17.根据权利要求1所述的耦合半导体封装，其特征在于，
一个以上的所述半导体芯片和一个以上的所述终端端子的电性连接通过金属夹形成。
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