CN109841592A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109841592A
CN109841592A CN201811429595.7A CN201811429595A CN109841592A CN 109841592 A CN109841592 A CN 109841592A CN 201811429595 A CN201811429595 A CN 201811429595A CN 109841592 A CN109841592 A CN 109841592A
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China
Prior art keywords
semiconductor device
external connection
inner conductor
thin
layer
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Pending
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CN201811429595.7A
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English (en)
Inventor
榊原明徳
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Denso Corp
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Toyota Motor Corp
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Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Publication of CN109841592A publication Critical patent/CN109841592A/zh
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明是一种半导体装置。半导体装置具备:半导体元件;绝缘基板,其配置有半导体元件;以及外部连接端子,其经由绝缘基板而与半导体元件电连接。绝缘基板具有:绝缘层;内侧导体层,其位于绝缘层的一侧并与半导体元件电连接;以及外侧导体层,其位于绝缘基板的另一侧。外部连接端子沿着其长边方向具有薄壁区间和厚度比薄壁区间大的厚壁区间,且在薄壁区间与绝缘基板的内侧导体层接合。

Description

半导体装置
技术领域
本说明书公开的技术涉及半导体装置。
背景技术
国际公开第2013/005474号中公开了半导体装置。该半导体装置具备:半导体元件、配置有半导体元件的绝缘基板、以及经由绝缘基板而与半导体元件电连接的外部连接端子。绝缘基板具有绝缘层、位于绝缘层的一侧并与半导体元件电连接的内侧导体层、以及位于绝缘层的另一侧的外侧导体层。外部连接端子的一端与绝缘基板的内侧导体层接合。
当半导体装置的温度上升时,绝缘基板的内侧导体层和外部连接端子分别热膨胀。此时,由于绝缘基板的内侧导体层的热膨胀被相邻的绝缘层抑制,因此比外部连接端子的热膨胀小。其结果是,在内侧导体层与外部连接端子的接合部分,容易因热膨胀的差异而产生比较高的应力,由此,有可能导致半导体装置的耐久性降低。本说明书提供至少能够部分地解决这样的问题的技术。
发明内容
本说明书公开的半导体装置具备:半导体元件;绝缘基板,其配置有半导体元件;以及外部连接端子,其经由绝缘基板而与半导体元件电连接。绝缘基板具有:绝缘层;内侧导体层,其位于绝缘层的一侧并与半导体元件电连接;以及外侧导体层,其位于绝缘基板的另一侧。外部连接端子沿着其长边方向具有薄壁区间和厚度比薄壁区间大的厚壁区间,且在薄壁区间与绝缘基板的内侧导体层接合。
在上述半导体装置中,外部连接端子具有厚度小的薄壁区间,且在薄壁区间与绝缘基板的内侧导体层接合。由于在厚度小的薄壁区间,在外部连接端子产生的热应力被抑制,因此,能够减小在外部连接端子与内侧导体层之间的接合部分产生的应力。另一方面,外部连接端子还具有厚度大的厚壁区间,能够在厚壁区间维持与外部连接所需的强度。
附图说明
图1表示实施例1的半导体装置10的俯视图。
图2表示图1中的II-II线的剖视图。
图3表示图1中的III-III线的剖视图。
图4放大地表示第一主端子40与下侧绝缘基板30的内侧导体层34之间的接合部分。在此,图中的箭头Va表示与下侧绝缘基板30垂直的方向,平面Ha表示与下侧绝缘基板30平行的平面。
图5放大地表示第二主端子50与上侧绝缘基板20的内侧导体层24之间的接合部分。在此,图中的箭头Vb表示与上侧绝缘基板20垂直的方向,平面Hb表示与上侧绝缘基板20平行的平面。
图6放大地表示信号端子60与上侧绝缘基板20的内侧导体层24之间的接合部分。
图7表示第一主端子40的一个变形例。在该变形例中,第一主端子40的厚壁区间44的一部分和下侧绝缘基板30的绝缘层32的至少一部分位于与下侧绝缘基板30平行的同一平面Ha内。
图8表示第一主端子40的另一变形例。在该变形例中,第一主端子40的厚壁区间44的厚度沿着第一主端子40的长边方向变化。
图9表示第一主端子40的另一变形例。在该变形例中,厚壁区间44相对于薄壁区间42向上侧绝缘基板20侧突出。
具体实施方式
在本技术的一个实施方式中,也可以是,外部连接端子的厚壁区间的至少一部分和绝缘基板的内侧导体层的至少一部分位于与绝缘基板平行的同一平面内。根据这样的结构,能够一边抑制半导体装置的整体的厚度,一边使厚壁区间的厚度增大。在此,半导体装置的厚度是指与绝缘基板垂直的方向上的半导体装置的尺寸。
在本技术的一个实施方式中,也可以是,外部连接端子的厚壁区间的一部分和绝缘基板的绝缘层的至少一部分位于与所述绝缘基板平行的同一平面内。根据这样的结构,能够进一步减小半导体装置的厚度。
在本技术的一个实施方式中,也可以是,薄壁区间的厚度比绝缘基板的内侧导体层的厚度小。如上所述,内侧导体层的热膨胀被相邻的绝缘层限制。因此,若外部连接端子的薄壁区间的厚度比内侧导体层的厚度小,则能够有效地减小在外部连接端子与内侧导体层之间的接合部分产生的应力。
在本技术的一个实施方式中,也可以是,半导体装置还具备将半导体元件密封的密封件。在该情况下,可以是,外部连接端子的薄壁区间位于密封件的内部,外部连接端子的厚壁区间从薄壁区间向密封件的外部延伸。根据这样的结构,能够利用密封件来保护半导体元件。
在上述实施方式中,也可以是,绝缘基板的外侧导体层在密封件的表面露出。根据这样的结构,能够经由绝缘基板有效地将在半导体元件产生的热量向外部放出。即,绝缘基板还能够作为散热板发挥功能。
在上述实施方式中,也可以是,半导体装置还具备第二绝缘基板,该第二绝缘基板夹着半导体元件而与绝缘基板对置。在该情况下,可以是,第二绝缘基板具有:第二绝缘层、位于第二绝缘层的一侧并与半导体元件电连接的第二内侧导体层、以及位于第二绝缘层的另一侧的第二外侧导体层。并且,可以是,第二绝缘基板的第二外侧导体层在密封件的表面露出。根据这样的结构,能够经由第二绝缘基板进一步有效地将在半导体元件产生的热量向外部放出。即,能够利用第一绝缘基板和第二绝缘基板这两者从两面对半导体元件进行冷却。
在上述实施方式中,也可以是,半导体装置还具备第二外部连接端子,该第二外部连接端子经由第二绝缘基板而与半导体元件电连接。在该情况下,可以是,第二外部连接端子在其长边方向上具有薄壁区间和厚度比薄壁区间大的厚壁区间,且在薄壁区间与第二绝缘基板的第二内侧导体层接合。根据这样的结构,与上述外部连接端子同样地,能够减小在第二外部连接端子与第二内侧导体层之间的接合部分产生的应力。另外,第二外部连接端子还能够维持与外部连接所需的强度。
在上述实施方式中,可以是,第二外部连接端子的厚壁区间的至少一部分和第二绝缘基板的第二内侧导体层的至少一部分位于与第二绝缘基板平行的同一平面内。根据这样的结构,能够一边抑制半导体装置的整体的厚度,一边使厚壁区间的厚度增大。
在上述实施方式中,也可以是,第二外部连接端子的厚壁区间的一部分和第二绝缘基板的第二绝缘层的至少一部分位于与第二绝缘基板平行的同一平面内。根据这样的结构,能够进一步减小半导体装置的厚度。
在上述实施方式中,也可以是,第二外部连接端子的薄壁区间的厚度比第二绝缘基板的第二内侧导体层的厚度小。第二内侧导体层的热膨胀被相邻的第二绝缘层限制。因此,若第二外部连接端子的薄壁区间的厚度比第二内侧导体层的厚度小,则能够有效地减小在第二外部连接端子与第二内侧导体层之间的接合部分产生的应力。
在上述实施方式中,可以是,第二外部连接端子的薄壁区间位于密封件的内部,第二外部连接端子的厚壁区间从薄壁区间向密封件的外部延伸。
以下,参照附图,对本发明的代表性且非限定性的具体例进行详细说明。该详细说明单纯地旨在向本领域技术人员示出用于实施本发明的优选例的详细内容,并不意图限定本发明的范围。另外,为了提供进一步改善的半导体装置及该半导体装置的使用方法和制造方法,以下公开的追加的技术特征和技术方案能够与其他技术特征、技术方案独立地使用或一起使用。
另外,在以下的详细说明中公开的技术特征、工序的组合并不是在最广泛的意义上实施本发明时所必需的,仅是为了特别说明本发明的代表性的具体例而记载的内容。而且,在提供本发明的追加且有用的实施方式时,上述及下述的代表性的具体例的各种技术特征和在独立权利要求及从属权利要求中记载的各种技术特征并不一定需要如在此记载的具体例那样或如所列举的顺序那样进行组合。
对于在本说明书和/或权利要求书中记载的全部技术特征而言,与实施例和/或权利要求中记载技术特征的结构不同,旨在作为原始公开以及对权利要求化的特定事项的限定而单独且相互独立地进行公开。而且,全部数值范围以及关于组或组集的记载旨在作为原始公开以及对权利要求化的特定事项的限定而公开它们的中间的结构。
实施例
参照附图,对实施例的半导体装置10进行说明。半导体装置10例如能够在电动汽车中用于转换器、逆变器这样的电力转换电路。在此所说的电动汽车广义上是指具有驱动车轮的电动机的汽车,例如包括利用外部的电力进行充电的电动汽车、除了电动机之外还具有发动机的混合动力车、以及以燃料电池为电源的燃料电池车等。
如图1~图3所示,半导体装置10具备半导体元件12和将半导体元件12密封的密封件14。半导体元件12是电力电路用的所谓的功率半导体元件。半导体元件12的具体的种类、构造并不被特别限定。半导体元件12例如能够采用MOSFET(Metal-Oxide-SemiconductorField-Effect Transistor:金属氧化物半导体场效应晶体管)元件或者IGBT(InsulatedGate Bipolar Transistor:绝缘栅双极型晶体管)元件等。另外,用于半导体元件12的半导体材料也不被特别限定,例如可以是硅(Si)、碳化硅(SiC)或者氮化镓(GaN)这样的氮化物半导体。半导体元件12具有上表面电极12a、下表面电极12b及多个信号焊盘12c。上表面电极12a和下表面电极12b是电力用的电极,信号焊盘12c是信号用的电极。上表面电极12a和信号焊盘12c位于半导体元件12的上表面,下表面电极12b位于半导体元件12的下表面。
密封件14并不被特别限定,例如能够由环氧树脂这样的热固化性树脂或其他绝缘体构成。密封件14例如也被称为模制树脂或封装(日文:パッケージ)。半导体装置10不限于一个半导体元件12,也可以具备多个半导体元件。在该情况下,多个半导体元件也能够由单独的密封件14密封。另外,多个半导体元件在密封件14的内部既可以串联连接,也可以并联连接,还可以串并联连接。
半导体装置10还具备上侧绝缘基板20和下侧绝缘基板30。上侧绝缘基板20和下侧绝缘基板30夹着半导体元件12而相互对置。上侧绝缘基板20具有绝缘层22、位于绝缘层22的一侧的内侧导体层24、以及位于绝缘层22的另一侧的外侧导体层26。内侧导体层24和外侧导体层26通过绝缘层22而相互绝缘。上侧绝缘基板20的内侧导体层24在密封件14的内部与半导体元件12接合,并与半导体元件12电连接。作为一例,本实施例的内侧导体层24被分割为多个部分,各个部分被锡焊在半导体元件12的上表面电极12a或任意的信号焊盘12c上。因此,在内侧导体层24与上表面电极12a或内侧导体层24与信号焊盘12c之间,分别形成有锡焊层28。但是,上侧绝缘基板20与半导体元件12之间的接合构造并不限定于锡焊。
上侧绝缘基板20不仅与半导体元件12电连接,而且还与半导体元件12热连接。另外,上侧绝缘基板20的外侧导体层26在密封件14的表面露出,能够将半导体元件12的热量向密封件14的外部放出。由此,上侧绝缘基板20在半导体装置10中不仅构成电路的一部分,而且还能够作为散热板来发挥功能。
作为本实施例的上侧绝缘基板20,采用DBC(Direct Bonded Copper:直接敷铜)基板。绝缘层22例如由氧化铝、氮化硅、氮化铝等陶瓷构成,内侧导体层24和外侧导体层26分别由铜构成。但是,上侧绝缘基板20并不限定于DBC基板,也可以是在绝缘层22的两面接合有铝的DBA(Direct Bonded Aluminum:直接敷铝)基板。上侧绝缘基板20的具体的结构并不被特别限定。绝缘层22并不限定于陶瓷,也可以由其他绝缘体构成。内侧导体层24和外侧导体层26也并不限定于铜、铝,也可以由其他金属构成。并且,绝缘层22与各导体层24、26之间的接合构造也不被特别限定。
下侧绝缘基板30具有绝缘层32、位于绝缘层32的一侧的内侧导体层34、以及位于绝缘层32的另一侧的外侧导体层36。内侧导体层34和外侧导体层36通过绝缘层32而相互绝缘。下侧绝缘基板30的内侧导体层34与半导体元件12接合,并与半导体元件12电连接。作为一例,本实施例的内侧导体层34被锡焊在半导体元件12的下表面电极12b上,在内侧导体层34与下表面电极12b之间形成有锡焊层38。但是,下侧绝缘基板30与半导体元件12之间的接合构造并不限定于锡焊。
对于下侧绝缘基板30而言,也是不仅与半导体元件12电连接,而且还与半导体元件12热连接。并且,下侧绝缘基板30的外侧导体层36在密封件14的表面露出,能够将半导体元件12的热量向密封件14的外部放出。由此,下侧绝缘基板30也是在半导体装置10中不仅构成电路的一部分,而且还能够作为散热板来发挥功能。即,本实施例的半导体装置10具有在半导体元件12的两侧配置有散热板的两面冷却构造。
作为本实施例的下侧绝缘基板30,也采用DBC(Direct Bonded Copper:直接敷铜)基板。但是,与上述上侧绝缘基板20同样地,下侧绝缘基板30的具体的种类、结构并不被特别限定。下侧绝缘基板30的绝缘层32可以由陶瓷或其他绝缘材料构成。另外,下侧绝缘基板30的各导体层34、36可以由铜、铝或其他导体构成。并且,绝缘层32与各导体层34、36之间的接合构造也不被特别限定。
半导体装置10还具备多个外部连接端子40、50、60。作为一例,多个外部连接端子40、50、60中包括第一主端子40、第二主端子50及多个信号端子60。各个外部连接端子40、50、60由铜或铝等导体构成。外部连接端子40、50、60从密封件14的内部延伸至外部,并与外部的电路连接。在密封件14的内部,外部连接端子40、50、60经由上侧绝缘基板20或下侧绝缘基板30而与半导体元件12电连接。例如如图2所示,第一主端子40在密封件14的内部与下侧绝缘基板30的内侧导体层34接合。由此,第一主端子40经由下侧绝缘基板30的内侧导体层34而与半导体元件12的下表面电极12b电连接。此外,第一主端子40通过锡焊而与内侧导体层34接合,在第一主端子40与内侧导体层34之间形成有锡焊层48。但是,第一主端子40与内侧导体层34之间的接合并不限定于锡焊。第一主端子40与内侧导体层34之间例如既可以使用金属膏(日文:金属ペース)这样的接合材料进行接合,也可以通过焊接进行接合。
如图3所示,第二主端子50在密封件14的内部与上侧绝缘基板20的内侧导体层24接合。由此,第二主端子50经由上侧绝缘基板20的内侧导体层24而与半导体元件12的上表面电极12a电连接。此外,第二主端子50通过锡焊而与内侧导体层24接合,在第二主端子50与内侧导体层24之间形成有锡焊层58。但是,第二主端子50与内侧导体层24之间的接合并不限定于锡焊。第二主端子50与内侧导体层24之间例如既可以使用金属膏这样的接合材料进行接合,也可以通过焊接进行接合。
如图2、图3所示,各个信号端子60在密封件14的内部与上侧绝缘基板20的内侧导体层24接合。由此,各个信号端子60分别经由上侧绝缘基板20的内侧导体层24而与半导体元件12的对应的信号焊盘12c电连接。此外,信号端子60通过锡焊而与内侧导体层24接合,在信号端子60与内侧导体层24之间形成有锡焊层68。但是,信号端子60与内侧导体层24之间的接合并不限定于锡焊。信号端子60与内侧导体层24之间例如既可以使用金属膏这样的接合材料进行接合,也可以通过焊接进行接合。
在上述半导体装置10中,在其温度上升时,绝缘基板20、30的内侧导体层24、34及各个外部连接端子40、50、60分别进行热膨胀。此时,绝缘基板20、30的内侧导体层24、34的热膨胀被相邻的绝缘层22、32抑制,因此,比外部连接端子40、50、60的热膨胀小。其结果是,在内侧导体层24、34与外部连接端子40、50、60的接合部分,容易因热膨胀的差异而产生比较高的应力。其结果是,有可能导致半导体装置10的耐久性降低。
关于上述问题,如图4所示,第一主端子40沿着其长边方向具有薄壁区间42和厚度比薄壁区间42大的厚壁区间44。并且,第一主端子40在薄壁区间42与下侧绝缘基板30的内侧导体层34接合。此外,第一主端子40的薄壁区间42位于密封件14的内部,第一主端子40的厚壁区间44从薄壁区间42向密封件14的外部延伸(参照图2)。在此,第一主端子40的厚度是指与接合第一主端子40的下侧绝缘基板30垂直的方向Va上的第一主端子40的尺寸。
如上所述,第一主端子40具有厚度小的薄壁区间42,且在薄壁区间42与下侧绝缘基板30的内侧导体层34接合。由于在厚度小的薄壁区间42,在第一主端子40产生的热应力被抑制,因此,能够减小在第一主端子40与内侧导体层34之间的接合部分产生的应力。除此之外,第一主端子40还具有厚度大的厚壁区间44,因此,能够在厚壁区间44维持与外部连接所需的强度。
如图4所示,在本实施例的半导体装置10中,第一主端子40的厚壁区间44的至少一部分和下侧绝缘基板30的内侧导体层34的至少一部分位于与下侧绝缘基板30平行的同一平面Ha内。根据这样的结构,能够一边抑制半导体装置10的整体的厚度,一边使厚壁区间44的厚度增大。在此,半导体装置10的厚度是指与下侧绝缘基板30垂直的方向Va上的半导体装置10的尺寸。此外,在图4所示的例子中,薄壁区间42与厚壁区间44之间的交界部46位于与下侧绝缘基板30对置的范围内,但该交界部46也可以位于与下侧绝缘基板30对置的范围的外侧。
在本实施例的半导体装置10中,第一主端子40的薄壁区间42的厚度比下侧绝缘基板30的内侧导体层34的厚度小。如上所述,内侧导体层34的热膨胀被相邻的绝缘层32限制。因此,若第一主端子40的薄壁区间42的厚度比内侧导体层34的厚度小,则能够有效地减小在第一主端子40与内侧导体层34之间的接合部分产生的应力。
如图5所示,对于第二主端子50而言,也是沿着其长边方向具有薄壁区间52和厚度比薄壁区间52大的厚壁区间54。并且,第二主端子50在该薄壁区间52与上侧绝缘基板20的内侧导体层24接合。此外,第二主端子50的薄壁区间52位于密封件14的内部,第二主端子50的厚壁区间54从薄壁区间52向密封件14的外部延伸(参照图3)。在此,第二主端子50的厚度是指与接合第二主端子50的上侧绝缘基板20垂直的方向Vb上的第二主端子50的尺寸。此外,在图5所示的例子中,薄壁区间52与厚壁区间54之间的交界部56位于与上侧绝缘基板20对置的范围内,但该交界部56也可以位于与上侧绝缘基板20对置的范围的外侧。
如上所述,第二主端子50也具有厚度小的薄壁区间52,且在薄壁区间52与上侧绝缘基板20的内侧导体层24接合。由于在厚度小的薄壁区间52,在第二主端子50产生的热应力被抑制,因此,能够减小在第二主端子50与内侧导体层24之间的接合部分产生的应力。除此之外,第二主端子50还具有厚度大的厚壁区间54,因此,能够在厚壁区间54维持与外部连接所需的强度。
如图5所示,在本实施例的半导体装置10中,第二主端子50的厚壁区间54的至少一部分和上侧绝缘基板20的内侧导体层24的至少一部分位于与上侧绝缘基板20平行的同一平面Hb内。根据这样的结构,能够一边抑制半导体装置10的整体的厚度,一边使厚壁区间54的厚度增大。
在本实施例的半导体装置10中,第二主端子50的薄壁区间52的厚度比上侧绝缘基板20的内侧导体层24的厚度小。如上所述,内侧导体层24的热膨胀被相邻的绝缘层22限制。因此,若第二主端子50的薄壁区间52的厚度比内侧导体层24的厚度小,则能够有效地减小在第二主端子50与内侧导体层24之间的接合部分产生的应力。
如图6所示,对于信号端子60而言,也是沿着其长边方向具有薄壁区间62和厚度比薄壁区间62大的厚壁区间64。并且,信号端子60在该薄壁区间62与上侧绝缘基板20的内侧导体层24接合。此外,信号端子60的薄壁区间62位于密封件14的内部,信号端子60的厚壁区间64从薄壁区间62向密封件14的外部延伸(参照图2、图3)。在此,信号端子60的厚度是指与接合信号端子60的上侧绝缘基板20垂直的方向Vb上的信号端子60的尺寸。此外,在图6所示的例子中,薄壁区间62与厚壁区间64之间的交界部66位于与上侧绝缘基板20对置的范围内,但该交界部66也可以位于与上侧绝缘基板20对置的范围的外侧。
如上所述,信号端子60也具有厚度小的薄壁区间62,且在薄壁区间62与上侧绝缘基板20的内侧导体层24接合。由于在厚度小的薄壁区间62,在信号端子60产生的热应力被抑制,因此,能够减小在信号端子60与内侧导体层24之间的接合部分产生的应力。除此之外,信号端子60还具有厚度大的厚壁区间64,因此,能够在厚壁区间64维持与外部连接所需的强度。
如图6所示,在本实施例的半导体装置10中,信号端子60的厚壁区间64的至少一部分和上侧绝缘基板20的内侧导体层24的至少一部分位于与上侧绝缘基板20平行的同一平面Hb内。根据这样的结构,能够一边抑制半导体装置10的整体的厚度,一边使厚壁区间64的厚度增大。
在本实施例的半导体装置10中,信号端子60的薄壁区间62的厚度比上侧绝缘基板20的内侧导体层24的厚度小。如上所述,内侧导体层24的热膨胀被相邻的绝缘层22限制。因此,若信号端子60的薄壁区间62的厚度比内侧导体层24的厚度小,则能够有效地减小在信号端子60与内侧导体层24之间的接合部分产生的应力。
外部连接端子40、50、60的结构能够进行各种变更。例如,在图4所示的第一主端子40中,薄壁区间42与厚壁区间44之间的交界部46位于与下侧绝缘基板30的绝缘层32对置的范围内。与此相对,也可以如图7所示,在第一主端子40的一个变形例中,薄壁区间42与厚壁区间44之间的交界部46位于比与下侧绝缘基板30的绝缘层32对置的范围靠外侧的位置。在该情况下,也可以是,第一主端子40的厚壁区间44的一部分和下侧绝缘基板30的绝缘层32的至少一部分位于与下侧绝缘基板30平行的同一平面Ha内。根据这样的结构,能够进一步减小半导体装置10的厚度。或者,能够进一步增厚第一主端子40的厚壁区间44。该变形例的结构并不限于第一主端子40,对于第二主端子50及信号端子60这样的其他外部连接端子而言,也能够同样地采用该变形例的结构。
或者,如图8所示,在第一主端子40的另一变形例中,厚壁区间44的厚度也可以沿着长边方向阶段性地(或连续性地)变化。作为一例,在该情况下,也可以是,使厚壁区间44的厚度沿着相邻的下侧绝缘基板30的轮廓进行变化。根据这样的结构,例如能够提高第一主端子40的强度。该变形例的结构并不限于第一主端子40,对于第二主端子50及信号端子60这样的其他外部连接端子而言,也能够同样地采用该变形例的结构。
或者,如图9所示,在第一主端子40的另一变形例中,厚壁区间44相对于薄壁区间42突出的方向也可以不是接合第一主端子40的下侧绝缘基板30侧,而是与下侧绝缘基板30对置的上侧绝缘基板20侧。在该情况下,也可以是,第一主端子40的厚壁区间44的至少一部分和上侧绝缘基板20的内侧导体层24的至少一部分位于与上侧绝缘基板20平行的同一平面Hb内。根据这样的结构,也能够一边抑制半导体装置10的整体的厚度,一边使厚壁区间44的厚度增大。该变形例的结构并不限于第一主端子40,对于第二主端子50及信号端子60这样的其他外部连接端子而言,也能够同样地采用该变形例的结构。
在图9所示的变形例中,薄壁区间42与厚壁区间44之间的交界部46位于与上侧绝缘基板20的绝缘层22对置的范围内。与此相对,在又一变形例中,薄壁区间42与厚壁区间44之间的交界部46也可以位于比与上侧绝缘基板20的绝缘层22对置的范围靠外侧的位置。在该情况下,也可以是,第一主端子40的厚壁区间44的一部分和上侧绝缘基板20的绝缘层22的至少一部分位于与上侧绝缘基板20平行的同一平面Hb内。根据这样的结构,能够进一步减小半导体装置10的厚度。
在本说明书中说明的半导体装置10具备相互对置的两个绝缘基板20、30。但是,作为其他实施方式,半导体装置10既可以具备单独的绝缘基板,也可以具备三个以上的绝缘基板。另外,作为又一实施方式,半导体装置10也可以代替多个外部连接端子40、50、60,而具备单独的外部连接端子。或者,即使在半导体装置10具备多个外部连接端子40、50、60的情况下,只要多个外部连接端子40、50、60中的至少一个具有薄壁区间42和厚壁区间44即可。

Claims (12)

1.一种半导体装置,其中,所述半导体装置具备:
半导体元件;
绝缘基板,其配置有所述半导体元件;以及
外部连接端子,其经由所述绝缘基板而与所述半导体元件电连接,
所述绝缘基板具有:绝缘层;内侧导体层,其位于所述绝缘层的一侧并与所述半导体元件电连接;以及外侧导体层,其位于所述绝缘层的另一侧,
所述外部连接端子沿着其长边方向具有薄壁区间和厚度比所述薄壁区间大的厚壁区间,且在所述薄壁区间与所述绝缘基板的所述内侧导体层接合。
2.根据权利要求1所述的半导体装置,其中,
所述外部连接端子的所述厚壁区间的至少一部分和所述绝缘基板的所述内侧导体层的至少一部分位于与所述绝缘基板平行的同一平面内。
3.根据权利要求2所述的半导体装置,其中,
所述外部连接端子的所述厚壁区间的一部分和所述绝缘基板的所述绝缘层的至少一部分位于与所述绝缘基板平行的同一平面内。
4.根据权利要求1~3中任一项所述的半导体装置,其中,
所述薄壁区间的厚度比所述绝缘基板的所述内侧导体层的厚度小。
5.根据权利要求1~4中任一项所述的半导体装置,其中,
所述半导体装置还具备将所述半导体元件密封的密封件,
所述外部连接端子的所述薄壁区间位于所述密封件的内部,所述外部连接端子的所述厚壁区间从所述薄壁区间向所述密封件的外部延伸。
6.根据权利要求5所述的半导体装置,其中,
所述绝缘基板的所述外侧导体层在所述密封件的表面露出。
7.根据权利要求6所述的半导体装置,其中,
所述半导体装置还具备第二绝缘基板,所述第二绝缘基板夹着所述半导体元件而与所述绝缘基板对置,
所述第二绝缘基板具有:第二绝缘层、位于所述第二绝缘层的一侧并与所述半导体元件电连接的第二内侧导体层、以及位于所述第二绝缘层的另一侧的第二外侧导体层,
所述第二绝缘基板的所述第二外侧导体层在所述密封件的表面露出。
8.根据权利要求7所述的半导体装置,其中,
所述半导体装置还具备第二外部连接端子,所述第二外部连接端子经由所述第二绝缘基板而与所述半导体元件电连接,
所述第二外部连接端子在其长边方向上具有薄壁区间和厚度比所述薄壁区间大的厚壁区间,且在所述薄壁区间与所述第二绝缘基板的所述第二内侧导体层接合。
9.根据权利要求8所述的半导体装置,其中,
所述第二外部连接端子的所述厚壁区间的至少一部分和所述第二绝缘基板的所述第二内侧导体层的至少一部分位于与所述第二绝缘基板平行的同一平面内。
10.根据权利要求9所述的半导体装置,其中,
所述第二外部连接端子的所述厚壁区间的一部分和所述第二绝缘基板的所述第二绝缘层的至少一部分位于与所述第二绝缘基板平行的同一平面内。
11.根据权利要求8~10中任一项所述的半导体装置,其中,
所述薄壁区间的厚度比所述第二绝缘基板的所述第二内侧导体层的厚度小。
12.根据权利要求8~11中任一项所述的半导体装置,其中,
所述第二外部连接端子的所述薄壁区间位于所述密封件的内部,所述第二外部连接端子的所述厚壁区间从所述薄壁区间向所述密封件的外部延伸。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070290342A1 (en) * 2006-06-15 2007-12-20 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device
US20110037166A1 (en) * 2008-04-09 2011-02-17 Fuji Electric Systems Co., Ltd. Semiconductor device and semiconductor device manufacturing method
WO2013005474A1 (ja) * 2011-07-04 2013-01-10 本田技研工業株式会社 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004134703A (ja) 2002-10-15 2004-04-30 Toshiba Corp 端子付き回路基板
JP2012146760A (ja) 2011-01-11 2012-08-02 Calsonic Kansei Corp パワー半導体モジュール
US9697409B2 (en) * 2013-09-10 2017-07-04 Apple Inc. Biometric sensor stack structure
CN105794094B (zh) * 2013-12-04 2018-09-28 三菱电机株式会社 半导体装置
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JP7024269B2 (ja) * 2017-09-12 2022-02-24 富士電機株式会社 半導体装置、半導体装置の積層体、及び、半導体装置の積層体の搬送方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070290342A1 (en) * 2006-06-15 2007-12-20 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device
US20110037166A1 (en) * 2008-04-09 2011-02-17 Fuji Electric Systems Co., Ltd. Semiconductor device and semiconductor device manufacturing method
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