CN109830466A - 热界面材料层及包括热界面材料层的层叠封装件器件 - Google Patents

热界面材料层及包括热界面材料层的层叠封装件器件 Download PDF

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Publication number
CN109830466A
CN109830466A CN201910150160.7A CN201910150160A CN109830466A CN 109830466 A CN109830466 A CN 109830466A CN 201910150160 A CN201910150160 A CN 201910150160A CN 109830466 A CN109830466 A CN 109830466A
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material layer
interface material
thermal interface
package
packaging part
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CN201910150160.7A
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CN109830466B (zh
Inventor
罗珉玉
金钟局
柳孝昌
朴镇右
孙凤辰
李章雨
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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Abstract

提供了一种热界面材料层和包括该热界面材料层的层叠封装件器件。层叠封装件器件可包括设置在上半导体封装件和下半导体封装件之间并被构造为具有特定的物理性质的热界面材料层。因此，在执行焊料球焊接工艺来将上半导体封装件安装在下半导体封装件时，能够防止在下半导体芯片中出现开裂。

Description

热界面材料层及包括热界面材料层的层叠封装件器件
本申请是基于2013年8月12日提交的、申请号为2013800788244、发明创造名称为“热界面材料层及包括热界面材料层的层叠封装件器件”的中国专利申请的分案申请。
技术领域
本发明构思的示例实施例涉及一种热界面材料层及包括该热界面材料层的层叠封装件器件。
背景技术
随着电子工业的成熟，高性能、高速度和紧凑的电子系统的需求日见增加。已经提出了各种半导体封装技术来满足这种需求。例如，半导体封装件器件可以被构造为包括安装在封装件基底上的多个半导体芯片，或者具有层叠封装件(PoP)结构。由于PoP器件的每个封装件具有半导体芯片和封装件基底，所以PoP器件的厚度大，导致各种技术问题。另外，对于PoP器件，难以将半导体芯片中产生的热排到外部，因此，PoP器件具有诸如器件故障或运行速度降低的技术问题。
发明内容
技术问题
本发明构思的示例实施例提供一种防止在下半导体芯片中出现开裂问题的热界面材料层，所述下半导体芯片可包括在层叠封装件器件的下半导体封装件中。
本发明构思的其他示例实施例提供一种包括该热界面材料层的层叠封装件器件。
问题的解决方案
根据本发明构思的示例实施例，一种热界面材料层可以设置在下半导体封装件和上半导体封装件之间，其中，热界面材料层的弹性模量为500kPa或更低。
在示例实施例中，热界面材料层具有小于7的莫氏硬度。热界面材料层的导热率为1W/mK或更高。
在示例实施例中，热界面材料层可包括树脂层和分散在树脂层中的填料颗粒，树脂层的弹性模量为500kPa或更低。树脂层可由硅基化合物或橡胶基化合物形成。
在示例实施例中，填料颗粒具有小于7的莫氏硬度。
在示例实施例中，填料颗粒可被构造为表现出绝缘性质。
在示例实施例中，填料颗粒可以是氮化硼颗粒和氧化锌颗粒中的至少一种。
在其他实施例中，填料颗粒中的至少一个可以包括涂覆有绝缘层的金属颗粒，金属颗粒具有小于7的莫氏硬度。例如，填料颗粒中的至少一个可以是涂覆有氧化铝的铝颗粒。
在示例实施例中，热界面材料层中的填料颗粒的含量范围为60wt％至95wt％。
根据本发明构思的另一示例实施例，一种热界面材料层可以设置在顺序地堆叠的下半导体封装件和上半导体封装件之间，并且可被构造为具有小于7的莫氏硬度。
根据本发明构思的另一示例实施例，一种层叠封装件器件可包括：下半导体封装件，包括下封装件基底和安装在下封装件基底上的下半导体芯片；上半导体封装件，包括设置在下半导体封装件上的上封装件基底和安装在上封装件基底上的上半导体芯片；以及第一热界面材料层，设置在下半导体芯片和上封装件基底之间。这里，第一热界面材料层的弹性模量为500kPa或更低。
在示例实施例中，第一热界面材料层的莫氏硬度可以小于下半导体芯片的莫氏硬度。
在示例实施例中，第一热界面材料层可以与下半导体芯片的顶表面接触。在其他实施例中，下半导体封装件还可包括覆盖下半导体芯片的顶表面的下成型层，第一热界面材料层可以与下成型层的顶表面接触。
在示例实施例中，器件还可包括设置在下半导体封装件和上半导体封装件之间的插入基底。这里，第一热界面材料层可以设置在下半导体封装件与插入基底之间，并且可以在上半导体封装件与插入基底之间。
在示例实施例中，器件还可包括：第二热界面材料层，设置在上半导体封装件上；以及散热板，设置在第二热界面材料层上。这里，第二热界面材料层的物理性质与第一热界面材料层的物理性质不同。
根据本发明构思的又一示例实施例，层叠封装件器件可以包括：下半导体封装件，包括下封装件基底和安装在下封装件基底上的下半导体芯片；上半导体封装件，包括设置在下半导体封装件上的上封装件基底和安装在上封装件基底上的上半导体芯片；以及第一热界面材料层，设置在下半导体芯片和上封装件基底之间。第一热界面材料层具有小于7的莫氏硬度。
发明的有益效果
根据本发明构思的示例实施例，可以在层叠封装件器件的下半导体封装件和上半导体封装件之间设置热界面材料层，并且热界面材料层可被构造为具有特定的物理性质(例如，低于7的莫氏硬度和/或500kPa或更低的弹性模量)。因此，当执行焊料球焊接工艺来将上半导体封装件安装在下半导体封装件上时，能够防止在下半导体芯片中出现开裂。结果，能够减少层叠封装件器件的失效并且提高层叠封装件器件的良率。
另外，由于热界面材料层被添加在下半导体封装件和上半导体封装件之间，所以能够将下半导体芯片中产生的热快速地排放到上半导体封装件。结果，能够减少层叠封装件器件的故障并提高层叠封装件器件的运行速度。
附图说明
通过下面结合附图进行的简要描述，示例实施例将被更清楚地理解。如这里描述的，附图给出了非限制性的示例实施例。
图1是示出根据本发明构思的示例实施例1的层叠封装件器件的示例的剖视图。
图2是示出图1的层叠封装件器件中的热传递过程的图。
图3A至图3C是示例性地示出根据本发明构思的示例实施例的热界面材料层的剖视图。
图4至图7是示出制造图1的层叠封装件器件的工艺的剖视图。
图8是示出用于第一实验示例的电路构造的示意图，其中，测试了根据本发明构思的示例实施例的热界面材料层的绝缘性质。
图9A至图9C是示意性地示出作为本发明构思的第一实验示例的一部分的被执行为检查在半导体芯片中是否形成开裂的测试工艺的透视图。
图10是示意性地示出作为本发明构思的第一实验示例的一部分的被执行为检查在半导体芯片中是否产生了划痕的测试工艺的透视图。
图11是示出第三实验示例的结果的曲线图。
图12是示出根据本发明构思的示例实施例2的层叠封装件器件的示例的剖视图。
图13和图14是示出根据本发明构思的示例实施例3的层叠封装件器件的示例的剖视图。
图15是示出根据本发明构思的示例实施例4的层叠封装件器件的示例的剖视图。
图16是示出根据本发明构思的示例实施例5的层叠封装件器件的示例的剖视图。
图17是示出根据本发明构思的示例实施例6的层叠封装件器件的示例的剖视图。
图18是示出根据本发明构思的示例实施例7的层叠封装件器件的示例的剖视图。
图19是示出根据本发明构思的示例实施例的包括半导体封装件的封装模块的示例的图。
图20是示出根据本发明构思的示例实施例的包括半导体封装件的电子系统的示例的示意性框图。
图21是示出根据本发明构思的示例实施例的包括半导体封装件的存储系统的示例的示意性框图。
应当注意的是，这些附图意图示出在特定的示例实施例中使用的方法、结构和/或材料的一般特性，并且意图补充下面提供的说明书。然而，这些附图不是按比例的，并且可以不精确地反映任何给出的实施例的精确结构性或性能特性，并且不应被解释为限定或限制示例实施例所包括的值或性质的范围。例如，为了清楚起见，可以减小或夸大模块、层、区域和/或结构性元件的相对厚度和位置。在不同的附图中使用相似或相同的标号意图表示存在相似或相同的元件或特征。
具体实施方式
现在将参照附图更充分地描述本发明构思的示例实施例，在附图中示出了示例实施例。然而，本发明构思的示例实施例可以以许多不同的形式实施，而不应当被解释为局限于在这里阐述的实施例；相反，提供这些实施例使得本公开将是彻底的和完整的，并将把示例实施例的构思充分地传达给本领域普通技术人员。在附图中，为了清楚起见，夸大了层和区域的厚度。同样的标号在附图中表示同样的元件，因此将省略对它们的描述。
将理解的是，当元件被称作‘连接’或‘结合’到另一元件时，该元件可以直接连接到或直接结合到所述另一元件，或者可以存在中间元件。相反，当元件被称作‘直接连接’或‘直接结合’到另一元件时，不存在中间元件。同样的数字始终指示同样的元件。如在这里使用的，术语‘和/或’包括一个或多个相关所列项的任意组合和全部组合。用来描述元件之间或层之间的关系的其他词语应当以相似的方式进行解释(例如，‘在……之间’与‘直接在……之间’、‘与……相邻’与‘与……直接相邻’、‘在……上’与‘直接在……上’)。
应该理解的是，虽然在这里可以使用术语‘第一’、‘第二’等来描述不同的元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应受这些术语的限制。这些术语仅用于将一个元件、组件、区域、层或部分与另一元件、组件、区域、层或部分区分开来。因此，在不脱离示例实施例的教导的情况下，下面讨论的第一元件、组件、区域、层或部分可以被命名为第二元件、区间、区域、层或部分。
为了方便描述，在这里可使用空间相对术语，如‘在…之下’、‘在…下方’、‘下面的’、‘在…上方’、‘上面的’等，来描述如图中所示的一个元件或特征与另一元件或特征的关系。将理解的是，空间相对术语意在包含除了在附图中描述的方位之外的装置在使用或操作中的不同方位。例如，如果在附图中的装置被翻转，则描述为‘在’其他元件或特征‘下方’或‘之下’的元件随后将被定位为‘在’其他元件或特征‘上方’。因此，示例性术语‘在…下方’可包括‘在…上方’和‘在…下方’两种方位。所述装置可被另外定位(旋转90度或者在其他方位)，并对在这里使用的空间相对描述符做出相应的解释。
这里使用的术语仅为了描述特定实施例的目的，而不意图限制示例实施例。如这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式。还将理解的是，如果在本说明书中使用术语‘包含’和/或‘包括’，则说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组。
在此参照作为示例实施例的理想实施例(和中间结构)的示意图的剖视图来描述本发明构思的示例实施例。这样，预计会出现例如由制造技术和/或公差引起的图示的形状的变化。因此，本发明构思的示例实施例不应该被解释为局限于在此示出的区域的特定形状，而将包括例如由制造导致的形状偏差。例如，示出为矩形的注入区域在其边缘可以具有圆形或弯曲的特征和/或注入浓度的梯度，而不是从注入区域到非注入区域的二元变化。同样，通过注入形成的埋区会导致在埋区和通过其发生注入的表面之间的区域中的一些注入。因此，在图中示出的区域实际上是示意性的，它们的形状并不意图示出装置的区域的实际形状，也不意图限制示例实施例的范围。
除非另有定义，否则这里使用的所有术语(包括技术术语和科学术语)具有与本发明构思的示例实施例所属领域的普通技术人员所通常理解的意思相同的意思。还将理解的是，除非这里明确这样定义，否则术语(例如在通用的字典中定义的那些术语)应该被解释为具有与相关领域的环境中它们的意思一致的意思，而不将理想的或者过于正式的含义来解释它们的意思。
[实施例1]
图1是示出根据本发明构思的示例实施例1的层叠封装件器件的示例的剖视图。图2是示出图1的层叠封装件器件中的热传递过程的图。图3A至图3C是示例性地示出根据本发明构思的示例实施例的热界面材料层的剖视图。
参照图1，根据本实施例1的层叠封装件器件200可包括下半导体封装件101和上半导体封装件102。
下半导体封装件101可以包括下封装件基底1、安装在下封装件基底1上的下半导体芯片10和覆盖它们的下成型层12。下半导体芯片10可以以倒装芯片键合的方式利用第一下焊料凸起5电连接到下封装件基底1。第二下焊料凸起16可以设置在下封装件基底1下方。下成型层12可以覆盖下半导体芯片10的侧壁，并且暴露下半导体芯片10的顶表面。换言之，下半导体芯片10的顶表面可以不被下成型层12覆盖。下成型层12可被设置为具有与下半导体芯片10分开地形成的连接孔14。下半导体芯片10可以是例如逻辑芯片。下半导体芯片10可以包括多个电子器件，例如，中央处理器单元(CPU)、图形处理器单元(GPU)和/或通用串行总线(USB)。
上半导体封装件102可以包括上封装件基底30、安装在上封装件基底30上的上半导体芯片40a和40b以及覆盖它们的上成型层36。上半导体芯片40a和40b可以包括第一上半导体芯片40a和第二上半导体芯片40b。上半导体芯片40a和40b可以以引线键合的方式安装在上封装件基底30上。上半导体芯片40a和40b可以是例如存储芯片。
上半导体封装件102可以堆叠在下半导体封装件101上。在示例实施例中，下半导体封装件101和上半导体封装件102可以通过连接焊料凸起38彼此电连接。连接焊料凸起38可以分别设置在连接孔14中。
热界面材料层50可以设置在下半导体芯片10和上封装件基底30之间。热界面材料层50可以既与下半导体芯片10的顶表面接触又与上封装件基底30的底表面接触。
在层叠封装件器件200中，热界面材料层50可以设置在下半导体芯片10和上封装件基底30之间，其中，下半导体芯片10可以是逻辑芯片或者主要热源。如果下半导体芯片10与上封装件基底30分开而没有热界面材料层50，则它们之间的空间可能填充有空气。由于诸如空气的气体材料的导热率远小于固体材料的导热率，所以在未设置热界面材料层50时，在使从下半导体芯片10产生的热消散或排放方面会存在困难。相反，根据本发明构思的示例实施例，能够通过热界面材料层50有效地将从下半导体芯片10产生的热传递到上半导体封装件102(如图2中的箭头所指示)，从而使热排放到外部。这使得能够提高器件的运行速度并减少故障的问题。另外，这使得能够推迟动态热管理(DTM)的开始时间，从而提高中央处理单元的使用效率。
同时，当上半导体封装件102安装在下半导体封装件101上时，来自上半导体封装件102的压力可能被施加到下半导体封装件101。这里，如果在它们之间设置热界面材料层50，则与不存在热界面材料层50的情况相比，下半导体芯片10可以经受更大的冲击。结果，下半导体芯片10可能开裂。为了避免这种开裂问题，可将热界面材料层50构造为具有特定的物理性质。
例如，热界面材料层50可具有500kPa或更低的弹性模量。由于低弹性模量为500kPa或更低，所以当与将具有高弹性模量的材料用于热界面材料层50的情形相比时，热界面材料层50可以较软，并且更有效地吸收冲击。因此，在将上半导体封装件102安装在下半导体封装件101上时，能够防止在下半导体芯片10中出现开裂的问题。
热界面材料层50的莫氏硬度可以小于下半导体芯片10的莫氏硬度。例如，热界面材料层50可具有小于7的莫氏硬度。由于低莫氏硬度小于7，所以当与将莫氏硬度高于7的材料用于热界面材料层的情况相比时，热界面材料层50可以更软，并且更有效地吸收冲击。因此，在将上半导体封装件102安装在下半导体封装件101上时，能够防止在下半导体芯片10中出现开裂的问题。
热界面材料层50可具有1W/mK或更高的导热率。这使得能够将下半导体芯片10中产生的热快速地排放到上半导体封装件102。结果，在下半导体芯片10的中央处理器单元中，能够减少频率损失和故障的问题，并且能够提高运行速度。
热界面材料层50可由绝缘材料形成。因此，即使当热界面材料层50和与其相邻地设置的连接焊料凸起38接触时，也能够防止在连接焊料凸起38之间出现电短路。
在示例实施例中，如图3A中所示，热界面材料层50可包括树脂层51和分散在树脂层51中的填料颗粒53和57。热界面材料层50的弹性模量可以与树脂层51的弹性模量高度相关。例如，热界面材料层50的弹性模量可以与树脂层51的弹性模量基本相等。热界面材料层50的莫氏硬度可以与树脂层51的莫氏硬度高度相关。例如，热界面材料层50的莫氏硬度可以与树脂层51的莫氏硬度基本相等。
树脂层51的弹性模量可以是500kPa或更低。树脂层51可以是硅基化合物或橡胶基化合物，或者树脂层51可以包括硅基化合物或橡胶基化合物。树脂层51的弹性模量可以根据其中的组分以及构成物的含量而改变。根据本发明构思的示例实施例，热界面材料层50可以包括弹性模量为500kPa或更低的硅基化合物或橡胶基化合物。
填料颗粒53和57的莫氏硬度可以低于下半导体芯片10的莫氏硬度。例如，填料颗粒53和57的莫氏硬度可以低于7。填料颗粒53和57可由绝缘材料形成。填料颗粒53和57可包括第一填料颗粒53和第二填料颗粒57。第一填料颗粒53可由莫氏硬度为大约2的氮化硼和/或莫氏硬度为大约4-5的氧化锌制成。每个第二填料颗粒57可包括金属颗粒55和覆盖金属颗粒55的绝缘层56。这里，金属颗粒55可具有小于7的莫氏硬度。绝缘层56可具有几十纳米至几百纳米的厚度。金属颗粒55可具有大约几微米至几百微米的直径。在示例实施例中，绝缘层56可由氧化铝制成，金属颗粒55可由铝制成。绝缘层56可使第二填料颗粒57表现出绝缘性质。由于绝缘层56的厚度比金属颗粒55的直径相对小得多，所以第二填料颗粒57的莫氏硬度可以不因绝缘层56的存在而受到实质性影响。换言之，第二填料颗粒57的莫氏硬度可以与金属颗粒55的莫氏硬度基本相等。在示例实施例中，金属颗粒55可具有大约3的莫氏硬度。
如上所述，在填料颗粒53和57的莫氏硬度小于7并且树脂层50的弹性模量为500kPa或更低的情况下，能够实现莫氏硬度小于7并且弹性模量为500kPa或更低的热界面材料层50。
在示例实施例中，填料颗粒53和57可被设置为在热界面材料层50中具有大约60-95wt％。结果，热界面材料层50可被构造为具有1W/mK或更高的导热率。
图3A示出了包括第一填料颗粒53和第二填料颗粒57的树脂层51。然而，本发明构思的示例实施例可以不限于此。例如，如图3B中所示，可以仅将第一填料颗粒53分散在树脂层51中，或者如图3C中所示，可以仅将第二填料颗粒57分散在树脂层51中。
图4至图7是示出制造图1的层叠封装件的工艺的剖视图。
参照图4，可将下半导体芯片10以倒装芯片键合的方式利用第一下焊料凸起5安装到下封装件基底1上。然后，可执行成型工艺，以形成覆盖下半导体芯片10的下成型层12。
参照图5，可执行抛光工艺，以至少部分地去除下成型层12的上部，从而暴露下半导体芯片10的顶表面。在示例实施例中，下半导体芯片10的顶部可以在抛光工艺中被部分地去除，因此，下半导体芯片10可被形成为具有期望的厚度。
可选地，在不进行额外的抛光工艺的情况下，可以以这样的方式来执行成型工艺，使得下半导体芯片10的顶表面被下成型层12暴露。
参照图6，可将第二下焊料凸起16附着到下封装件基底1的底表面上。可利用例如激光在下成型层12中形成连接孔14。然后，可在下封装件基底1的通过连接孔14暴露的一些部分上形成下连接焊料凸起38b。因此，可形成下半导体封装件101。
参照图7，第一上半导体芯片40a和第二上半导体芯片40b可以顺序地堆叠在上封装件基底30上，并且利用引线32电连接到上封装件基底30。可执行成型工艺来形成覆盖上半导体芯片40a和40b的上成型层36。可将上连接焊料凸起38a附着到上封装件基底30的底表面上。
然后，可在下半导体芯片10的顶表面涂覆热界面材料组合物50s。热界面材料组合物50s可被设置为包含其中分散有参照图3A至图3C描述的填料颗粒53和57的树脂溶液。上半导体封装件102可以设置在下半导体芯片10上。然后，可将上连接焊料凸起38a分别插入到连接孔14中。可将获得的结构加热至连接焊料凸起38a和38b的熔点，因此，可将上连接焊料凸起38a和下连接焊料凸起38b彼此焊接。在该过程中，热界面材料组合物50s中的溶剂可以挥发，结果，可形成图1的热界面材料层50。
在上述工艺中，来自上半导体封装件102的压力可被施加于下半导体芯片10。如果热界面材料层50的弹性模量和莫氏硬度不在如上所述的合适的范围内，则下半导体芯片10可能开裂或损坏。相反，根据本发明构思的示例实施例，由于热界面材料层50的弹性模量为500kPa或更小和/或莫氏硬度小于7，所以可保护下半导体芯片10免于开裂或损坏。
然后，可使层叠封装件器件200冷却。然后，可执行测试工艺，以检查层叠封装件器件200中是否存在失效。在该测试工艺中，可通过测试插槽来向下推层叠封装件器件200。这里，如果热界面材料层50的弹性模量和莫氏硬度不在合适的范围内，则下半导体芯片10可能开裂或损坏。相反，根据本发明构思的示例实施例，由于热界面材料层50的弹性模量为500kPa或更小和/或莫氏硬度小于7，所以可保护下半导体芯片10免于开裂或损坏。
将在下面描述本发明构思的实验示例。
[第一实验示例]
在第一实验示例中，测试热界面材料层165，以了解它们的绝缘性质、开裂性质和划痕性质与其中包含的填料颗粒的类型之间的关系。在第一实验示例中，使用涂覆有氧化铝的铝颗粒(涂覆有Al2O3的Al)、氧化锌(ZnO)、氧化铝(Al2O3)、氧化硅(SiO2)和银(Ag)作为填料颗粒。对于树脂层，通常使用基于硅的材料。
(1)热界面材料层的绝缘性能
图8是示出用于第一实验示例的电路构造的示意图，其中，测试根据本发明构思的示例实施例的热界面材料层的绝缘性能。
参照图8，在基底161上将导电图案163形成为彼此分开。导电图案163之间的距离D1为80μm。导电图案163被热界面材料层165覆盖。在85℃的温度以及85％的湿度下将45V的电压施加到导电图案163之间。然后，测量导电图案163之间的电阻以作为时间的函数。只要改变热界面材料层165中的填料颗粒的类型，就重复上述过程。
在将涂覆有Al2O3的Al颗粒用作填料颗粒的情况下，在表1中示出了测量的电阻。
【表1】
经历的时间(hour) 0 150 300
电阻(Ω) 4×10<sup>9</sup> 3×10<sup>10</sup> 4×10<sup>10</sup>
如表1中所示，即使经过了300个小时，也保持了大约1010Ω的极高的电阻。即，导电图案163彼此电隔离。结果，可以说，如果将涂覆有Al2O3的Al颗粒用作填料颗粒，则热界面材料层165可以表现出良好的绝缘特性。
(2)半导体芯片的开裂特性
图9A至图9C是示意性地示出作为本发明构思的第一实验示例的一部分的被执行为检查在半导体芯片中是否形成开裂的测试工艺的透视图。
参照图9A，将热界面材料层165设置在半导体芯片161a和161b之间，半导体芯片161a和161b中的每个被制造为具有大约10mm×10mm的面积。如图9B中所示，在室温下使用夹具170来将200psi的压力施加到获得的结构达10分钟，结果，使半导体芯片161a和161b之间的热界面材料层165的厚度减小至大约20μm。如图9C中所示，将获得的结构装载到炉子172中，然后，在150℃的温度对获得的结构执行固化工艺大约120分钟。然后，卸载半导体芯片161a和161b并检查。
(3)半导体芯片的划痕特性
图10是示意性地示出作为本发明构思的第一实验示例的一部分的被执行为检查在半导体芯片中是否产生了划痕的测试工艺的透视图。
参照图10，将热界面材料层165像图9A中所示那样设置在半导体芯片161a和161b之间，然后，将半导体芯片中的上面的那个半导体芯片(例如161b)从一侧至另一侧移动二十次。然后，将半导体芯片161a和161b分开以视觉地检查它们的与热界面材料层165接触的表面。
将通过三个测试过程获得的结果总结到下面的表2中。
【表2】
如表2中所示，在将热界面材料层构造为包括莫氏硬度小于7的填料颗粒情况下，未出现半导体芯片的开裂或表面划痕。然而，银(Ag)具有好的莫氏硬度特性(即，2.4)，但是其并未涂覆有绝缘层，从而表现出差的绝缘性能。换言之，银不适于用作热界面材料层的填料颗粒。根据表2，可以说，对于填料颗粒需要小于7的莫氏硬度和绝缘特性。另外，鉴于热界面材料层的莫氏硬度与填料颗粒的莫氏硬度高度相关，因此可以说，对于热界面材料层需要小于7的莫氏硬度。
[第二实验示例]
在第二实验示例中，检查设置在下半导体封装件和上半导体封装件之间的热界面材料层的弹性模量与层叠封装件器件的良率之间的关系。在第二实验示例中，通过执行参照图4至图7描述的工艺步骤来形成图1的层叠封装件器件。如在下面的表3中所示，层叠封装件器件200被构造为包括具有范围在50kPa至120MPa的弹性模量的热界面材料层，然后，检查其良率。通过改变热界面材料层的树脂层的构成、组分和/或含量来实现热界面材料层的弹性模量的变化。在下面的表3中，100％的良率表示不存在与下半导体芯片的开裂相关的问题，0％的良率表示失效的器件的比例为100％。
【表3】
如表3中所示，当热界面材料层的弹性模量为500kPa或更低时，良率为100％。这表明下半导体封装件与上半导体封装件之间的热界面材料层应当具有500kPa或更低的弹性模量。
[第三实验示例]
在第三实验示例中，检查层叠封装件器件，以了解层叠封装件器件的热阻减小率与下半导体封装件和上半导体封装件之间的热界面材料层的导热率之间的关系。结果总结在下面的表4中。通过改变包含在热界面材料层中的填料颗粒的含量来实现热界面材料层的导热率的变化。在不同的位置测量层叠封装件器件的温度，并通过计算来计算热阻减小率。高的热阻减小率表示层叠封装件器件的热阻可以容易减小，并且因此能够有效地排出热。
【表4】
在图11中的曲线图中示出了表4的结果。
根据图11的曲线图，在导热率为1W/mK或更高的情况下，热阻减小率的变化减小并且饱和为具有大约10的值。换言之，在下半导体封装件和上半导体封装件之间的热界面材料层的导热率为1W/mK或更高的情况下，热阻减小率基本相同。根据该结果，优选地，热界面材料层具有1W/mK或更高的导热率。
实验示例示出了可以设置在下半导体封装件和上半导体封装件之间的热界面材料层优选地具有上面描述的物理特性或值。
[实施例2]
图12是示出根据本发明构思的示例实施例2的层叠封装件器件的示例的剖视图。
参照图12，根据本实施例，在层叠封装件器件201的下半导体封装件101a中，下半导体芯片10的顶表面可被下成型层12覆盖。热界面材料层50可以与下半导体芯片10分开，并与下成型层12的顶表面以及上封装件基底20的底表面接触。虽然热界面材料层50与下半导体芯片10分开，但是它们之间的距离可以非常小，以允许热界面材料层50的物理性质与参照示例实施例描述的物理性质基本相同。因此，能够防止下半导体芯片10损坏或开裂。
除了该区别之外，层叠封装件器件201及其制造方法可被构造为具有与本发明构思的示例实施例的层叠封装件器件及其制造方法基本相同或相似的特征。
[实施例3]
图13和图14是示出根据本发明构思的实施例3的层叠封装件器件的示例的剖视图。
参照图13，根据本实施例，层叠封装件器件202可包括横向延伸以同时与下半导体芯片10的顶表面和下成型层12的顶表面接触的热界面材料层50。
参照图14，根据本实施例，层叠封装件器件203可包括横向延伸以与下半导体芯片10顶表面和下成型层12的顶表面以及连接焊料凸起38的侧表面接触的热界面材料层50。在示例实施例中，热界面材料层50可以包括填充连接孔14的部分。
除了该区别之外，层叠封装件器件202和层叠封装件器件203及其制造方法可被构造为具有与本发明构思的示例实施例的层叠封装件器件及其制造方法基本相同或相似的特征。
[实施例4]
图15是示出是示出根据本发明构思的实施例4的层叠封装件器件的示例的剖视图。
参照图15，根据本实施例，层叠封装件器件204还可以包括设置在下半导体封装件101和上半导体封装件102之间的插入基底62。下半导体封装件101可以通过第一连接焊料凸起38电连接到插入基底62，上半导体封装件102可以通过第二连接焊料凸起39电连接到插入基底62。插入基底62可以是可由例如塑料、柔性膜或陶瓷制成的印刷电路板(PCB)。第一热界面材料层50a可以设置在插入基底62和下半导体封装件101之间，第二热界面材料层50b可以设置在插入基底62和上半导体封装件102之间。第一热界面材料层50a和第二热界面材料层50b中的每个可被构造为具有与本发明构思的示例实施例的热界面材料层50的特征基本相同或相似的特征。
除了该区别之外，层叠封装件器件204及其制造方法可被构造为具有与本发明构思的示例实施例的层叠封装件器件及其制造方法基本相同或相似的特征。
[实施例5]
图16是示出根据本发明构思的实施例5的层叠封装件器件的示例的剖视图。
参照图16，根据本实施例，层叠封装件器件205可包括其中未设置图1的下成型层12的下半导体封装件101b。在示例实施例中，可在下半导体芯片10和下封装件基底1之间设置下填充树脂层7。除了该区别之外，层叠封装件器件205及其制造方法可被构造为具有与本发明构思的示例实施例的层叠封装件器件及其制造方法基本相同或相似的特征。
[实施例6]
图17是示出根据本发明构思的实施例6的层叠封装件器件的示例的剖视图。
参照图17，根据本实施例，层叠封装件器件206可包括设置在上半导体封装件102和下半导体封装件101之间的第一热界面材料层50。第一热界面材料层50可被构造为具有与本发明构思的示例实施例的热界面材料层基本相同的特征。第二热界面材料层70和散热板60可以顺序地设置在上半导体封装件102上。第二热界面材料层70可被构造为具有与第一热界面材料层50的物理性质不同的物理性质。第二热界面材料层70可以是粘合层。散热板60可以是金属板或柔性金属带。除了该区别之外，层叠封装件器件206及其制造方法可被构造为具有与本发明构思的示例实施例的层叠封装件器件及其制造方法基本相同或相似的特征。
[实施例7]
图18是示出根据本发明构思的示例实施例7的层叠封装件器件的示例的剖视图。
参照图18，根据本实施例，层叠封装件器件207可以以这样的方式被构造，即，在其他示例实施例中描述的第二界面材料层70和散热板60延伸为覆盖上半导体封装件102和下半导体封装件101的侧表面。第二下焊料凸起16可以附着到下封装件基底1的底表面上。这使得能够进一步提高器件的散热效率。根据本实施例，由于散热板60被设置为覆盖上半导体封装件102和下半导体封装件101的顶表面和侧表面，所以除了散热功能之外，散热板60也可提供电磁干扰(EMI)屏蔽功能。结果，能够抑制半导体封装件的故障。
除了该区别之外，层叠封装件器件207及其制造方法可被构造为具有与本发明构思的其他示例实施例的层叠封装件器件及其制造方法基本相同或相似的特征。
可以应用上面描述的半导体封装技术来获得各种半导体器件及包括该半导体器件的封装模块。
图19是示出根据本发明构思的示例实施例的包括半导体封装件的封装件模块的示例的图。参照图19，封装件模块1200可包括以四角扁平封装(QFP)形式封装的半导体器件1220和半导体器件1230。半导体器件1220和1230可以利用根据本发明构思的示例实施例的半导体封装技术来形成，在封装件模块1200中，半导体器件1220和1230可以被安装在封装件基底1210上。封装件模块1200可以通过设置在封装件基底1210的一侧的外部连接端子1240连接到外部电子装置。
可以应用半导体封装技术来实现电子系统。图20是示出根据本发明构思的示例实施例的包括半导体封装件的电子系统的示例的示意性框图。参照图20，电子系统1300可以包括控制器1310、输入/输出(I/O)单元1320以及存储装置1330。控制器1310、I/O单元1320和存储装置1330可以通过数据总线1350彼此结合。数据总线1350可以对应于通过其传输电信号的路径。控制器1310可以包括微处理器、数据信号处理器、微控制器或另一逻辑器件中的至少一种。其他逻辑器件可以具有与微处理器、数据信号处理器和微控制器中的任意一种相似的功能。控制器1310和存储装置1330可以包括根据本发明构思的示例实施例的半导体封装件。I/O单元1320可以包括键区、键盘和/或显示单元。存储装置1330可以存储数据和/或由控制器1310执行的指令。存储装置1330可以包括易失性存储装置和/或非易失性存储装置。例如，存储装置1330可以包括闪存存储装置。闪存存储装置可以实现为固态硬盘(SSD)。在这种情况下，电子系统1300可以将大量数据稳定地存储到闪存存储系统。电子系统1300还可以包括将电数据传输到通信网络或从通信网络接收电数据的接口单元1340。接口单元1340可以通过无线或有线操作。例如，接口单元1340可以包括用于无线通信的天线或者用于有线通信的收发器。虽然未在附图中示出，但是还可在电子系统1300中设置应用芯片组和/或照相机图像处理器(CIS)。
电子系统1300可被实现为可移动系统、个人计算机、工业计算机或执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、网络平板、无线电话、移动电话、膝上计算机、数字音乐系统以及信息发送/接收系统中的一种。当电子系统1300执行无线通信时，电子系统1300可以用于诸如CDMA、GSM、NADC、E-TDMA、WCDMA、CDMA2000、Wi-Fi、Muni Wi-Fi、Bluetooth、DECT、Wireless USB、Flash-OFDM、IEEE802.20、GPRS、iBurst、WiBro、WiMAX、WiMAX-Advanced、UMTS-TDD、HSPA、EVDO、LTE-Advanced和MMDS等的通信系统的通信接口协议中。
根据本发明构思的示例实施例的半导体器件可以以存储卡的形式提供。图21是示出根据本发明构思的示例实施例的包括半导体封装件的存储系统的示例的示意性框图。参照图21，存储系统1400可包括非易失性存储装置1410和存储控制器1420。非易失性存储装置1410和存储控制器1420可以存储数据或读取存储的数据。非易失性存储装置1410可以包括至少一个非易失性存储装置，根据本发明构思的示例实施例的半导体封装技术可以应用到该非易失性存储装置。存储控制器1420可以控制非易失性存储装置1410，以响应于主机1430的读取/写入请求来读取存储的数据和/或存储数据。
根据本发明构思的示例实施例，热界面材料层可以设置在层叠封装件器件的下半导体封装件和上半导体封装件之间，并被构造为具有特定的物理性质(例如，小于7的莫氏硬度和/或500kPa或更低的弹性模量)。因此，能够在执行焊料球焊接工艺来将上半导体封装件安装在下半导体封装件上时防止在下半导体芯片中出现开裂。结果，能够减少层叠封装件器件的失效并提高层叠封装件器件的良率。
另外，由于在上半导体封装件和下半导体封装件之间添加了热界面材料层，所以能够将下半导体芯片中产生的热快速地排放到上半导体封装件。结果，能够减少层叠封装件器件的故障并提高层叠封装件器件的运行速度。
虽然已经具体示出并描述了本发明构思的示例实施例，但是本领域普通技术人员应当理解，在不脱离权利要求的精神和范围的情况下，在这里可以进行形式和细节上的改变。

Claims (36)

1.一种热界面材料层，设置在下半导体封装件和上半导体封装件之间，热界面材料层的弹性模量为500kPa或更低。
2.如权利要求1所述的热界面材料层，其中，热界面材料层具有小于7的莫氏硬度。
3.如权利要求1所述的热界面材料层，其中，热界面材料层的导热率为1W/mK或更高。
4.如权利要求1所述的热界面材料层，其中，热界面材料层包括树脂层和分散在树脂层中的填料颗粒，
树脂层的弹性模量为500kPa或更低。
5.如权利要求4所述的热界面材料层，其中，树脂层由硅基化合物或橡胶基化合物形成。
6.如权利要求4所述的热界面材料层，其中，填料颗粒具有小于7的莫氏硬度。
7.如权利要求6所述的热界面材料层，其中，填料颗粒被构造为表现出绝缘性质。
8.如权利要求7所述的热界面材料层，其中，填料颗粒是氮化硼颗粒和氧化锌颗粒中的至少一种。
9.如权利要求7所述的热界面材料层，其中，填料颗粒中的至少一个包括涂覆有绝缘层的金属颗粒，金属颗粒具有小于7的莫氏硬度。
10.如权利要求4所述的热界面材料层，其中，热界面材料层中的填料颗粒的含量范围为60wt％至95wt％。
11.一种热界面材料层，设置在顺序地堆叠的下半导体封装件和上半导体封装件之间，所述热界面材料层具有小于7的莫氏硬度。
12.如权利要求11所述的热界面材料层，其中，热界面材料层具有500kPa或更低的弹性模量。
13.如权利要求11所述的热界面材料层，其中，热界面材料层的导热率为1W/mK或更高。
14.如权利要求11所述的热界面材料层，其中，热界面材料层包括树脂层和分散在树脂层中的填料颗粒，
填料颗粒具有小于7的莫氏硬度。
15.如权利要求14所述的热界面材料层，其中，填料颗粒被构造为表现出绝缘性质。
16.如权利要求14所述的热界面材料层，其中，填料颗粒是氮化硼颗粒和氧化锌颗粒中的至少一种。
17.如权利要求14所述的热界面材料层，其中，填料颗粒中的至少一个包括涂覆有绝缘层的金属颗粒，金属颗粒具有小于7的莫氏硬度。
18.如权利要求14所述的热界面材料层，其中，树脂层的弹性模量为500kPa或更低。
19.如权利要求18所述的热界面材料层，其中，树脂层由硅基化合物或橡胶基化合物形成。
20.如权利要求14所述的热界面材料层，其中，热界面材料层中的填料颗粒的含量范围为60wt％至95wt％。
21.一种层叠封装件器件，所述器件包括：
下半导体封装件，包括下封装件基底和安装在下封装件基底上的下半导体芯片；
上半导体封装件，包括设置在下半导体封装件上的上封装件基底和安装在上封装件基底上的上半导体芯片；以及
第一热界面材料层，设置在下半导体芯片和上封装件基底之间，
其中，第一热界面材料层的弹性模量为500kPa或更低。
22.如权利要求21所述的器件，其中，第一热界面材料层具有小于7的莫氏硬度。
23.如权利要求22所述的器件，其中，第一热界面材料层的导热率为1W/mK或更高。
24.如权利要求22所述的器件，其中，第一热界面材料层包括树脂层和分散在树脂层中的填料颗粒，
树脂层的弹性模量为500kPa或更低。
25.如权利要求24所述的器件，其中，树脂层由硅基化合物或橡胶基化合物形成。
26.如权利要求24所述的器件，其中，填料颗粒具有小于7的莫氏硬度。
27.如权利要求26所述的器件，其中，填料颗粒被构造为表现出绝缘性质。
28.如权利要求27所述的器件，其中，填料颗粒是氮化硼颗粒和氧化锌颗粒中的至少一种。
29.如权利要求27所述的器件，其中，填料颗粒中的至少一个包括涂覆有绝缘层的金属颗粒，金属颗粒具有小于7的莫氏硬度。
30.如权利要求24所述的器件，其中，第一热界面材料层中的填料颗粒的含量范围为60wt％至95wt％。
31.如权利要求21所述的器件，其中，第一热界面材料层与下半导体芯片的顶表面接触。
32.如权利要求21所述的器件，其中，下半导体封装件还包括覆盖下半导体芯片的顶表面的下成型层，第一热界面材料层与下成型层的顶表面接触。
33.如权利要求21所述的器件，所述器件还包括设置在下半导体封装件和上半导体封装件之间的插入基底，
其中，第一热界面材料层设置在下半导体封装件与插入基底之间，并且在上半导体封装件与插入基底之间。
34.如权利要求21所述的器件，所述器件还包括：
第二热界面材料层，设置在上半导体封装件上；以及
散热板，设置在第二热界面材料层上，
其中，第二热界面材料层的物理性质与第一热界面材料层的物理性质不同。
35.如权利要求21所述的器件，其中，第一热界面材料层的莫氏硬度小于下半导体芯片的莫氏硬度。
36.一种层叠封装件器件，所述器件包括：
下半导体封装件，包括下封装件基底和安装在下封装件基底上的下半导体芯片；
上半导体封装件，包括设置在下半导体封装件上的上封装件基底和安装在上封装件基底上的上半导体芯片；以及
第一热界面材料层，设置在下半导体芯片和上封装件基底之间，
其中，第一热界面材料层具有小于7的莫氏硬度。
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