CN109830438B - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN109830438B
CN109830438B CN201711186310.7A CN201711186310A CN109830438B CN 109830438 B CN109830438 B CN 109830438B CN 201711186310 A CN201711186310 A CN 201711186310A CN 109830438 B CN109830438 B CN 109830438B
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layer
isolation
forming
fin
material layer
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CN109830438A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Priority to US16/118,010 priority patent/US10916479B2/en
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Priority to US17/247,984 priority patent/US11742414B2/en
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Abstract

一种半导体器件及其形成方法，其中方法包括：提供半导体衬底，所述半导体衬底上具有初始鳍部；在所述半导体衬底和初始鳍部上形成栅极结构材料层，所述栅极结构材料层的顶部表面高于初始鳍部的顶部表面；在所述栅极结构材料层和初始鳍部中形成凹槽，所述凹槽沿垂直于初始鳍部延伸方向且平行于半导体衬底表面的方向贯穿初始鳍部，使所述初始鳍部形成鳍部；在所述凹槽中形成隔离层，所述隔离层的顶部表面高于鳍部的顶部表面；刻蚀栅极结构材料层，使栅极结构材料层形成位于隔离层两侧的栅极结构，所述栅极结构横跨鳍部、且覆盖鳍部的部分顶部表面和部分侧壁表面。所述方法提高了半导体器件的隔离性能。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体器件及其形成方法。
背景技术
MOS(金属-氧化物-半导体)晶体管，是现代集成电路中最重要的元件之一。MOS晶体管的基本结构包括：半导体衬底；位于半导体衬底表面的栅极结构，所述栅极结构包括：位于半导体衬底表面的栅介质层以及位于栅介质层表面的栅电极层；位于栅极结构两侧半导体衬底中的源漏掺杂区。
随着半导体技术的发展，传统的平面式的MOS晶体管对沟道电流的控制能力变弱，造成严重的漏电流。鳍式场效应晶体管(Fin FET)是一种新兴的多栅器件，它一般包括凸出于半导体衬底表面的鳍部，覆盖部分所述鳍部的顶部表面和侧壁的栅极结构，位于栅极结构两侧的鳍部中的源漏掺杂区。
然而，现有技术中鳍式场效应晶体管构成的半导体器件的性能有待提高。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，以提高半导体器件的隔离性能。
为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供半导体衬底，所述半导体衬底上具有初始鳍部；在所述半导体衬底和初始鳍部上形成栅极结构材料层，所述栅极结构材料层的顶部表面高于初始鳍部的顶部表面；在所述栅极结构材料层和初始鳍部中形成凹槽，所述凹槽沿垂直于初始鳍部延伸方向且平行于半导体衬底表面的方向贯穿初始鳍部，使所述初始鳍部形成鳍部；在所述凹槽中形成隔离层，所述隔离层的顶部表面高于鳍部的顶部表面；刻蚀栅极结构材料层，使栅极结构材料层形成位于隔离层两侧的栅极结构，所述栅极结构横跨鳍部、且覆盖鳍部的部分顶部表面和部分侧壁表面。
可选的，还包括：在形成所述凹槽之前，在所述栅极结构材料层上形成掩膜层，所述掩膜层中具有开口；以所述掩膜层为掩膜，沿所述开口刻蚀所述栅极结构材料层和初始鳍部，形成所述凹槽；形成所述隔离层后，且在刻蚀栅极结构材料层之前，刻蚀掩膜层，使掩膜层形成栅保护层；以所述栅保护层为掩膜刻蚀栅极结构材料层以形成所述栅极结构；形成栅极结构后，所述栅保护层位于栅极结构顶部。
可选的，形成所述隔离层的步骤包括：在所述开口和所述凹槽中、以及掩膜层上形成隔离膜；平坦化隔离膜直至暴露出掩膜层表面，形成所述隔离层。
可选的，以所述掩膜层为掩膜，沿所述开口刻蚀栅极结构材料层和初始鳍部的方法包括：以所述掩膜层为掩膜，采用第一各向异性干刻工艺沿所述开口刻蚀栅极结构材料层和初始鳍部，在栅极结构材料层和初始鳍部中形成初始凹槽；进行所述第一各向异性干刻工艺后，以所述掩膜层为掩膜，采用第二各向异性干刻工艺刻蚀初始凹槽底部的初始鳍部，使所述初始凹槽形成所述凹槽，使初始鳍部形成所述鳍部；在沿所述鳍部的延伸方向上，所述凹槽的顶部尺寸大于底部尺寸。
可选的，所述第一各向异性干刻工艺的参数包括：采用气体包括CH4、CHF3、Ar和He，CH4的流量为50sccm～200sccm，CHF3的流量为50sccm～300sccm，Ar的流量为200sccm～500sccm，He的流量为200sccm～500sccm，源射频功率为200瓦～1000瓦，偏置电压为200伏～1000伏，腔室压强为10mtorr～50mtorr。
可选的，所述第二各向异性干刻工艺的参数包括：采用气体包括O2、N2和HBr，O2的流量为3sccm～10sccm，N2的流量为10sccm～30sccm，HBr的流量为200sccm～500sccm，源射频功率为500瓦～1000瓦，偏置电压为200伏～700伏，腔室压强为20mtorr～80mtorr。
可选的，还包括：在形成所述隔离层之前，在所述凹槽的侧壁和底部形成阻挡层；所述隔离层位于阻挡层上。
可选的，所述阻挡层的材料包括氮化硅。
可选的，所述阻挡层的厚度为5埃～10埃。
可选的，在形成所述栅极结构材料层之前，在所述半导体衬底上形成隔离结构，所述隔离结构覆盖初始鳍部的部分侧壁；形成鳍部后，所述隔离结构覆盖鳍部的部分侧壁；所述栅极结构材料层还位于隔离结构上；形成栅极结构后，栅极结构还位于隔离结构上。
可选的，所述隔离结构的材料包括氧化硅。
可选的，所述凹槽还位于所述隔离结构中。
可选的，在形成所述隔离层之前，所述凹槽暴露出半导体衬底表面。
可选的，所述隔离层的材料包括氧化硅。
可选的，所述栅极结构材料层包括位于半导体衬底和初始鳍部上的栅介质材料层、以及位于栅介质材料层表面的栅电极材料层。
可选的，所述栅介质材料层的材料为氧化硅；所述栅电极材料层的材料为多晶硅。
可选的，还包括：在所述栅极结构两侧的鳍部中分别形成源漏掺杂区；所述隔离层和栅极结构之间的鳍部中具有源漏掺杂区。
可选的，还包括：形成第一侧墙和第二侧墙，所述第一侧墙位于栅极结构侧壁，所述第二侧墙位于隔离层的侧壁，第二侧墙还覆盖部分鳍部；所述源漏掺杂区分别位于所述栅极结构和第一侧墙两侧的鳍部中。
本发明还提供一种采用上述任意一项方法形成的半导体器件，包括：半导体衬底；位于所述半导体衬底上的鳍部；位于所述鳍部中的隔离层，所述隔离层的顶部表面高于鳍部的顶部表面，且所述隔离层沿垂直于鳍部延伸方向且平行于半导体衬底表面的方向贯穿鳍部；位于隔离层两侧的栅极结构，所述栅极结构横跨鳍部、且覆盖鳍部的部分顶部表面和部分侧壁表面。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案提供的半导体器件的形成方法中，位于所述栅极结构材料层中的凹槽以及位于鳍部之间的凹槽在一个步骤中形成，避免了高于鳍部顶部表面的凹槽相对于低于鳍部顶部表面的凹槽对准出现偏差。在所述凹槽中形成隔离层后，高于鳍部顶部表面的隔离层能够将低于鳍部顶部表面的隔离层全部覆盖，使得隔离层的隔离性能增强，满足工艺设计的要求。
其次，在栅极结构材料层中形成凹槽，利用栅极结构材料层限定凹槽的位置。无需采用额外的材料定义凹槽，形成隔离层后，也无需采用额外的刻蚀工艺去除栅极结构材料层。综上，简化了工艺，且降低了成本。
进一步，在形成所述凹槽之前，在所述栅极结构材料层上形成掩膜层，所述掩膜层中具有开口；以所述掩膜层为掩膜，沿所述开口刻蚀所述栅极结构材料层和初始鳍部，形成所述凹槽。所述开口不仅定义出高于鳍部顶部表面的凹槽的位置，还定义出低于鳍部顶部表面的凹槽的位置。由于低于鳍部顶部表面的凹槽的位置无需单独采用光罩工艺定义，因此使得形成半导体器件的工艺成本降低。
其次，所述凹槽和所述初始鳍部在不同的步骤中形成，使得能够单独控制所述凹槽的深度，避免凹槽的深度受到初始鳍部形成过程的影响。因此能够避免凹槽在鳍部中的深度过浅，从而提高了隔离层的隔离性能。
进一步，在形成所述栅极结构材料层之前，在所述半导体衬底上形成隔离结构，所述隔离结构覆盖初始鳍部的部分侧壁。形成鳍部后，所述隔离结构覆盖鳍部的部分侧壁。因此在所述凹槽中形成隔离层后，无需再对隔离结构进行刻蚀处理，进而避免因刻蚀处理隔离结构对隔离层产生损耗。提高了隔离层的隔离性能。
进一步，在形成所述隔离层之前，在所述凹槽的侧壁和底部形成阻挡层，所述阻挡层用于在形成隔离层的过程中阻挡隔离层的材料氧化鳍部，避免鳍部尺寸有较大的变化。
本发明技术方案提供的半导体器件中，高于鳍部顶部表面的隔离层能够将低于鳍部顶部表面的隔离层全部覆盖，使得隔离层的隔离性能增强，满足工艺设计的要求。
附图说明
图1至图5是一种半导体器件形成过程的结构示意图；
图6至图12是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有技术形成的半导体器件的性能较差。
图1至图5是一种半导体器件形成过程的结构示意图。
参考图1，提供半导体衬底100，所述半导体衬底100上具有第一鳍部110和第二鳍部111，第一鳍部110和第二鳍部111的延伸方向平行，第一鳍部110和第二鳍部111之间的半导体衬底100为隔离区。
结合参考图2和图3，图3为沿着图2中切割线A1-A2的剖面图，在半导体衬底100上形成覆盖第一鳍部110和第二鳍部111侧壁的隔离结构膜120。
参考图4，图4为在图3基础上形成的示意图，在所述隔离结构膜120、第一鳍部110和第二鳍部111上形成掩膜层130，所述掩膜层130中具有开口(未图示)，所述开口位于隔离区上，所述开口沿着垂直于开口侧壁方向上的尺寸大于第一鳍部110和第二鳍部111之间的距离；在所述开口中形成隔离膜140。
参考图5，去除所述掩膜层130(参考图4)后，回刻蚀隔离膜140(参考图4)和隔离结构膜120，使相邻第一鳍部110之间、以及相邻第二鳍部111的隔离结构膜120形成隔离结构，使隔离膜140、以及第一鳍部110和第二鳍部111之间的隔离结构膜120形成隔离层141，所述隔离结构的顶部表面低于第一鳍部110和第二鳍部111的顶部表面，隔离层141的顶部表面高于第一鳍部110和第二鳍部111的顶部表面。
然而，上述方法所形成的半导体器件的性能较差，经研究发现，原因在于：
在形成掩膜层130的过程中，由于受到光刻对准精度受到工艺限制，因此导致所述开口相对于第一鳍部110和第二鳍部111之间的隔离结构膜120出现对准偏差，即所述掩膜层130覆盖第一鳍部110和第二鳍部111之间的部分隔离结构膜120。形成隔离膜140后，隔离膜140不能完全覆盖第一鳍部110和第二鳍部111之间的隔离结构膜120。去除掩膜层130后，会暴露出第一鳍部110和第二鳍部111之间的部分隔离结构膜120。在回刻蚀隔离膜140和隔离结构膜120的过程中，会刻蚀到所暴露出的第一鳍部110和第二鳍部111之间的隔离结构膜120，从而在第二鳍部111和隔离层141之间形成孔隙150，导致隔离层141隔离性能降低，不满足工艺设计的要求。
在此基础上，本发明提供一种半导体器件的形成方法，包括：在半导体衬底和初始鳍部上形成栅极结构材料层，栅极结构材料层的顶部表面高于初始鳍部的顶部表面；在栅极结构材料层和初始鳍部中形成凹槽，所述凹槽沿垂直于初始鳍部延伸方向且平行于半导体衬底表面的方向贯穿初始鳍部，使初始鳍部形成鳍部；在凹槽中形成隔离层，隔离层的顶部表面高于鳍部的顶部表面；之后，刻蚀栅极结构材料层，使栅极结构材料层形成栅极结构。所述方法提高了半导体器件的隔离性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图6至图12是本发明一实施例中半导体器件形成过程的结构示意图。
参考图6，提供半导体衬底200，所述半导体衬底200上具有初始鳍部210。
所述半导体衬底200为后续形成半导体器件提供工艺平台。
本实施例中，所述半导体衬底200的材料为单晶硅。所述半导体衬底200还可以是多晶硅或非晶硅。所述半导体衬底200的材料还可以为锗、锗化硅、砷化镓等半导体材料。
本实施例中，所述初始鳍部210通过图形化半导体衬底200而形成。在其它实施例中，可以是：在所述半导体衬底上形成鳍部材料层；刻蚀鳍部材料层，从而形成初始鳍部。
所述初始鳍部210的数量为1个或多个。本实施例中，以所述初始鳍部210的数量为2个作为示例。
本实施例中，当所述初始鳍部210的数量为多个时，初始鳍部210在半导体衬底200上的排布为：各条初始鳍部210彼此平行，初始鳍部210的排列方向垂直于初始鳍部210的延伸方向。在其它实施例中，可以根据设计的需要设定初始鳍部在半导体衬底上的排布。
本实施例中，在后续形成栅极结构材料层之前，还包括：在所述半导体衬底200上形成隔离结构220，所述隔离结构220覆盖初始鳍部210的部分侧壁，所述隔离结构220的表面低于初始鳍部210的顶部表面。
所述隔离结构220的作用包括：电学隔离相邻的初始鳍部210。
所述隔离结构220的材料包括氧化硅。
形成所述隔离结构220的方法包括：在所述半导体衬底200和初始鳍部210上形成隔离结构膜(未图示)；平坦化隔离结构膜，以去除高于初始鳍部210顶部表面的隔离结构膜；平坦化隔离结构膜后，回刻蚀隔离结构膜，形成隔离结构220。
形成所述隔离结构膜的工艺为沉积工艺。本实施例中，形成所述隔离结构膜的工艺为流体化学气相沉积工艺，使得隔离结构膜的填充能力较好。
参考图7，在所述半导体衬底200和初始鳍部210上形成栅极结构材料层230，所述栅极结构材料层230的顶部表面高于初始鳍部210的顶部表面。
本实施例中，在所述初始鳍部210和隔离结构220上形成栅极结构材料层230。
所述栅极结构材料层230包括位于半导体衬底200和初始鳍部210上的栅介质材料层、以及位于栅介质材料层表面的栅电极材料层。
所述栅介质材料层的材料为氧化硅；所述栅电极材料层的材料为多晶硅。
接着，在所述栅极结构材料层230和初始鳍部210中形成凹槽，所述凹槽沿垂直于初始鳍部210延伸方向且平行于半导体衬底200表面的方向贯穿初始鳍部210，使所述初始鳍部210形成鳍部。
本实施例中，还包括：在形成所述凹槽之前，在所述栅极结构材料层230上形成掩膜层，所述掩膜层中具有开口；以所述掩膜层为掩膜，沿所述开口刻蚀所述栅极结构材料层230和初始鳍部210，形成所述凹槽。
结合参考图8和图9，图8为在图7基础上的示意图，图9为沿着图8中切割线A2-A3的剖面图，在所述栅极结构材料层230上形成掩膜层240，所述掩膜层240中具有开口241。
本实施例中，形成所述掩膜层240的方法包括：在所述栅极结构材料层230上形成初始掩膜层(未图示)；在所述初始掩膜层上形成图形化的光刻胶层，所述图形化的光刻胶层定义出开口241的位置；以所述图形化的光刻胶层为掩膜刻蚀所述初始掩膜层，使初始掩膜层形成掩膜层240；之后，去除所述图形化的光刻胶层。
本实施例中，所述初始掩膜层为叠层结构，具体的，所述初始掩膜层包括：位于栅极结构材料层230上的初始有机掩膜层和位于初始有机掩膜层上的初始底部抗反射涂层。相应的，所述掩膜层240为叠层结构，所述掩膜层240包括：位于栅极结构材料层230上的有机掩膜层和位于有机掩膜层上的底部抗反射涂层。
所述初始有机掩膜层的作用为：使得工艺表面平坦化。
本实施例中，所述初始底部抗反射涂层的材料为含硅的碳氢化合物。所述初始底部抗反射涂层的作用为：在形成图形化的光刻胶的过程中，使得曝光精度提高；将初始底部抗反射涂层中的图形传递到初始有机掩膜层中。
在其它实施例中，所述初始掩膜层为单层结构，相应的，所述掩膜层为单层结构。所述初始掩膜层的材料为氮化硅或氮氧化硅。
参考图10，图10为在图9基础上的示意图，以所述掩膜层240为掩膜，沿所述开口241刻蚀所述栅极结构材料层230和初始鳍部210，在所述栅极结构材料层230和初始鳍部210(参考图9)中形成凹槽250，所述凹槽250沿垂直于初始鳍部210延伸方向且平行于半导体衬底200表面的方向贯穿初始鳍部210，使所述初始鳍部210形成鳍部211。
本实施例中，在沿所述鳍部211的延伸方向上，所述凹槽250的顶部尺寸大于底部尺寸，优势在于：有利于后续隔离膜的填充。
在其它实施例中，在沿所述鳍部的延伸方向上，所述凹槽的顶部尺寸等于或小于底部尺寸。
本实施例中，以所述掩膜层240为掩膜，沿所述开口241刻蚀栅极结构材料层230和初始鳍部210的方法包括：以所述掩膜层240为掩膜，采用第一各向异性干刻工艺沿所述开口241刻蚀栅极结构材料层230和初始鳍部210，在栅极结构材料层230和初始鳍部210中形成初始凹槽(未图示)；进行所述第一各向异性干刻工艺后，以所述掩膜层240为掩膜，采用第二各向异性干刻工艺刻蚀初始凹槽底部的初始鳍部210，使所述初始凹槽形成所述凹槽250，使初始鳍部210形成所述鳍部211；在沿所述鳍部211的延伸方向上，所述凹槽250的顶部尺寸大于底部尺寸。
为了方便说明，将凹槽250的顶部区域称为第一槽区，将凹槽250的底部区域称为第二槽区，第一槽区沿平行于鳍部211延伸方向的尺寸大于第二槽区沿平行于鳍部211延伸方向的尺寸。
本实施例中，所述第一槽区和第二槽区呈阶梯型，使得凹槽250的顶部尺寸和底部尺寸的差距较大，进一步利于后续隔离膜的填充。
在一个实施例中，第一各向异性干刻工艺的参数包括：采用气体包括CH4、CHF3、Ar和He，CH4的流量为50sccm～200sccm，CHF3的流量为50sccm～300sccm，Ar的流量为200sccm～500sccm，He的流量为200sccm～500sccm，源射频功率为200瓦～1000瓦，偏置电压为200伏～1000伏，腔室压强为10mtorr～50mtorr；所述第二各向异性干刻工艺的参数包括：采用气体包括O2、N2和HBr，O2的流量为3sccm～10sccm，N2的流量为10sccm～30sccm，HBr的流量为200sccm～500sccm，源射频功率为500瓦～1000瓦，偏置电压为200伏～700伏，腔室压强为20mtorr～80mtorr。
在进行第一各向异性干刻工艺和第二各向异性干刻工艺的过程中，会产生副产物。被副产物覆盖的区域受到第一各向异性干刻工艺和第二各向异性干刻工艺的刻蚀程度较少。第一各向异性干刻工艺产生的副产物聚集在初始凹槽的侧壁表面、以及初始凹槽底部表面边缘处。通过调整第二各向异性干刻工艺的第一各向异性干刻工艺的参数，使得第二各向异性干刻工艺产生副产物的速率大于第一各向异性干刻工艺产生副产物的速率。在进行第二各向异性干刻工艺时，副产物在初始凹槽底部边缘聚集速率较快，副产物覆盖的初始凹槽底部边缘的表面增加的程度较大，从而使得所述第一凹槽和第二凹槽呈阶梯型。
需要说明的是，在其它实施例中，第一各向异性干刻工艺和第二各向异性干刻工艺的参数相同。在进行第一各向异性干刻工艺和第二各向异性干刻工艺的参数相同，因此可以在一个步骤中连续进行，使得工艺简化。
所述隔离结构220覆盖鳍部211的部分侧壁。
本实施例中，所述凹槽250暴露出半导体衬底200的表面。在其它实施例中，所述凹槽的底部表面高于半导体衬底表面且低于隔离结构的顶部表面。或者，所述凹槽的底部表面高于隔离结构的顶部表面。
本实施例中，以所述掩膜层240为掩膜，沿所述开口241刻蚀栅极结构材料层230和初始鳍部210的过程中，还刻蚀了隔离结构220，使所述凹槽250还位于隔离结构220中。
所述开口241不仅定义出高于鳍部211顶部表面的凹槽250的位置，还定义出低于鳍部211顶部表面的凹槽250的位置。由于低于鳍部211顶部表面的凹槽250的位置无需单独采用光罩工艺定义，因此使得形成半导体器件的工艺成本降低。
另外，所述凹槽250和所述初始鳍部210在不同的步骤中形成，使得能够单独控制所述凹槽250的深度，避免凹槽250的深度受到初始鳍部210形成过程的影响。因此能够避免凹槽250在鳍部211中的深度过浅，从而提高了后续隔离层的隔离性能。
参考图11，在所述凹槽250(参考图10)中形成隔离层260，所述隔离层260的顶部表面高于鳍部211的顶部表面。
所述隔离层260的材料包括氧化硅。
形成所述隔离层260的步骤包括：在所述开口241和所述凹槽250中、以及掩膜层240上形成隔离膜(未图示)；平坦化隔离膜直至暴露出掩膜层240表面，形成所述隔离层260。
本实施例中，还包括：在形成所述隔离层260之前，在所述凹槽250和开口241的侧壁、以及凹槽250的底部形成阻挡层270；所述隔离层260位于阻挡层270上。
所述阻挡层270的材料包括氮化硅。
所述阻挡层270用于在形成隔离层260的过程中阻挡隔离层260的材料氧化鳍部211，避免鳍部211尺寸有较大的变化。
所述阻挡层270的厚度为5埃～10埃。阻挡层270的厚度选择此范围的意义包括：若所述阻挡层270的厚度大于10埃，导致阻挡层270占据凹槽250和开口241中的空间较大，后续隔离层形成的空间较小，导致隔离层的隔离性能下降；若阻挡层270的厚度小于5埃，导致阻挡层270对鳍部211的保护能力较弱。
参考图12，形成所述隔离层260后，刻蚀栅极结构材料层230，使栅极结构材料层230形成位于隔离层260两侧的栅极结构280，所述栅极结构280横跨鳍部211、且覆盖鳍部211的部分顶部表面和部分侧壁表面。
所述隔离层260和所述栅极结构280相互分立。
本实施例中，还包括：形成所述隔离层260后，且在刻蚀栅极结构材料层230之前，刻蚀掩膜层240，使掩膜层240形成栅保护层290；以所述栅保护层290为掩膜刻蚀栅极结构材料层230以形成所述栅极结构280；形成栅极结构280后，所述栅保护层290位于栅极结构280顶部。
所述栅保护层290的材料为氮化硅或氮氧化硅。
所述栅极结构材料层230还位于隔离结构220上；形成栅极结构280后，栅极结构280还位于隔离结构220上。
本实施例中，隔离层260的顶部表面高于栅极结构280的顶部表面，具体的，隔离层260的顶部表面和栅保护层290的顶部表面的高度基本一致。相应的，无需在隔离层260上形成附加栅极结构，后续以隔离层和栅极结构280共同限制源漏掺杂区的生长空间，无需用附加栅极结构限制源漏掺杂区的生长空间。
本实施例中，在形成栅极结构材料层230之前，在半导体衬底200上形成隔离结构220，隔离结构220覆盖初始鳍部210的部分侧壁。形成鳍部211后，所述隔离结构220覆盖鳍部211的部分侧壁。因此在所述凹槽250中形成隔离层260后，无需再对隔离结构220进行刻蚀处理，进而避免因刻蚀处理隔离结构220对隔离层260产生损耗，提高了隔离层260的隔离性能。
本实施例中，还包括：在栅极结构280两侧的鳍部211中分别形成源漏掺杂区；所述隔离层260和栅极结构280之间的鳍部211中具有源漏掺杂区。
形成所述源漏掺杂区的步骤包括：在所述栅极结构280两侧的鳍部211中分别形成源漏槽；采用外延生长工艺在所述源漏槽中形成源漏掺杂区。
本实施例中，还包括：形成第一侧墙和第二侧墙，所述第一侧墙位于栅极结构280侧壁，所述第二侧墙位于隔离层260的侧壁，第二侧墙还覆盖部分鳍部211；所述源漏掺杂区分别位于所述栅极结构280和第一侧墙两侧的鳍部211中。
所述第一侧墙和第二侧墙共同限制了源漏掺杂区的形成空间，使得对于栅极结构280和隔离层260之间的源漏掺杂区，靠近栅极结构280一侧的源漏掺杂区和靠近隔离层260一侧的源漏掺杂区的生长速率较为一致。
本实施例中，位于所述栅极结构材料层中的凹槽以及位于鳍部之间的凹槽在一个步骤中形成，避免了高于鳍部顶部表面的凹槽相对于低于鳍部顶部表面的凹槽对准出现偏差。在所述凹槽中形成隔离层后，高于鳍部顶部表面的隔离层能够将低于鳍部顶部表面的隔离层全部覆盖，使得隔离层的隔离性能增强，满足工艺设计的要求。
其次，在栅极结构材料层中形成凹槽，利用栅极结构材料层限定凹槽的位置。无需采用额外的材料定义凹槽，形成隔离层后，也无需采用额外的刻蚀工艺去除栅极结构材料层。综上，简化了工艺，且降低了成本。
相应的，本实施例还提供一种采用上述方法形成的半导体器件，请参考图12，包括：半导体衬底200；位于所述半导体衬底200上的鳍部211；位于所述鳍部211中的隔离层260，所述隔离层260的顶部表面高于鳍部211的顶部表面，且所述隔离层260沿垂直于鳍部211延伸方向且平行于半导体衬底200表面的方向贯穿鳍部211；位于隔离层260两侧的栅极结构280，所述栅极结构280横跨鳍部211、且覆盖鳍部211的部分顶部表面和部分侧壁表面。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (18)

1.一种半导体器件的形成方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底上具有初始鳍部；
在所述半导体衬底和初始鳍部上形成栅极结构材料层，所述栅极结构材料层的顶部表面高于初始鳍部的顶部表面；
在所述栅极结构材料层和初始鳍部中形成凹槽，所述凹槽沿垂直于初始鳍部延伸方向且平行于半导体衬底表面的方向贯穿初始鳍部，使所述初始鳍部形成鳍部；
在所述凹槽中形成隔离层，所述隔离层的顶部表面高于鳍部的顶部表面；
刻蚀栅极结构材料层，使栅极结构材料层形成位于隔离层两侧的栅极结构，所述栅极结构横跨鳍部、且覆盖鳍部的部分顶部表面和部分侧壁表面；
在形成所述栅极结构材料层之前，在所述半导体衬底上形成隔离结构，所述隔离结构覆盖初始鳍部的部分侧壁；形成鳍部后，所述隔离结构覆盖鳍部的部分侧壁；所述栅极结构材料层还位于隔离结构上；形成栅极结构后，栅极结构还位于隔离结构上。
2.根据权利要求1所述的半导体器件的形成方法，其特征在于，还包括：在形成所述凹槽之前，在所述栅极结构材料层上形成掩膜层，所述掩膜层中具有开口；以所述掩膜层为掩膜，沿所述开口刻蚀所述栅极结构材料层和初始鳍部，形成所述凹槽；形成所述隔离层后，且在刻蚀栅极结构材料层之前，刻蚀掩膜层，使掩膜层形成栅保护层；以所述栅保护层为掩膜刻蚀栅极结构材料层以形成所述栅极结构；形成栅极结构后，所述栅保护层位于栅极结构顶部。
3.根据权利要求2所述的半导体器件的形成方法，其特征在于，形成所述隔离层的步骤包括：在所述开口和所述凹槽中、以及掩膜层上形成隔离膜；平坦化隔离膜直至暴露出掩膜层表面，形成所述隔离层。
4.根据权利要求2所述的半导体器件的形成方法，其特征在于，以所述掩膜层为掩膜，沿所述开口刻蚀栅极结构材料层和初始鳍部的方法包括：以所述掩膜层为掩膜，采用第一各向异性干刻工艺沿所述开口刻蚀栅极结构材料层和初始鳍部，在栅极结构材料层和初始鳍部中形成初始凹槽；进行所述第一各向异性干刻工艺后，以所述掩膜层为掩膜，采用第二各向异性干刻工艺刻蚀初始凹槽底部的初始鳍部，使所述初始凹槽形成所述凹槽，使初始鳍部形成所述鳍部；在沿所述鳍部的延伸方向上，所述凹槽的顶部尺寸大于底部尺寸。
5.根据权利要求4所述的半导体器件的形成方法，其特征在于，所述第一各向异性干刻工艺的参数包括：采用气体包括CH4、CHF3、Ar和He，CH4的流量为50sccm～200sccm，CHF3的流量为50sccm～300sccm，Ar的流量为200sccm～500sccm，He的流量为200sccm～500sccm，源射频功率为200瓦～1000瓦，偏置电压为200伏～1000伏，腔室压强为10mtorr～50mtorr。
6.根据权利要求4所述的半导体器件的形成方法，其特征在于，所述第二各向异性干刻工艺的参数包括：采用气体包括O2、N2和HBr，O2的流量为3sccm～10sccm，N2的流量为10sccm～30sccm，HBr的流量为200sccm～500sccm，源射频功率为500瓦～1000瓦，偏置电压为200伏～700伏，腔室压强为20mtorr～80mtorr。
7.根据权利要求1所述的半导体器件的形成方法，其特征在于，还包括：在形成所述隔离层之前，在所述凹槽的侧壁和底部形成阻挡层；所述隔离层位于阻挡层上。
8.根据权利要求7所述的半导体器件的形成方法，其特征在于，所述阻挡层的材料包括氮化硅。
9.根据权利要求7所述的半导体器件的形成方法，其特征在于，所述阻挡层的厚度为5埃～10埃。
10.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述隔离结构的材料包括氧化硅。
11.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述凹槽还位于所述隔离结构中。
12.根据权利要求1所述的半导体器件的形成方法，其特征在于，在形成所述隔离层之前，所述凹槽暴露出半导体衬底表面。
13.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述隔离层的材料包括氧化硅。
14.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述栅极结构材料层包括位于半导体衬底和初始鳍部上的栅介质材料层、以及位于栅介质材料层表面的栅电极材料层。
15.根据权利要求14所述的半导体器件的形成方法，其特征在于，所述栅介质材料层的材料为氧化硅；所述栅电极材料层的材料为多晶硅。
16.根据权利要求1所述的半导体器件的形成方法，其特征在于，还包括：在所述栅极结构两侧的鳍部中分别形成源漏掺杂区；所述隔离层和栅极结构之间的鳍部中具有源漏掺杂区。
17.根据权利要求16所述的半导体器件的形成方法，其特征在于，还包括：形成第一侧墙和第二侧墙，所述第一侧墙位于栅极结构侧壁，所述第二侧墙位于隔离层的侧壁，第二侧墙还覆盖部分鳍部；所述源漏掺杂区分别位于所述栅极结构和第一侧墙两侧的鳍部中。
18.一种根据权利要求1至17任意一项方法形成的半导体器件，其特征在于，包括：
半导体衬底；
位于所述半导体衬底上的鳍部；
位于所述鳍部中的隔离层，所述隔离层的顶部表面高于鳍部的顶部表面，且所述隔离层沿垂直于鳍部延伸方向且平行于半导体衬底表面的方向贯穿鳍部；
位于隔离层两侧的栅极结构，所述栅极结构横跨鳍部、且覆盖鳍部的部分顶部表面和部分侧壁表面。
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