CN109728093A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
CN109728093A
CN109728093A CN201810731334.4A CN201810731334A CN109728093A CN 109728093 A CN109728093 A CN 109728093A CN 201810731334 A CN201810731334 A CN 201810731334A CN 109728093 A CN109728093 A CN 109728093A
Authority
CN
China
Prior art keywords
nano wire
barrier layer
sige
pmos
top surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810731334.4A
Other languages
English (en)
Other versions
CN109728093B (zh
Inventor
萧孟轩
陈维宁
李东颖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109728093A publication Critical patent/CN109728093A/zh
Application granted granted Critical
Publication of CN109728093B publication Critical patent/CN109728093B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明实施例涉及一种半导体结构，其包括第一晶体管和第二晶体管。所述第一晶体管包括半导体衬底，其具有顶面和所述顶面处的掺杂有第一导电性掺杂剂的第一抗穿通区域。所述第一晶体管进一步包括位于所述半导体衬底的所述顶面上方第一距离处的第一沟道。所述第二晶体管包括所述半导体衬底的所述顶面处的掺杂有第二导电性掺杂剂的第二抗穿通区域。所述第二晶体管进一步包括位于所述半导体衬底的所述顶面上方第二距离处的第二沟道，所述第二距离大于所述第一距离。本发明实施例还涉及一种用于制造本文中所描述的半导体结构的方法。

Description

半导体结构及其制造方法
技术领域
本发明实施例涉及半导体结构及其制造方法。
背景技术
金属氧化物半导体场效晶体管(MOSFET)用于存在于现今的半导体集成电路(IC)芯片产品中的超大型集成(ULSI)电路中。MOSFET的栅极长度不断缩小以获得更快电路速度、更高电路密度和增加功能性和更低单位功能成本。随着MOSFET的栅极长度缩小到小于20nm的范围内，源极和漏极越来越多与沟道相互作用以大体上影响沟道电位。因此，具有短栅极长度的晶体管通常存在与栅极无法大体上控制沟道的开/关状态相关的问题。与沟道电位的减少栅极控制相关的现象被称为短沟道效应。
提高体相掺杂浓度、减小栅极氧化物厚度和结深度是抑制短沟道效应的一些方法。然而，为使装置完全缩小到小于20nm的范围内，体相掺杂浓度、栅极氧化物厚度和源极/漏极掺杂分布的要求越来越难以使用基于块硅衬底的常规装置结构来满足。因此，考量提供短沟道效应的更好控制的替代装置结构来实现晶体管大小的不断缩小。
提供短沟道效应的极佳控制的可高度缩放装置结构是晶体管的回绕式栅极结构(也称为环绕式栅极或全环绕式栅极晶体管结构)。回绕式栅极结构通常具有环绕或回绕沟道区域的栅极。与常规块硅衬底晶体管结构、双栅极晶体管结构和三栅极晶体管结构相比，此结构有效改进栅极与沟道之间的电容耦合。就回绕式栅极结构来说，栅极对沟道电位产生重要影响且因此改进短沟道效应的抑制。
发明内容
本发明的一实施例涉及一种半导体结构，其包含第一晶体管，所述第一晶体管包含：半导体衬底，其具有顶面和所述顶面处的掺杂有第一导电性掺杂剂的第一抗穿通(anti-punch through)区域；第一沟道，其位于所述半导体衬底的所述顶面上方第一距离处，其中所述第一沟道处的所述第一导电性掺杂剂的浓度低于所述半导体衬底的所述顶面处的所述第一导电性掺杂剂的浓度。
本发明的一实施例涉及一种用于制造半导体结构的方法，其包含：使第一抗穿通区域形成于第一晶体管区域处的半导体衬底的顶面处；通过生长结晶层来使势垒层形成于所述第一晶体管区域处的所述半导体衬底的所述顶面上方；使第一沟道材料和第二沟道材料堆叠形成于所述势垒层上方。
本发明的一实施例涉及一种用于形成PMOS结构的方法，其包含：使N型井区域形成于半导体衬底中；使具有n型掺杂剂的抗穿通区域形成于所述半导体衬底中；使具有大于所述n型掺杂剂的扩散长度的厚度的扩散势垒层形成于所述半导体衬底的顶面上方；使SiGe纳米线沟道层形成于所述扩散势垒层上方；形成SiGe纳米线沟道且去除所述SiGe纳米线沟道下方的所述扩散势垒层。
附图说明
附图中依举例而非限制的方式绘示一或多个实施例，其中具有相同元件符号的元件表示所有图中的相同元件。除非另有公开，否则图式未按比例绘制。
图1A是展示纳米线和半导体鳍片结构中的库仑散射的说明图。
图1B是展示纳米线和半导体鳍片结构中的对相对于带电粒子数目的载子移动率变化的效应的图式。
图2A和图2B是展示根据本公开的一些实施例的非平面半导体结构和不同位置处的剖切线的俯视图。
图3是根据本公开的一些实施例的沿图2A的剖切线AA'剖切的半导体结构的剖面图。
图4是根据本公开的一些实施例的沿图2A的剖切线AA'剖切的半导体结构的剖面图。
图5是根据本公开的一些实施例的沿图2B的剖切线BB'剖切的半导体结构的剖面图。
图6是根据本公开的一些实施例的沿图2B的剖切线BB'剖切的半导体结构的剖面图。
图7是根据本公开的一些实施例的沿图2A的剖切线剖切的PMOS半导体结构的简化剖面图。
图8是根据本公开的一些实施例的沿图2A的剖切线剖切的PMOS半导体结构和NMOS半导体结构的简化剖面图。
图9是展示根据本公开的一些实施例的两种情境(具有或不具有本文中所描述的势垒层)下的第一硅锗纳米线和半导体衬底中的磷浓度的SIMS分布图。
图10到16、图17A、图17B、图18A、图18B、图19和图20是展示根据本公开的一些实施例的制造半导体结构中的中间操作的剖面图。
具体实施方式
下文将详细讨论本公开的实施例的制造和使用。然而，应了解，实施例提供可在各种特定背景中体现的诸多适用发明概念。所讨论的特定实施例仅用于绘示制造和使用实施例的特定方式且不限制本公开的范围。在所有各种视图和绘示性实施例中，相同元件符号用于标示相同元件。现将详细参考附图中所绘示的示范性实施例。只要可能，相同元件符号在图式和描述中用于指相同或相似部件。在图式中，为了清楚和方便起见，可放大形状和厚度。此描述将尤其针对形成根据本公开的设备的部分或更直接地与所述设备协作的元件。应了解，未特定展示或描述的元件可呈现各种形式。参考本说明书中的“一实施例”意味着结合所述实施例所描述的特定特征、结构或特性包括于至少一实施例中。因此，出现于本说明书的各种位置中的短语“在一实施例中”未必全部是指相同实施例。此外，特定特征、结构或特性可在一或多个实施例中依任何适合方式组合。应了解，下列图式未按比例绘制；相反地，此些图仅供说明。
此外，为了方便描述，可在本文中使用空间相对术语(例如“底下”、“下方”、“下”、“上方”、“上”等等)来描述一元件或构件与另一(些)元件或构件的关系，如图中所绘示。除图中所描绘的定向之外，空间相对术语还打算涵盖装置在使用或操作中的不同定向。设备可依其它方式定向(旋转90度或依其它定向)，且还可据此解译本文中所使用的空间相对描述词。
在FinFET装置中，沟道区域中的掺杂剂或缺陷可将少数载子的移动率减小到比全环绕式栅极装置的沟道区域中的掺杂剂或缺陷小的程度，这是因为FinFET装置的物理沟道大于全环绕式栅极对应物，如图1A中所展示，类似数量的掺杂剂或缺陷将比全环绕式栅极装置对载子移动率产生更大影响。如图1B中所展示，模拟结果表明，全环绕式栅极装置的沟道区域中的3个带电粒子将使载子移动率减小74％，而FinFET装置的沟道区域中的相同数目个带电粒子将使载子移动率减小19％。换句话说，随着从FinFET装置发展到全环绕式栅极装置，应在设计接近沟道区域的掺杂区域处的结构时格外小心以防止掺杂剂或缺陷非所要地扩散到沟道区域中。
全环绕式栅极MOSFET结构的特征为具有多个纳米线沟道的3D栅极区域。应用抗穿通(APT)注入以缓解全环绕式栅极MOSFET结构中的沟道穿通泄漏电流和反向偏压p-n结漏电。然而，APT注入被应用于紧邻沟道区域的区域中；因此，沟道区域的结构完整性易受损坏。另外，归因于N/P井注入接近底部纳米线沟道，其也成为进入沟道区域的缺陷的来源。本公开不是直接使APT区域和N/P井区域与沟道区域非常接近或直接接触，而是提供势垒层来缓冲源于APT区域和/或N/P井区域的掺杂剂扩散。
缓冲源于APT区域和/或N/P井区域的掺杂剂扩散的势垒层可(例如)安置于半导体衬底的顶面与纳米线沟道的底部之间。在一些实施例中，势垒层可由结晶材料组成。在一些实施例中，势垒层可由相同于或不同于纳米线沟道的材料组成。在一些实施例中，可取决于势垒层的材料选择而在最终产品中去除或不去除或部分去除势垒层。
在全环绕式栅极MOSFET的技术中，包括III族和IV族材料的若干材料系统是目前已知的且应被涵盖于本公开的考量范围内。例如，在硅衬底上，通常针对NMOS采用Si纳米线沟道且针对PMOS采用SiGe纳米线沟道。在GaAs衬底上，通常针对NMOS采用GaAs纳米线沟道且针对PMOS采用InGaAs纳米线沟道。在Ge/GaAs衬底上，通常针对NMOS采用Ge纳米线沟道且针对PMOS采用GaAs纳米线沟道。为简洁起见，本公开仅提供Si纳米线和SiGe纳米线材料系统的绘示和详细描述。相同发明概念可应用于要解决的不同半导体材料系统上。
参考图2A和图2B，图2A和图2B是展示根据本公开的一些实施例的非平面半导体结构和不同位置处的剖切线的俯视图。在图2A中，将有源区域20A和20B绘示为两个平行条。在描述全环绕式栅极MOSFET结构的实施例中，有源区域包括图案化半导体衬底的掺杂区域和所述图案化半导体衬底上方的纳米线沟道。在下列公开中，有源区域20A可包括PMOS晶体管结构的一部分且有源区域20B可包括NMOS晶体管结构的一部分。在本公开中，元件符号20A可通常指称具有PMOS晶体管结构的有源区域，且元件符号20B可通常指称具有NMOS晶体管结构的有源区域。两个栅极200和200'正交地安置于有源区域20A和20B上方，有源区域20A和20B在栅极200处由源极/漏极区域201A、201B邻接且在栅极200'处由源极/漏极区域201A'、201B'邻接。剖切线AA'沿栅极200的纵向方向穿过栅极200，借此在后续图3和图4中展示栅极200(为简单起见，其被省略)和下伏有源区域20A和20B的剖面。类似地，在图2B中，将有源区域20A和20B绘示为两个平行条。在下列公开中，有源区域20A可为PMOS晶体管结构且有源区域20B可为NMOS晶体管结构。两个栅极200和200'正交地安置于有源区域20A和20B上方，有源区域20A和20B在栅极200处由源极/漏极区域201A、201B邻接且在栅极200'处由源极/漏极区域201A'、201B'邻接。剖切线BB'穿过源极/漏极区域201A、201B，借此在后续图5和图6中展示源极/漏极区域201A、201B和下伏有源区域20A和20B的剖面。
参考图3，图3是根据本公开的一些实施例的沿图2A的剖切线AA'剖切的半导体结构30的剖面图。为简单起见，图3中省略所有纳米线上方的栅极200的一部分。半导体结构30包括PMOS 20A和NMOS 20B。在一些实施例中，PMOS 20A可或可不安置于NMOS 20B相邻处。
半导体结构30包括图案化为至少两个半导体鳍片100A、100B的衬底100。在一些实施例中，衬底100包括硅，且衬底100是根据FinFET布置形成，所述布置包括由例如浅沟渠隔离区(STI)的隔离结构103分离的一或多个硅鳍片。例如，第一鳍片100A和第二鳍片100B形成于衬底100上且在鳍片100A、100B的各者处具有顶面100T。在PMOS20A中，通过使用n型掺杂剂(例如磷)的APT注入来使抗穿通区域(APT)101P形成于顶面100T接近处。在NMOS 20B中，通过使用p型掺杂剂(例如硼)的另一APT注入来使APT 101P'形成于顶面100T接近处。
仍参考图3，PMOS 20A进一步包括沿第一鳍片100A的纵向方向的多个SiGe纳米线101A、102A、103A、104A、105A，在SiGe纳米线101A、102A、103A、104A、105A的两端处连接源极/漏极201A(图3中未展示)。在所有SiGe纳米线中，101A被称为底部SiGe纳米线，其为最靠近半导体鳍片100A的顶面100T的纳米线。在一些实施例中，顶面100T与底部SiGe纳米线101A的底部之间的距离大致为从约1nm到约10nm。在一些实施例中，栅极200填充于相邻SiGe纳米线101A、102A、103A、104A、105A之间和顶面100T与底部SiGe纳米线101A之间。
如图3中所展示，PMOS 20A中未展示势垒层，这是因为势垒层已在沟道处的纳米线释放操作期间被去除或部分去除，如稍后将在图18A中描述。APT区域101P可具有约5E18/cm3的n型掺杂剂浓度。归因于本文中所描述的势垒层的有效缓冲，底部SiGe纳米线101A的底部部分处的n型掺杂剂浓度可低于1E18/cm3。
类似地，NMOS 20B进一步包括沿第二鳍片100B的纵向方向的多个Si纳米线101B、102B、103B、104B、105B，在Si纳米线101B、102B、103B、104B、105B的两端处连接源极/漏极201B(图3中未展示)。在所有Si纳米线中，101B被称为底部Si纳米线，其为最靠近半导体鳍片100B的顶面100T的纳米线。在一些实施例中，顶面100T与底部Si纳米线101B的底部之间的距离大于顶面100T与底部SiGe纳米线101A的底部之间的距离。在一些实施例中，栅极200填充于相邻Si纳米线101B、102B、103B、104B、105B之间和顶面100T与底部Si纳米线101B之间。
如图3中所展示，NMOS 20B中展示位于APT区域101P'上方和栅极200'和底部Si纳米线101B下方的势垒层110B。在一些实施例中，势垒层110B由结晶硅或掺碳结晶硅组成。APT区域101P'可具有约5E18/cm3的p型掺杂剂浓度。底部Si纳米线101B的底部部分处的p型掺杂剂浓度可低于1E18/cm3。在一些实施例中，p型掺杂剂可为硼。
参考图4，图4是根据本公开的一些实施例的沿图2A的剖切线AA'剖切的半导体结构40的剖面图。为简单起见，图4中省略所有纳米线上方的栅极200的一部分。半导体结构40包括PMOS 20A和NMOS 20B。在一些实施例中，PMOS 20A可或可不安置于NMOS 20B相邻处。
半导体结构40包括图案化为至少两个半导体鳍片100A、100B的衬底100。在一些实施例中，衬底100包括硅，且衬底100是根据FinFET布置形成，所述布置包括由例如浅沟渠隔离区(STI)的隔离结构103分离的一或多个硅鳍片。例如，第一鳍片100A和第二鳍片100B形成于衬底100上且在鳍片100A、100B的各者处具有顶面100T。在PMOS20A中，通过使用n型掺杂剂(例如磷)的APT注入来使抗穿通区域(APT)101P形成于顶面100T接近处。在NMOS 20B中，通过使用p型掺杂剂(例如硼)的另一APT注入来使APT 101P'形成于顶面100T接近处。
仍参考图4，NMOS 20B进一步包括沿第二鳍片100B的纵向方向的多个Si纳米线101B、102B、103B、104B、105B，在Si纳米线101B、102B、103B、104B、105B的两端处连接源极/漏极201B(图3中未展示)。在所有Si纳米线中，101B被称为底部Si纳米线，其为最靠近半导体鳍片100B的顶面100T的纳米线。在一些实施例中，顶面100T与底部Si纳米线101B的底部之间的距离大致大于半导体鳍片100A的顶面100T与底部SiGe纳米线101A的底部之间的距离。在一些实施例中，栅极200'填充于相邻Si纳米线101B、102B、103B、104B、105B之间和顶面100T与底部Si纳米线101B之间。
如图4中所展示，NMOS 20B中未展示势垒层，这是因为势垒层已在沟道处的纳米线释放操作期间被去除或部分去除，如稍后将在图17B中描述。APT区域101P'可具有约5E18/cm3的p型掺杂剂浓度。底部Si纳米线101B的底部部分处的p型掺杂剂浓度可低于1E18/cm3。
类似地，PMOS 20A进一步包括沿第一鳍片100A的纵向方向的多个SiGe纳米线101A、102A、103A、104A、105A，在SiGe纳米线101A、102A、103A、104A、105A的两端处连接源极/漏极201A(图3中未展示)。在所有SiGe纳米线中，101A被称为底部SiGe纳米线，其为最靠近半导体鳍片100A的顶面100T的纳米线。在一些实施例中，顶面100T与底部SiGe纳米线101A的底部之间的距离是在从约1nm到约10nm的范围内。在一些实施例中，栅极200填充于相邻SiGe纳米线101A、102A、103A、104A、105A之间和顶面100T与底部SiGe纳米线101A之间。
如图4中所展示，PMOS 20A中展示位于APT区域101P上方和栅极200和底部SiGe纳米线101A下方的势垒层110A。在一些实施例中，势垒层110A由结晶硅锗或掺碳结晶硅锗组成。APT区域101P可具有约5E18/cm3的n型掺杂剂浓度。底部SiGe纳米线101A的底部部分处的n型掺杂剂浓度可低于1E18/cm3。在一些实施例中，n型掺杂剂可为磷。
参考图5，图5是根据本公开的一些实施例的沿图2B的剖切线BB'剖切的半导体结构50的剖面图。半导体结构50包括PMOS 20A和NMOS 20B。在一些实施例中，PMOS20A可或可不安置于NMOS 20B相邻处。图5和图3中的相同元件符号是指相同组件或其等效物，且为简洁起见，此处不再重复。在图5中，PMOS 20A的源极/漏极201A包围SiGe纳米线101A、102A、103A、104A，而NMOS 20B的源极/漏极201B包围Si纳米线101B、102B、103B、104B和势垒层110B。如图5中所展示，源极/漏极201A或201B的轮廓展示根据各纳米线的刻面化侧壁。然而，在其它实施例中，源极/漏极201A或201B可拥有包覆结构，其在堆叠纳米线的两端处的垂直侧壁可被检测。在其它实施例中，源极/漏极201A或201B拥有从半导体鳍片100A/100B的顶部雕刻的凹槽结构。换句话说，源极/漏极201A或201B的底部可低于半导体衬底100的顶面100T。在一些实施例中，NMOS 20B中的势垒层110B由结晶硅或掺碳结晶硅组成。PMOS20A中未展示势垒层，这是因为势垒层已在源极/漏极201A处的纳米线释放操作期间被去除或部分去除。
参考图6，图6是根据本公开的一些实施例的沿图2B的剖切线BB'剖切的半导体结构60的剖面图。半导体结构60包括PMOS 20A和NMOS 20B。在一些实施例中，PMOS20A可或可不安置于NMOS 20B相邻处。图6和图4中的相同元件符号是指相同组件或其等效物，且为简洁起见，此处不再重复。在图6中，PMOS 20A的源极/漏极201A包围SiGe纳米线101A、102A、103A、104A和势垒层110A，而NMOS 20B的源极/漏极201B包围Si纳米线101B、102B、103B、104B。如图6中所展示，源极/漏极201A或201B的轮廓展示根据各纳米线的刻面化侧壁。然而，在其它实施例中，源极/漏极201A或201B可拥有包覆结构，其在堆叠纳米线的两端处的垂直侧壁可被检测。在其它实施例中，源极/漏极201A或201B拥有从半导体鳍片100A/100B的顶部雕刻的凹槽结构。换句话说，源极/漏极201A或201B的底部可低于半导体衬底100的顶面100T。在一些实施例中，PMOS 20A中的势垒层110A由结晶硅锗或掺碳结晶硅锗组成。NMOS 20B中未展示势垒层，这是因为势垒层已在源极/漏极201B处的纳米线释放操作期间被去除或部分去除。
参考图7，图7是根据本公开的一些实施例的沿图2A的剖切线剖切的PMOS半导体结构70的简化剖面图。图7中省略PMOS半导体结构70中的栅极200以更好展示半导体衬底的顶面100T与底部SiGe纳米线101A的相对位置。在一些实施例中，底部SiGe纳米线101A的底部与顶面100T之间的距离T1至少等于或大于势垒层(图7中未展示)的厚度。在一些实施例中，势垒层的厚度是在从约5nm到约10nm的范围内。势垒层的厚度应至少大于n型掺杂剂最初在APT区域101P中时的扩散长度。例如，n型掺杂剂(磷)的平均扩散长度为约5nm。势垒层的厚度应至少薄于允许在不损坏下伏鳍片的情况下完全去除势垒层的临界厚度。在一些实施例中，临界厚度为约10nm。
图8是根据本公开的一些实施例的沿图2A的剖切线剖切的PMOS和NMOS半导体结构80的简化剖面图。图8中省略PMOS和NMOS半导体结构中的栅极200以更好展示半导体衬底的顶面100T与底部SiGe纳米线101A和底部Si纳米线101B的相对位置。在一些实施例中，底部Si纳米线101B的底部与顶面100T之间的距离T2至少等于或大于势垒层110B的厚度T3。例如，距离T2可在从约3nm到约12nm的范围内。在一些实施例中，势垒层的厚度T3是在从约1nm到约10nm的范围内。势垒层的厚度T3应至少大于p型掺杂剂最初在APT区域101P'中时的扩散长度。例如，p型掺杂剂(硼)的平均扩散长度为约1nm。势垒层的厚度应至少薄于允许在不损坏下伏鳍片的情况下完全去除势垒层的临界厚度。在一些实施例中，临界厚度为约10nm。
参考图9，图9是展示两种情境下的底部SiGe纳米线101A和半导体衬底100中的磷浓度的SIMS分布图。数据901展示未永久形成势垒层时的PMOS半导体结构中的磷浓度。半导体衬底100的顶面100T下方的磷浓度大于5E18/cm3，且底部SiGe纳米线101A中的磷浓度也大于5E18/cm3。两个相邻区域中的相当磷浓度表明磷扩散未受抑制。然而，数据903展示在制造操作期间形成势垒层时的PMOS半导体结构中的磷浓度。半导体衬底100的顶面100T下方的磷浓度大于5E18/cm3，但底部SiGe纳米线101A中的磷浓度小于1E18/cm3。两个相邻区域中的磷浓度的显著下降表明磷扩散受到抑制，即，由于本文中所描述的势垒层的阻碍。
图10到16、图17A、图17B、图18A、图18B、图19和图20是展示根据本公开的一些实施例的制造半导体结构中的中间操作的剖面图。为体现全面性，衬底100的左侧展示PMOS 20A的制造操作，且衬底100的右侧展示NMOS 20B的制造操作。在图10中，使牺牲层1003形成于衬底100的顶面100T上方。在一些实施例中，牺牲层1003可为通过CVD、PVD或其它适合方法所沉积的氧化物或氮化物。在PMOS 20A中，执行第一注入操作1001以形成从顶面100T向下延伸的n型井1001A。在一些实施例中，第一注入的高能量掺杂剂穿透牺牲层1003而进入到衬底100中。类似地，在NMOS 20B中，执行第二注入操作1001'以形成从顶面100T向下延伸的p型井1001B。在第一注入操作与第二注入操作之间进行掩模或光阻图案化以分别形成n型井1001A和p型井1001B，且为简洁起见，此处省略掩模或光阻图案化。另外，形成p型井1001B未必为紧跟形成n型井1001A之后的操作。在一些实施例中，可在制造NMOS 20B的操作之前执行制造PMOS 20A的操作。在一些实施例中，可在制造NMOS 20B的操作之后执行制造PMOS20A的操作。
在图11中，执行第一抗穿通(APT)注入操作1002以将n型掺杂剂(例如磷或砷)提供到PMOS 20A中的第一APT区域101P中。第一APT区域101P浅于n型井1001A且接近顶面100T。执行第二抗穿通(APT)注入操作1002'以将p型掺杂剂(例如硼)提供到NMOS 20B中的第一APT区域101P'中。第二APT区域101P'浅于p型井1001B且接近顶面100T。第一APT区域101P和第二APT区域101P'两者位于牺牲层1003下方且邻接牺牲层1003。在图12中，通过氧化物或氮化物剥离操作来从PMOS 20A和NMOS 20B中的半导体衬底100的顶面100T去除牺牲层1003。
在图13中，将势垒层110A、110B沉积于先前从其去除牺牲层1003的顶面100T上方。在一些实施例中，势垒层110A、110B与顶面100T直接接触。将势垒层110A指派为PMOS 20A中的部分且将势垒层110B指派为NMOS 20B中的部分。在一些实施例中，势垒层110A、110B通过单一沉积操作来形成且由相同材料组成。换句话说，使势垒层110A和势垒层110B同时形成于顶面100T上方。在一些实施例中，势垒层110A、110B为结晶层，这是因为随后覆加材料为结晶材料，当下伏模板也为结晶结构时，优选地获得具有满意结晶度的结晶层。就此来说，如果Si/SiGe堆叠将形成于势垒层110A、110B上方，那么势垒层110A、110B可为结晶硅层或结晶硅锗层。在其它实施例中，为减小掺杂剂扩散程度，势垒层110A、110B可为掺碳的，例如掺碳结晶硅层或掺碳结晶硅锗层。在一些实施例中，鉴于例如对应掺杂剂扩散长度和蚀刻能力的因数，势垒层110A、110B的厚度T3可在从约1nm到约10nm的范围内。例如，势垒层的厚度T3应至少大于n型掺杂剂最初在APT区域101P中或p型掺杂剂最初在APT区域101P'中时的扩散长度。另一方面，势垒层的厚度T3应至少薄于允许在不损坏半导体衬底100的下伏顶面100T的情况下完全去除势垒层的临界厚度。
在图14中，使第一沟道材料和第二沟道材料堆叠形成于势垒层110A、110B上方。例如，使硅和硅锗堆叠140形成于势垒层110A、110B上方。例如，使第一硅和硅锗堆叠形成于衬底100上方。第一硅和硅锗堆叠包括一或多个硅层和一或多个硅锗层。例如，第一硅和硅锗堆叠包括第一硅锗层101A、第一硅层101B、第二硅锗层102A、第二硅层102B、第三硅锗层103A、第三硅层103B。应了解，可形成任何数目个硅层或硅锗层。在一实例中，硅锗层包含约20％到约75％之间的锗。替代地，上述硅锗层101A、102A、103A、104A、105A的至少一者可由纯锗层替换。接着，图案化硅和硅锗堆叠140、势垒层110A、110B和衬底100以形成由STI 103分离的半导体鳍片100A和100B，如图15中所展示。
在图16中，使输入/输出(I/O)氧化物层150保形地形成于鳍片100A、100B的部分、经图案化硅和硅锗堆叠140和STI 103的顶面上方。在形成输入/输出(I/O)氧化物层150之后，通过后续图案化操作来横跨第一鳍片100A和第二鳍片100B正交地形成虚设栅极160。虚设栅极160为通过图案化技术所形成的牺牲栅极，例如多晶硅栅极。在虚设栅极160形成之后，在源极/漏极201A、201B形成之前将虚设栅极160用作用于源极/漏极区域(图16中未展示)处的后续第一纳米线释放操作的硬掩模。可取决于用于势垒层110A、110B的材料而在源极/漏极区域处的第一纳米线释放操作期间去除或不去除势垒。例如，如果将结晶硅或掺碳结晶硅用作势垒层110A，那么当释放PMOS中的硅锗纳米线时，将通过适当蚀刻剂来去除包括势垒层110A的基于硅的材料。另一方面，当释放对应NMOS中的硅纳米线时，将通过适当蚀刻剂来去除基于硅锗的材料以使势垒层110A在第一纳米线释放操作之后完好无损。在PMOS和对应NMOS中的第一纳米线释放操作之后，随后将使源极/漏极201A、201B形成于所释放的纳米线的两端处。
图17A和图18A展示将硅或掺碳硅用作势垒层110A、110B时的PMOS 20A和NMOS20B中的沟道区域处的第二纳米线释放操作。与第一纳米线释放操作相比，第二纳米线释放操作在虚设栅极去除操作之后于原来由虚设栅极160覆盖的沟道区域处进行，而第一纳米线释放操作在将虚设栅极160用作硬掩模时于源极/漏极201A、201B处进行。在图17A中，将硬掩模170安置于PMOS 20A上方且使NMOS 20B暴露于硅纳米线释放操作。如先前所讨论，由于势垒层110B由硅或掺碳硅组成，所以在硅纳米线释放操作之后保留势垒层110B，因为用于释放Si纳米线101B、102B、103B、104B、105B的蚀刻剂对基于硅的材料具有较低选择性且对非基于硅的材料(例如基于硅锗的材料)具有较高选择性。类似地，在图18A中，将硬掩模180安置于NMOS 20B上方且使PMOS 20A暴露于硅锗纳米线释放操作。如先前所讨论，由于势垒层110A也是由硅或掺碳硅组成，所以在硅锗纳米线释放操作之后去除势垒层110A，因为用于释放SiGe纳米线101A、102A、103A、104A、105A的蚀刻剂对基于硅锗的材料具有较低选择性且对非基于硅锗的材料(例如基于硅的材料)具有较高选择性。
图17B和图18B展示将硅锗或掺碳硅锗用作势垒层110A、110B时的PMOS 20A和NMOS20B中的沟道区域处的第二纳米线释放操作。与第一纳米线释放操作相比，第二纳米线释放操作在虚设栅极去除操作之后于原来由虚设栅极160覆盖的沟道区域处进行，而第一纳米线释放操作在将虚设栅极160用作硬掩模时于源极/漏极201A、201B处进行。在图17B中，将硬掩模170安置于PMOS 20A上方且使NMOS 20B暴露于硅纳米线释放操作。如先前所讨论，由于势垒层110B由硅锗或掺碳硅锗组成，所以在硅纳米线释放操作之后去除势垒层110B，因为用于释放Si纳米线101B、102B、103B、104B、105B的蚀刻剂对基于硅的材料具有较低选择性且对非基于硅的材料(例如基于硅锗的材料)具有较高选择性。类似地，在图18B中，将硬掩模180安置于NMOS 20B上方且使PMOS 20A暴露于硅锗纳米线释放操作。如先前所讨论，由于势垒层110A也是由硅锗或掺碳硅锗组成，所以在硅锗纳米线释放操作之后保留势垒层110A，因为用于释放SiGe纳米线101A、102A、103A、104A、105A的蚀刻剂对基于硅锗的材料具有较低选择性且对非基于硅锗的材料(例如基于硅的材料)具有较高选择性。
图19展示去除图18A中的硬掩模180之后的半导体结构190。NMOS 20B使势垒层110B保留于APT区域101P'上方，而PMOS 20A中的势垒层110A已在上文所描述的第二纳米线释放操作期间被去除。随后，沉积栅极材料以填充相邻释放纳米线之间的空间和顶面100T与底部SiGe纳米线101A或底部Si纳米线101B之间的空间。在一些实施例中，在NMOS 20B之前执行PMOS 20A处的栅极材料填充。在其它实施例中，在PMOS 20A之前执行NMOS 20B处的栅极材料填充。在一些实施例中，在PMOS 20A和NMOS 20B中，可在多个释放纳米线周围和多个释放纳米线周围上方形成包括界面层材料、高k介电层、氮化钛覆盖层、功函数金属层和钨栅极金属的栅极材料。
图20展示去除图18B中的硬掩模180之后的半导体结构200。PMOS 20A使势垒层110A保留于APT区域101P上方，而NMOS 20B中的势垒层110B已在上文所描述的第二纳米线释放操作期间被去除。随后，沉积栅极材料以填充相邻释放纳米线之间的空间和顶面100T与底部SiGe纳米线101A或底部Si纳米线101B之间的空间。在一些实施例中，在NMOS 20B之前执行PMOS 20A处的栅极材料填充。在其它实施例中，在PMOS20A之前执行NMOS 20B处的栅极材料填充。在一些实施例中，在PMOS 20A和NMOS20B中，可在多个释放纳米线周围和多个释放纳米线上方形成包括界面层材料、高k介电层、氮化钛覆盖层、功函数金属层和钨栅极金属的栅极材料。
一些实施例提供一种半导体结构，其包括第一晶体管。所述第一晶体管包括半导体衬底，其具有顶面和所述顶面处的掺杂有第一导电性掺杂剂的第一抗穿通区域。所述第一晶体管进一步包括位于所述半导体衬底的所述顶面上方第一距离处的第一沟道。所述第一沟道处的所述第一导电性掺杂剂的浓度低于所述半导体衬底的所述顶面处的所述第一导电性掺杂剂的浓度。
一些实施例提供一种用于制造半导体结构的方法，其包括：(1)使第一抗穿通区域形成于第一晶体管区域处的半导体衬底的顶面处；(2)通过生长结晶层来使势垒层形成于所述第一晶体管区域处的所述半导体衬底的所述顶面上方；和(3)使第一沟道材料和第二沟道材料堆叠形成于所述势垒层上方。
一些实施例提供一种用于制造PMOS结构的方法，其包括：(1)使N型井区域形成于半导体衬底中；(2)使具有n型掺杂剂的抗穿通区域形成于所述半导体衬底中；(3)使具有大于所述n型掺杂剂的扩散长度的厚度的扩散势垒层形成于所述半导体衬底的顶面上方；(4)使SiGe纳米线沟道层形成于所述扩散势垒层上方；(5)形成SiGe纳米线沟道且去除所述SiGe纳米线沟道下方的所述扩散势垒层。
尽管已详细描述本发明实施例和其优点，但应了解，可在不背离随附权利要求书界定的本发明实施例的精神和范围的情况下对本文进行各种改变、置换和变更。例如，上文所讨论的诸多程序可以不同方法实施且可由其它程序或其等的一组合替换。
此外，不打算使本申请案的范围受限于本说明书中所描述的程序、机器、制造、物质组成、手段、方法和步骤的特定实施例。一般技术人员将易于从本发明实施例的公开了解，可根据本发明实施例来利用现存或后来将发展的程序、机器、制造、物质组成、手段、方法或步骤，其等执行大体上相同于本文中所描述的对应实施例的功能或达成大体上相同于本文中所描述的对应实施例的结果。据此，随附权利要求书打算将此些程序、机器、制造、物质组成、手段、方法或步骤包括于其范围内。
符号说明
20A 有源区域/PMOS
20B 有源区域/NMOS
30 半导体结构
40 半导体结构
50 半导体结构
60 半导体结构
70 PMOS半导体结构
80 PMOS和NMOS半导体结构
100 衬底
100A 半导体鳍片/第一鳍片
100B 半导体鳍片/第二鳍片
100T 顶面
101A SiGe纳米线
101B Si纳米线
101P 抗穿通区域(APT)
101P' APT
102A SiGe纳米线
102B Si纳米线
103 隔离结构
103A SiGe纳米线
103B Si纳米线
104A SiGe纳米线
104B Si纳米线
105A SiGe纳米线
105B Si纳米线
110A 势垒层
110B 势垒层
140 硅和硅锗堆叠
150 输入/输出(I/O)氧化物层
160 虚设栅极
170 硬掩模
180 硬掩模
190 半导体结构
200 栅极/半导体结构
200' 栅极
201A 源极/漏极区域
201B 源极/漏极区域
201A' 源极/漏极区域
201B' 源极/漏极区域
901 数据
903 数据
1001 第一注入操作
1001' 第二注入操作
1001A n型井
1001B p型井
1002 第一抗穿通(APT)注入操作
1002' 第二抗穿通(APT)注入操作
1003 牺牲层
T1 距离
T2 距离
T3 厚度

Claims (1)

1.一种半导体结构，其包含：
第一晶体管，其包含：
半导体衬底，其具有顶面和所述顶面处的掺杂有第一导电性掺杂剂的第一抗穿通区域；
第一沟道，其位于所述半导体衬底的所述顶面上方第一距离处，
其中所述第一沟道处的所述第一导电性掺杂剂的浓度低于所述半导体衬底的所述顶面处的所述第一导电性掺杂剂的浓度。
CN201810731334.4A 2017-10-31 2018-07-05 半导体结构及其制造方法 Active CN109728093B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762579422P 2017-10-31 2017-10-31
US62/579,422 2017-10-31
US15/879,888 2018-01-25
US15/879,888 US10535738B2 (en) 2017-10-31 2018-01-25 Semiconductor structure and manufacturing method of the same

Publications (2)

Publication Number Publication Date
CN109728093A true CN109728093A (zh) 2019-05-07
CN109728093B CN109728093B (zh) 2023-05-16

Family

ID=66244250

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810731334.4A Active CN109728093B (zh) 2017-10-31 2018-07-05 半导体结构及其制造方法

Country Status (3)

Country Link
US (4) US10535738B2 (zh)
CN (1) CN109728093B (zh)
TW (1) TWI759453B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10825933B2 (en) * 2018-06-11 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around structure and manufacturing method for the same
US11769836B2 (en) * 2019-05-07 2023-09-26 Intel Corporation Gate-all-around integrated circuit structures having nanowires with tight vertical spacing
US11348803B2 (en) 2019-05-20 2022-05-31 Applied Materials, Inc. Formation of bottom isolation
US11177259B2 (en) 2019-09-27 2021-11-16 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-threshold gate structure with doped gate dielectric layer
US11145654B2 (en) * 2019-10-16 2021-10-12 Qualcomm Incorporated Field effect transistor (FET) comprising channels with silicon germanium (SiGe)
US11222952B2 (en) * 2020-01-22 2022-01-11 Qualcomm Incorporated Gate all around transistors with high charge mobility channel materials
US11784226B2 (en) * 2020-11-13 2023-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor gate-all-around device having an anti-punch-through (APT) layer including carbon
US20240088252A1 (en) * 2022-09-08 2024-03-14 International Business Machines Corporation Gate all around transistors with heterogeneous channels

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593057A (zh) * 2011-01-13 2012-07-18 Soitec公司 具有埋入掺杂层的完全耗尽soi器件
US20150034899A1 (en) * 2013-08-01 2015-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Fabricating the Same
US20150214365A1 (en) * 2014-01-24 2015-07-30 Globalfoundries Inc. Multiwidth finfet with channel cladding
US20160049402A1 (en) * 2014-08-18 2016-02-18 Stmicroelectronics, Inc. Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods
US20160104765A1 (en) * 2014-06-27 2016-04-14 Taiwan Semiconductor Manufacturing Company Limited Semiconductor devices with horizontal gate all around structure and methods of forming the same
CN106033757A (zh) * 2014-10-10 2016-10-19 台湾积体电路制造股份有限公司 具有抗穿通层的高迁移率器件及其形成方法
CN106486544A (zh) * 2015-08-26 2017-03-08 环球晶圆股份有限公司 增强型高电子迁移率晶体管结构
TW201724278A (zh) * 2015-11-30 2017-07-01 台灣積體電路製造股份有限公司 多閘極元件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9006829B2 (en) 2012-08-24 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Aligned gate-all-around structure
US9209247B2 (en) 2013-05-10 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned wrapped-around structure
US9136332B2 (en) 2013-12-10 2015-09-15 Taiwan Semiconductor Manufacturing Company Limited Method for forming a nanowire field effect transistor device having a replacement gate
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9412817B2 (en) 2014-12-19 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide regions in vertical gate all around (VGAA) devices and methods of forming same
US9536738B2 (en) 2015-02-13 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical gate all around (VGAA) devices and methods of manufacturing the same
US9502265B1 (en) 2015-11-04 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical gate all around (VGAA) transistors and methods of forming the same
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593057A (zh) * 2011-01-13 2012-07-18 Soitec公司 具有埋入掺杂层的完全耗尽soi器件
US20150034899A1 (en) * 2013-08-01 2015-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Fabricating the Same
US20150214365A1 (en) * 2014-01-24 2015-07-30 Globalfoundries Inc. Multiwidth finfet with channel cladding
US20160104765A1 (en) * 2014-06-27 2016-04-14 Taiwan Semiconductor Manufacturing Company Limited Semiconductor devices with horizontal gate all around structure and methods of forming the same
US20160049402A1 (en) * 2014-08-18 2016-02-18 Stmicroelectronics, Inc. Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods
CN106033757A (zh) * 2014-10-10 2016-10-19 台湾积体电路制造股份有限公司 具有抗穿通层的高迁移率器件及其形成方法
CN106486544A (zh) * 2015-08-26 2017-03-08 环球晶圆股份有限公司 增强型高电子迁移率晶体管结构
TW201724278A (zh) * 2015-11-30 2017-07-01 台灣積體電路製造股份有限公司 多閘極元件

Also Published As

Publication number Publication date
US11728384B2 (en) 2023-08-15
US10535738B2 (en) 2020-01-14
TW201919108A (zh) 2019-05-16
TWI759453B (zh) 2022-04-01
US20220359663A1 (en) 2022-11-10
CN109728093B (zh) 2023-05-16
US20200176567A1 (en) 2020-06-04
US11411083B2 (en) 2022-08-09
US20230352535A1 (en) 2023-11-02
US20190131405A1 (en) 2019-05-02

Similar Documents

Publication Publication Date Title
CN109728093A (zh) 半导体结构及其制造方法
US10134840B2 (en) Series resistance reduction in vertically stacked silicon nanowire transistors
CN103531477B (zh) 具有位于下方的嵌入式抗穿通层的FinFET方法和结构
CN101661934B (zh) 半导体器件及其制造方法
CN104979211B (zh) 纳米线器件及其制造方法
US8105901B2 (en) Method for double pattern density
US20210050457A1 (en) Method for forming gate-all-around structure
CN107845579B (zh) 在垂直晶体管器件上形成底部与顶部源极/漏极区的方法
CN104854685B (zh) 提高纳米线和finfet的ion/ioff比率
CN103227202A (zh) FinFET体接触件及其制造方法
US20170170299A1 (en) Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
US20170125410A1 (en) Finfet device and method for fabricating the same
US10937810B2 (en) Sub-fin removal for SOI like isolation with uniform active fin height
US9379018B2 (en) Increasing Ion/Ioff ratio in FinFETs and nano-wires
CN103456782B (zh) 半导体器件及其制造方法
CN103390649A (zh) 用于高k和金属栅极堆叠件的器件和方法
US11264285B2 (en) Method for forming film stacks with multiple planes of transistors having different transistor architectures
CN107123673A (zh) 一种独立三栅FinFET器件的多阈值电压调控方法
CN110993681B (zh) C形有源区半导体器件及其制造方法及包括其的电子设备
CN106558604A (zh) 一种用于esd防护的栅控二极管
JP2021500741A (ja) 半導体デバイス、半導体装置および半導体デバイス形成方法
KR20130079010A (ko) 반도체 소자 제조 방법
CN114765219A (zh) 一种半导体器件及其制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant