CN106033757A - 具有抗穿通层的高迁移率器件及其形成方法 - Google Patents

具有抗穿通层的高迁移率器件及其形成方法 Download PDF

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CN106033757A
CN106033757A CN201510122423.5A CN201510122423A CN106033757A CN 106033757 A CN106033757 A CN 106033757A CN 201510122423 A CN201510122423 A CN 201510122423A CN 106033757 A CN106033757 A CN 106033757A
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layer
adulterant
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semiconductor
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CN106033757B (zh
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江国诚
冯家馨
吴志强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

示例性半导体器件包括从半导体衬底向上延伸的鳍。该鳍包括具有APT掺杂剂的抗穿通(APT)层和位于APT层上方的沟道区。沟道区基本无APT掺杂剂。半导体器件还包括位于沟道区的侧壁和顶面上的导电栅极堆叠件。本发明涉及具有抗穿通层的高迁移率器件及其形成方法。

Description

具有抗穿通层的高迁移率器件及其形成方法
相关申请的交叉引用
本申请要求于2014年10月10日提交的标题为“High Mobility Deviceswith Anti-Punch Through Layers and Methods of Forming Same”的美国临时专利申请第62/062,598号的权益，其全部内容结合于此作为参考。
技术领域
本发明涉及具有抗穿通层的高迁移率器件及其形成方法。
背景技术
半导体器件用于诸如计算机、手机等大量的电子器件中。半导体器件包括集成电路，该集成电路通过在半导体晶圆上方沉积诸多类型的材料薄膜以及图案化材料薄膜以形成集成电路而形成在半导体晶圆上。集成电路通常包括场效应晶体管(FET)。
通常，平面FET已用于集成电路。然而，由于对现代半导体处理的不断增加的密度和不断降低的覆盖区(footprint)的要求，当平面FET的尺寸减小时，平面FET通常可出现一些问题。一些这种问题包括亚阈值摆幅退化(swing degradation)、明显的漏致势垒降低(DIBL)、器件特性的波动以及泄漏。已研究了鳍式场效应晶体管(finFET)来克服一些这种问题。
在典型的finFET中，在衬底上方形成垂直鳍结构。这种垂直鳍结构用于在横向方向上形成源极/漏极区和在鳍中形成沟道区。在形成finFET的垂直方向上，在鳍的沟道区上方形成栅极。随后，可在finFET上方形成层间电介质(ILD)和多个互连层。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：第一鳍，从半导体衬底向上延伸，其中，所述第一鳍包括第一抗穿通(APT)层，包括APT掺杂剂；和第一沟道区，位于所述第一APT层上方，其中，所述第一沟道区基本不含所述APT掺杂剂；以及导电栅极堆叠件，位于所述第一沟道区的侧壁和顶面上。
在上述半导体器件中，所述第一APT层包括硅硼(SiB)或硅碳硼(SiCB)。
在上述半导体器件中，还包括邻近所述导电栅极堆叠件的源极和漏极区，其中，所述第一APT层设置在所述源极和漏极区下面。
在上述半导体器件中，还包括从所述半导体衬底向上延伸的第二鳍，其中，所述第二鳍包括：第二APT层，包括n型APT掺杂剂和p型APT掺杂剂；以及第二沟道区，位于所述第二APT层上方。
在上述半导体器件中，所述第二APT层中的所述p型APT掺杂剂的第一浓度与所述第二APT层中的所述n型APT掺杂剂的第二浓度的比率至少为约2:1。
在上述半导体器件中，所述第二APT层包括硅硼磷或硅碳硼磷。
根据本发明的另一方面，还提供了一种半导体器件，包括：第一鳍式场效应晶体管(finFET)，包括：第一抗穿通(APT)层，包括第一类型的第一APT掺杂剂；和第一半导体层，位于所述第一APT层上方；第一导电栅极堆叠件，位于所述第一半导体层的侧壁和顶面上；和第一源极和漏极区，邻近所述第一导电栅极堆叠件；以及第二finFET，包括：第二APT层，包括第一类型的第二APT掺杂剂和不同于所述第一类型的第二类型的第三APT掺杂剂；第二半导体层，位于所述第二APT层上方；第二导电栅极堆叠件，位于所述第二半导体层的侧壁和顶面上；和第二源极和漏极区，邻近所述第二导电栅极堆叠件。
在上述半导体器件中，所述第一半导体层基本未掺杂任何APT掺杂剂。
在上述半导体器件中，所述第一APT层包括硅硼(SiB)或硅碳硼(SiCB)，并且其中，所述第二APT层包括硅硼磷(SiBP)或硅碳硼磷(SiCBP)。
在上述半导体器件中，所述第二APT层包括至少为所述第二APT掺杂剂两倍的第三APT掺杂剂。
在上述半导体器件中，所述第一finFET还包括：第三半导体层，位于所述第一APT层下面；以及半导体氧化物层，位于所述第三半导体层的侧壁上。
在上述半导体器件中，所述第一APT层设置在所述第一源极和漏极区下面，并且其中，所述第二APT层设置在所述第二源极和漏极区下面。
根据本发明的又一方面，还提供了一种形成半导体器件的方法，所述方法包括：在半导体衬底上方形成抗穿通(APT)层，其中，所述APT层包括第一APT掺杂剂；在所述APT层上方形成半导体层；图案化所述半导体层和所述APT层以限定从所述半导体衬底向上延伸的第一鳍，其中，所述第一鳍包括第一APT层部分和第一半导体层部分；以及在所述第一鳍的所述第一半导体层部分的顶面和侧壁上形成导电栅极堆叠件。
在上述方法中，所述半导体层基本不含任何APT掺杂剂。
在上述方法中，图案化所述半导体层和所述APT层还限定了包括第二APT层部分和第二半导体层部分的第二鳍，并且其中，所述方法还包括：去除所述第二半导体层部分以暴露出所述第二APT层部分；以及在所述第二APT层部分中注入第二APT掺杂剂，其中，所述第二APT掺杂剂的类型不同于所述第一APT掺杂剂的类型。
在上述方法中，还包括当注入所述第二APT掺杂剂时，掩蔽所述第一鳍。
在上述方法中，注入所述第二APT掺杂剂包括在所述第二APT层部分中注入至少为所述第一APT掺杂剂的约两倍的所述第二APT掺杂剂。
在上述方法中，在注入所述第二APT掺杂剂之后，所述第二APT层部分包括硅硼磷(SiBP)或硅碳硼磷(SiCBP)。
在上述方法中，形成所述APT层包括外延生长包括硅硼或硅碳硼的层。
在上述方法中，还包括在邻近所述导电栅极堆叠件的所述第一鳍中形成源极和漏极区，其中，所述第一APT层部分设置在所述源极和漏极区下面。
附图说明
当结合附图进行阅读时，通过下列详细的描述，可以更好地理解本发明的各方面。应该强调的是，根据工业中的标准实践，没有按比例绘制各种部件。实际上，为了清楚地讨论，可以任意地增大或减小各种部件的尺寸。
图1是三维视图中的鳍式场效应晶体管(finFET)的实例。
图2至图17C示出了根据一些实施例的制造finFEt的中间阶段的截面图。
图18示出了根据一些实施例的用于制造finFET的方法的流程图。
具体实施方式
以下公开提供了多种不同实施例或实例，用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚，并且其本身不表示所述多个实施例和/或配置之间的关系。
此外，在此可使用诸如“在…之下”、“在…下面”、“下面的”、“在…之上”、以及“上面的”等的空间关系术语，以容易的描述如图中所示的一个元件或部件与另一元件(多个元件)或部件(多个部件)的关系。除图中所示的方位之外，空间关系术语将包括使用或操作中的装置的各种不同的方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且通过在此使用的空间关系描述符进行相应地解释。
各种实施例包括在半导体衬底中外延生长抗穿通(APT)层。APT层提供原位APT掺杂剂，其可防止来自源极/漏极区的n型和p型掺杂剂穿通进入各种finFET器件的下面的半导体层内。此外，包括APT层消除了在形成这种finFET器件期间至少在第一类型(例如，n型或p型)的器件中实施APT注入的需要，这可产生未掺杂的沟道区和提高的电功能性。可仍实施APT掺杂剂注入以在晶圆中形成第二类型(例如，n型或p型中的另一种)的器件。
图1示出了三维视图中的finFET 30的实例。FinFET 30包括位于衬底32上的鳍36。衬底32包括隔离区38，并且鳍36从相邻的隔离区38之间突出于相邻的隔离区38之上。衬底32还可包括APT层34，APT层34可用于使用APT掺杂剂原位掺杂finFET 30的各个区。栅极电介质40沿着鳍36的侧壁以及位于鳍36的顶面上方，并且栅电极42位于栅极电介质40上方。鳍36的被栅极电介质40/栅电极42覆盖的部分可被称为finFET 30的沟道区。源极/漏极区44和46相对于栅极电介质40和栅电极42设置在鳍36的相对两侧。图1还示出了在之后附图中所使用的参考横截面。横截面A-A横跨finFET 30的沟道、栅极电介质40和栅电极42。横截面B-B横跨finFET 30的源极/漏极区44或46。横截面C-C垂直于横截面A-A并且沿着鳍36的纵轴并且在例如源极/漏极区44和46之间的电流方向上。为了清楚的目的，之后的附图参照这些参考横截面。
图2至图17C是根据各种实施例的制造finFET的各个中间阶段的截面图，并且图18是图2至图17C中所示工艺的工艺流程。图2和图3示出了除了多个finFET和/或具有多个鳍的finFET之外的图1中示出的参考横截面A-A。如上所讨论的，在图4A至图17C中，沿着相似的横截面A-A示出了以标号“A”结尾的附图；沿着相似的横截面B-B示出了以标号“B”结尾的附图；以及沿着相似的横截面C-C示出了以标号“C”结尾的附图。
图2和图3示出了从衬底向上延伸的半导体鳍的形成。首先参照图2，示出了具有衬底102的晶圆100。衬底102包括用于形成NMOS finFET器件的n沟道金属氧化物半导体(NMOS)区202和用于形成PMOS finFET器件的p沟道金属氧化物半导体(PMOS)区204。区202和204可或可不是连续的，并且根据器件设计，任意数量的器件部件(例如，隔离区、伪部件等(未示出))可形成在NMOS区202和PMOS区204之间。
如图所示，衬底102是包括各个衬底层104、106、108和110的多层衬底。基底衬底层104可以为诸如块体半导体、绝缘体上半导体(SOI)衬底等的半导体衬底，其可被掺杂(例如，用p型或n型掺杂剂)或未被掺杂。通常，SOI衬底包括形成在绝缘层上的半导体材料层。绝缘层可以为例如埋氧(BOX)层、氧化硅层等。绝缘层提供在通常为硅或玻璃衬底的衬底上。还可使用诸如多层衬底或梯度衬底的其他衬底。在一些实施例中，衬底层104的半导体材料可包括硅(Si)、锗(Ge)；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP的合金半导体；或它们的组合。
如图2进一步所示，在基底衬底层104上方可形成附加的衬底层106、108和110。在一些实施例中，可实施各种外延以形成各个衬底层106、108和110。可使用任意合适的外延工艺，诸如，通过金属有机(MO)化学汽相沉积(CVD)、分子束外延(MBE)、液相外延(LPE)、汽相外延(VPE)、选择性外延生长(SEG)、它们的组合等。
衬底层106和110设置在基底衬底层104上方，其中衬底层110设置在衬底层106上方。在一些实施例中，衬底层106具有约20nm至约90nm的厚度T1，以及衬底层110可具有约20nm至约60nm的厚度T3。衬底层106和110可晶格混配(lattice mix-matched)以在产生的finFET器件中产生理想的应变和/或电特性。在一些实施例中，通过为衬底层106和110选择不同的锗原子百分比可实现这种晶格混配。例如，当衬底层110具有比下面的衬底层106低的Ge原子百分比时，可实现拉伸应变，这有益于NMOS器件。因此，在各个实施例中，衬底层110可包括块状Si，而衬底层106包括SiGe以产生拉伸应变。然而，对于PMOS器件，压缩应变可以是有利的，这当衬底层106具有比衬底层110低的Ge原子百分比时可实现。因此，在后续的工艺步骤(例如，见图10A和图10B)中，PMOS区204中的衬底层110可由具有比下面的衬底层106更高的Ge原子百分比的SiGe层代替。
此外，衬底层106中的Ge原子百分比在衬底102的不同区(例如，NMOS区或PMOS区204)中可变化以产生理想类型的应变和/或产生理想的电特性。例如，NMOS区202中的衬底层106可包括具有相对较高的Ge原子百分比的SiGe，例如，该Ge原子百分比为约30％至约80％。相反地，PMOS区204中的衬底层106可包括具有较低Ge原子百分比的SiGe。在这种实施例中，例如，PMOS区204中的衬底层106可包括具有约20％至约45％的Ge原子百分比的SiGe。此外，在一些实施例中，APT层108可以足够薄以不影响产生的finFET器件中诱导的应变。例如，APT层可具有约3nm至约10nm的厚度。
抗穿通(APT)层108设置在衬底层106和110之间。在一些实施例中，APT层108可以是包括适用于防止n型器件中的源极/漏极穿通的APT掺杂剂的半导体层。例如，APT层108可包括硅碳硼(SiCB)、硅硼(SiB)等。例如，APT层108中的n型APT掺杂剂(例如，硼)的浓度可为约1×1018/cm3至约3×1018/cm3。在当APT层18包括SiCB的实施例中，碳原子可防止(或至少减少)APT掺杂剂(例如，硼)扩散进周围的器件层内。在这种实施例中，APT层108中的C的原子浓度可为约0.5％至约1％。此外，APT层108可具有约3nm至约10nm的厚度T2。通过在衬底102中直接外延生长ATP层108，至少可避免对NMOS区202中的器件进行传统的APT掺杂剂注入。例如，上面的衬底层110可基本无任何掺杂剂，并且甚至在后续工艺步骤中可不对衬底层110实施APT掺杂剂注入。产生的NMOS finFET可包括基本未掺杂的沟道区，从而提高产生的器件的电性能和/或特性。
如图2进一步示出的，硬掩模112和光刻胶114可设置在衬底102上方。硬掩模112可包括一个或多个氧化物(例如，氧化硅)层和/或氮化物(例如，氮化硅)层以防止在图案化期间损坏下面的衬底102。可使用诸如原子层沉积(ALD)、化学汽相沉积(CVD)、高密度等离子体CVD(HDP-CVD)、物理汽相沉积(PVD)等的任意合适的沉积工艺形成硬掩模112。光刻胶114可包括使用诸如旋涂等的合适工艺毯式沉积的任意合适的光敏材料。
图3示出了图案化衬底102以形成设置在相邻沟槽118之间的鳍116。在示例实施例中，可首先通过使用光掩模将光刻胶114暴露于光来图案化光刻胶114。然后，可根据使用的是正性光刻胶或负性光刻胶来去除光刻胶114的暴露或未暴露的部分。
然后，可将光刻胶114的图案转印到硬掩模112(例如，使用合适的蚀刻工艺)。随后，例如，在蚀刻工艺期间使用硬掩模112作为图案化掩模将沟槽118图案化至下面的衬底102内。蚀刻衬底102可包括可接受的蚀刻工艺，诸如，反应离子蚀刻(RIE)、中性束蚀刻(NBE)等或它们的组合。蚀刻可以是各向异性的。随后，例如，在灰化和/或湿剥离工艺中去除光刻胶114。还可去除硬掩模112。因此，在晶圆100中形成鳍116。鳍116从相邻沟槽118之间的基底衬底层104向上延伸。
图4A至图5B示出了在NMOS区202中的鳍116上可选地形成拉伸应变产生部件(例如，介电层122，例如，见图5A)。参照图4A和图4B，硬掩模120形成在晶圆102的部分上方。此外，图4A示出了横跨沟道区的晶圆100的横截面(图1的横截面A-A)，而图4B示出了处于相同的制造阶段的横跨源极/漏极区的晶圆100的横截面(图1的横截面B-B)。如图所示，硬掩模120覆盖PMOS区204中的鳍116的顶面和侧壁以及NMOS区202中的鳍116的源极/漏极区。然而，图案化硬掩模120以暴露出NMOS区202中的鳍116的沟道区。硬掩模120可包括任意合适的介电材料(例如，氮化物或氧化物)，例如，可使用光刻和蚀刻的组合对其进行图案化。
图5A和图5B示出了在NMOS区202中的鳍116的部分上形成介电层122。通过氧化NMOS区202中的衬底层106可形成介电层122。在这种实施例中，介电层122可包括半导体氧化物(例如，SiGe氧化物)。可使用任意合适的氧化工艺，诸如选择地氧化衬底层106内的Ge但不氧化其他衬底层104、108或110的半导体材料(例如，块状Si、SiB或SiCB)的湿氧化工艺。在一些示例实施例中，湿氧化工艺可包括将晶圆100保持在约400℃至约500℃的温度下，同时在保持在约1Atm的气压的环境下将纯水蒸气供给至晶圆100，持续时间介于约三十分钟和约一小时之间。例如，产生的介电层122可具有约3nm至约10nm的厚度T4(在最厚点处)。还可使用其他合适的氧化工艺。
氧化工艺在NMOS区202中的沟道区的沟槽118内形成介电层122。介电层122可在其上形成有介电层122的鳍116中产生拉伸应变。产生的拉伸应变可更适于NMOS器件的沟道区。因此，可将介电层122的形成限制在NMOS区202的沟道区，并且介电层122可不形成在PMOS区204中或NMOS区202中的源极/漏极区下面。通过配置硬掩模120可有利于介电层122的选择性形成。例如，在氧化工艺期间，硬掩模120可掩蔽PMOS区204中的鳍116和NMOS区202中的鳍116的源极/漏极区中的鳍116。在形成介电层122之后，可去除硬掩模120。
接着参照图6A和图6B，可沿着沟槽118的底面和侧壁设置诸如扩散势垒层的衬垫124。在一些实施例中，衬垫124可包括半导体(例如，硅)氮化物、半导体(例如，硅)氧化物、热半导体(例如，硅)氧化物、半导体(例如，硅)氮氧化物、聚合物电介质、它们的组合等。衬垫124的形成可包括任意合适的方法，诸如，原子层沉积(ALD)、CVD、高密度等离子体(HDP)CVD、物理汽相沉积(PVD)等。
在图7A和图7B中，可用诸如氧化硅等的介电材料填充沟槽118。在一些实施例中，将硅烷(SiH4)和氧气(O2)用作反应前体，使用高密度等离子体(HDP)CVD工艺可形成所产生的STI区126。在其他实施例中，可使用次大气压CVD(SACVD)工艺或高高宽比工艺(HARP)形成STI区126，其中，工艺气体可包括正硅酸乙酯(TEOS)和臭氧(O3)。在又一些其他实施例中，使用旋涂电介质(SOD)工艺(诸如，氢倍半硅氧烷(HSQ)或甲基倍半硅氧烷(MSQ))可形成STI区126。可实施退火(或其他合适的工艺)以固化STI区126的材料，并且衬垫124在退火期间可防止(或至少减少)鳍116中的半导体材料(例如，Si和/或Se)扩散至周围的STI区126内。可使用其他工艺和材料。可使用化学机械抛光(CMP)或回蚀刻工艺以使STI区126、衬垫124和鳍116的顶面齐平。
图8A和图10B示出了在PMOS区204中用半导体层134(例如，具有较高的Ge原子百分比)代替半导体层110。图8A和图8B示出了去除PMOS区204中的鳍116的顶部(例如，半导体层110部分)。在一些实施例中，在去除PMOS区204中的半导体层110期间可掩蔽(例如，通过硬掩模128)NMOS区202。因此，在不影响NMOS区202的部件的情况下可选择性地处理PMOS区204。去除PMOS区204中的半导体层110可包括任意合适的工艺，诸如，干蚀刻、湿蚀刻、RIE等。去除半导体层110部分限定了相邻STI区126之间的沟槽132，并且这种沟槽132可暴露PMOS区204中的APT层108。
如由图8A和图8B进一步示出的，在暴露PMOS区204中的APT层108之后，可实施APT掺杂剂注入工艺(由箭头130所示)。APT掺杂剂注入工艺可将p型APT掺杂剂注入暴露的APT层108中。在一些实施例中，注入的APT掺杂剂可适用于防止p型器件中的源极/漏极穿通。例如，使用的p型APT掺杂剂可包括磷等。
在一些实施例中，可以以适合的高浓度注入p型APT掺杂剂以抑制在APT层108中原始发现的n型APT掺杂剂(例如，硼)。例如，注入的p型APT掺杂剂(例如，磷)与n型APT掺杂剂(例如，硼)的浓度的比率可至少为约2:1。作为另一个实例，在当APT层108中的n型APT掺杂剂(例如，硼)的浓度可为约1×1018/cm3至约3×1018/cm3时的实施例中，注入APT层108中的p型APT掺杂剂(例如，磷)的浓度可为约2×1018/cm3至约6×1018/cm3。在注入之后，PMOS区204中的产生的APT层108(图9A和图9B中标示为108P)可包括硅碳硼磷(SiCBP)、硅硼磷(SiBP)等。在p型APT掺杂剂注入期间，可掩蔽NMOS区202，并且因此甚至在注入之后NMOS区202中的鳍116的部分(例如，衬底层110)可保持基本未掺杂。
图9A和图9B示出了可选地使PMOS区204中的衬垫124凹进。衬垫124的凹进可包括任意合适的工艺，诸如，干蚀刻、湿蚀刻、RIE等。可从PMOS区204中的APT层108P的顶面凹进衬垫124。在后续工艺步骤中(例如，在图10A和图10B中)，在沟槽132中可生长半导体层134。在越过APT层108P凹进衬垫124的实施例中，半导体层134可生长在APT层108P的多个表面(例如，横向顶面和侧壁表面)上。这种增加的接合面积可减少APT层108P和半导体层134之间的界面处的空隙和其他界面缺陷的出现。
随后，在图10A和图10B中，实施外延以在沟槽132中外延生长半导体层134。在各个实施例中，半导体层134可与下面的衬底层106晶格混配以实现压缩应变，其可有益于p型器件。例如，半导体层134可包括比下面的衬底层106更高的Ge原子百分比。在这种实施例中，衬底层106可包括具有约20％至约45％的Ge原子百分比的SiGe，而半导体层134可包括具有约45％至约100％的Ge原子百分比的SiGe或Ge。半导体层134的外延可过度生长STI区126的顶面，并且可实施平坦化技术(例如，化学机械抛光(CMP)工艺)以使半导体层134的顶面和STI区126的顶面齐平。此外，半导体层134的材料(例如，SiGe或Ge)可在产生的p型器件的沟道区中提供增强的电性能(例如，提高的迁移率)。在一些实施例中，在形成之后，半导体层134可包括浓度为约2×1017/cm3至约2×1018/cm3的掺杂剂(例如，p型APT掺杂剂)，由于在APT层108P上方外延半导体层134，掺杂剂可形成在半导体层134中。然而，甚至在这种实施例中，由于硬掩模128，半导体层110可保持未掺杂。在外延半导体层134之后，可去除硬掩模128。
在图11A和图11B中，凹进STI区126，使得半导体层110和134的顶部高于STI区126的顶面。凹进STI区126可包括化学蚀刻工艺，例如，在具有或不具有等离子体的情况下使用氨(NH3)与氢氟酸(HF)或三氟化氮(NF3)的组合作为反应溶液。当HF用作反应溶液时，HF的稀释率可介于约1:50至约1:100之间。还可凹进NMOS区202中的衬垫124以与凹进的STI区126基本齐平。在凹进之后，暴露出鳍116中的半导体层110和134的顶面和侧壁。由此在鳍116中形成沟道区136(例如，沿着横截面A-A的半导体层110和134的暴露部分)。在完成的finFET结构中，栅极包绕且覆盖这种沟道区136的侧壁(例如，见图1和图17A)。例如，由于包含APT层108，至少NMOS区202中的沟道区136可不被掺杂并且基本无任何掺杂剂，因为在无APT注入工艺的情况下形成APT层108。
图12A至图12C示出了在沟道区136的顶面和侧壁上形成栅极堆叠件140。栅极堆叠件140包括共形的伪氧化物142和位于伪氧化物142上方的伪栅极144。伪栅极144可包括例如多晶硅，但是还可使用诸如金属硅化物、金属氮化物等的材料。每个栅极堆叠件140还可包括位于伪栅极144上方的硬掩模146。例如，硬掩模146可包括氮化硅或氧化硅。在一些实施例中，每个栅极堆叠件140可横跨于多个半导体鳍116和/或STI区126上方。栅极堆叠件140还可具有基本垂直于半导体鳍116的纵向的纵向(例如，见图1)。如图12B所示，形成栅极堆叠件140还可包括在鳍116的源极/漏极区中的鳍116的侧壁和顶面上方(例如，半导体层110和134的暴露部分上方)形成伪氧化物142。
还如图12C所示，在栅极堆叠件140的侧壁上形成栅极间隔件148。在一些实施例中，栅极间隔件148由氧化硅、氮化硅、碳氮化硅等形成。此外，栅极间隔件148可具有多层结构，例如，具有位于氧化硅层上方的氮化硅层。
参照图13A至图13C，实施蚀刻以蚀刻半导体鳍116的未被硬掩模146或栅极间隔件148覆盖的部分。蚀刻还可去除未被硬掩模146覆盖的伪氧化物142的部分，其可对应于位于鳍116的源极/漏极区中的半导体层110和134上方的伪氧化物142的部分(参见图13B)。在蚀刻之后，可将伪氧化物142的剩余部分用作主侧壁(MSW)间隔件152，以在后续工艺步骤中限定源极/漏极外延区。可选地，可越过STI区126的顶面凹进鳍116，并且STI区126的暴露侧壁可用于限定源极/漏极外延区。在这种实施例中，可省略间隔件152。因此，在相邻的间隔件152之间形成沟槽150。沟槽150位于伪栅极堆叠件140的相对两侧上(见图13C)。在形成沟槽150之后，可对鳍116的暴露表面(例如，凹进的半导体层110和134)实施轻掺杂漏极(LDD)和退火工艺。尽管沟槽150示出为暴露半导体层110和134的凹进表面，但是，在可选实施例中，沟槽150还可暴露下面的APT层108和108P。
接着，如图14A至图14C所示，通过在沟槽150中选择性地生长半导体材料形成外延区154。在一些实施例中，外延区154包括硅(无锗)、锗(无硅)、硅锗、硅磷等。例如，外延区154还可由锗原子百分比大于约95％的纯或基本纯的锗形成。硬掩模146和间隔件152可掩蔽晶圆100的区域以限定用于形成外延区154(例如，仅位于鳍116的暴露部分上)的区域。在以外延区154填充沟槽150之后，源极/漏极区154的进一步外延生长导致外延区154横向扩展并且可开始形成小平面。此外，由于源极/漏极区154的横向生长，STI区126的一些部分可位于外延区154的部分下面并且对准于外延区154的部分。
在外延步骤之后，外延区154可在PMOS区204中注入有p型杂质(例如，硼或BF2)并且在NMOS区202中注入有n型杂质(例如，磷或砷)以形成源极/漏极区，其也可使用参考标号154表示。可选地，当生长外延区154以形成源极/漏极区时，可原位掺杂p型或n型杂质。源极/漏极区154位于栅极堆叠件140的相对两侧上(见图14C)并且可为STI区126的表面的覆盖部分和重叠部分(见图14B)。此外，具有适当类型的APT掺杂剂(例如，NMOS区202中的n型APT掺杂剂和PMOS区204中的p型APT掺杂剂)的APT层108/108P位于源极/漏极区154下方，并且APT层108/108P可防止或至少减少源极/漏极穿通。
图15A至图15C示出了在形成层间电介质156之后的晶圆100。ILD 156可包括使用例如可流动化学汽相沉积(FCVD)形成的可流动氧化物。可实施CMP(或其他合适的平坦化工艺)以使ILD 156、栅极堆叠件140和栅极间隔件148的顶面彼此齐平。尽管图15A至图15C中未详细示出，但是在ILD层156和源极/漏极区154、栅极堆叠件140和/或栅极间隔件148之间可设置各种中间层(例如，缓冲层和/或蚀刻停止层)。
图16A至图16C示出了在暴露出鳍116的沟道区136之后的晶圆100的变化图。暴露沟道区136可包括从沟道区136的侧壁和顶面去除栅极堆叠件140(包括硬掩模146、伪栅极144和伪氧化物142)。栅极堆叠件140的去除可在栅极间隔件148之间限定沟槽160(见图16C)。在去除栅极堆叠件140期间，硬掩模158可用于掩蔽ILD 156和源极/漏极区154。因此，可在不图案化ILD 156或源极/漏极区154的情况下去除栅极堆叠件140。
接着，参照图17A至图17B，在沟槽160中形成栅极堆叠件162。例如，栅极电介质164形成为沟槽160中的共形层。栅极电介质164可覆盖沟道区136的顶面和侧壁(见图17A)。根据一些实施例，栅极电介质164包括氧化硅、氮化硅或它们的多层。在可选实施例中，栅极电介质164包括高k介电材料。在这种实施例中，栅极电介质164可以具有大于约7.0的k值并且可包括铪(Hf)、铝(Al)、锆(Zr)、镧(La)、镁(Mg)、钡(Ba)、钛(Ti)、铅(Pb)的金属氧化物或硅酸盐、它们的组合等。栅极电介质164的形成方法可包括分子束沉积(MBD)、ALD、等离子体增强CVD(PECVD)等。
接着，通过用导电材料填充沟槽160的剩余部分而在栅极电介质164上方形成导电栅电极166。栅电极166可包括含金属的材料，诸如，氮化钛(TiN)、氮化钽(TaN)、碳化钽(TaC)、钴(Co)、钌(Ru)、铝(Al)、它们的组合、它们的多层等。栅极电介质164和栅电极166的形成可溢出沟槽160并且覆盖ILD 156的顶面。随后，实施平坦化(例如，CMP)以去除栅极电介质164和栅电极166的过多部分。产生的栅极电介质164和栅电极166的剩余部分在产生的finFET的沟道区136上方形成栅极堆叠件162。然后，可使用任意合适的工艺在ILD 156中形成例如包括镍(Ni)、钨(W)等的附加部件(诸如，源极/漏极接触件168)以与源极/漏极区154电连接。
图18示出了根据一些实施例的用于形成半导体器件(例如，finFET)的示例工艺流程300。在步骤302中，在半导体衬底(例如，衬底102)中外延生长APT层(例如，APT层108)。APT层可包括第一类型的APT掺杂剂。例如，在一些实施例中，APT层可包括n型APT掺杂剂，并且在这种实施例中，APT层可包括SiB或SiCB。在步骤304中，使用任意合适的工艺(诸如，实施附加的外延)在APT层上方形成第一半导体层(例如，半导体层110)。第一半导体层可基本无任何掺杂剂，并且第一半导体层的至少一部分可用作产生的finFET的沟道区(例如，沟槽区136)。
接着，在步骤306中，图案化从半导体衬底向上延伸的第一和第二鳍(例如，NMOS区202和PMOS区204中的鳍116)。每个鳍可包括第一半导体层部分和APT层部分。在步骤308中，例如，通过去除第二鳍的第一半导体层部分暴露出第二鳍的APT层部分。在步骤310中，在第二鳍的APT层部分中注入不同类型的APT掺杂剂。例如，当原始APT层包含n型APT掺杂剂时，步骤310中注入的APT掺杂剂可包括p型APT掺杂剂。在一些实施例中，步骤310可包括注入浓度足够高的APT掺杂剂以抑制源自APT层的APT掺杂剂。在注入之后，例如，第二鳍中的APT层可包括SiBP或SiCBP。在步骤312中，在第二鳍中的APT上方形成第二半导体层(例如，半导体层134)。
在各种实施例中，在步骤308至步骤312期间掩蔽第一鳍(例如，NMOS区202的鳍116)。因此，第一鳍仍可包括可保持基本未掺杂的第一半导体层。最后，在步骤314中，在第一和第二鳍的顶面和侧壁上形成导电栅极堆叠件。例如，导电栅极堆叠件可形成在第一鳍的第一半导体层部分的顶面和侧壁上以及第二鳍的第二半导体层部分上。诸如源极/漏极区的附加部件还可邻近导电栅极堆叠件形成，并且APT层可设置在这种源极/漏极区下面以防止(或至少减少)产生的finFET器件中的源极/漏极穿通。
各种实施例包括在半导体衬底中外延生长APT层。APT层提供原位APT掺杂剂，其可防止来自源极/漏极区的n型和p型掺杂剂穿通进各种finFET器件的下面的半导体层内。附加的半导体层可形成在APT层上方，并且附加的半导体层的部分可用作产生的finFET器件的沟道区。包含具有原生APT掺杂剂的APT层消除了在这种finFET器件的鳍中的至少第一类型(例如，n型或p型)的器件中的APT注入，这样可产生未掺杂的沟道区和提高的电功能。仍可实施APT掺杂剂注入以在晶圆中形成第二类型(例如，n型或p型的另一种)的器件。
根据实施例，一种半导体器件包括从半导体衬底向上延伸的鳍。鳍包括具有APT掺杂剂的抗穿通(APT)层和位于APT层上方的沟道区。沟道区基本无APT掺杂剂。半导体器件还包括位于沟道区的侧壁和顶面上的导电栅极堆叠件。
根据另一个实施例，一种半导体器件包括第一finFET和第二finFET。第一finFET包括具有第一类型的第一APT掺杂剂的第一抗穿通(APT)层、位于第一APT层上方的第一半导体层、位于第一半导体层的侧壁和顶面上的第一导电栅极堆叠件、和邻近第一导电栅极堆叠件的第一源极和漏极区。第二finFET包括具有第一类型的第二APT掺杂剂和不同于第一类型的第二类型的第三APT掺杂剂的第二APT层。第二finFET还包括位于第二APT层上方的第二半导体层、位于第二半导体层的侧壁和顶面上的第二导电栅极堆叠件、和邻近第二导电栅极堆叠件的第二源极和漏极区。
根据再一个实施例，一种形成半导体器件的方法包括在半导体衬底上方外延生长抗穿通(APT)层和在APT层上方形成半导体层。APT层包括第一APT掺杂剂。图案化半导体层和APT层以限定从半导体衬底向上延伸的鳍。第一鳍包括第一APT层部分和第一半导体层部分。该方法还包括在第一鳍的第一半导体层部分的顶面和侧壁上形成导电栅极堆叠件。
上面论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个方面。本领域的技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域的技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、更换以及改变。

Claims (10)

1.一种半导体器件，包括：
第一鳍，从半导体衬底向上延伸，其中，所述第一鳍包括
第一抗穿通(APT)层，包括APT掺杂剂；和
第一沟道区，位于所述第一APT层上方，其中，所述第一沟道区基本不含所述APT掺杂剂；以及
导电栅极堆叠件，位于所述第一沟道区的侧壁和顶面上。
2.根据权利要求1所述的半导体器件，其中，所述第一APT层包括硅硼(SiB)或硅碳硼(SiCB)。
3.根据权利要求1所述的半导体器件，还包括邻近所述导电栅极堆叠件的源极和漏极区，其中，所述第一APT层设置在所述源极和漏极区下面。
4.根据权利要求1所述的半导体器件，还包括从所述半导体衬底向上延伸的第二鳍，其中，所述第二鳍包括：
第二APT层，包括n型APT掺杂剂和p型APT掺杂剂；以及
第二沟道区，位于所述第二APT层上方。
5.根据权利要求4所述的半导体器件，其中，所述第二APT层中的所述p型APT掺杂剂的第一浓度与所述第二APT层中的所述n型APT掺杂剂的第二浓度的比率至少为约2:1。
6.根据权利要求4所述的半导体器件，其中，所述第二APT层包括硅硼磷或硅碳硼磷。
7.一种半导体器件，包括：
第一鳍式场效应晶体管(finFET)，包括：
第一抗穿通(APT)层，包括第一类型的第一APT掺杂剂；和
第一半导体层，位于所述第一APT层上方；
第一导电栅极堆叠件，位于所述第一半导体层的侧壁和顶面上；和
第一源极和漏极区，邻近所述第一导电栅极堆叠件；以及
第二finFET，包括：
第二APT层，包括第一类型的第二APT掺杂剂和不同于所述第一类型的第二类型的第三APT掺杂剂；
第二半导体层，位于所述第二APT层上方；
第二导电栅极堆叠件，位于所述第二半导体层的侧壁和顶面上；和
第二源极和漏极区，邻近所述第二导电栅极堆叠件。
8.根据权利要求7所述的半导体器件，其中，所述第一半导体层基本未掺杂任何APT掺杂剂。
9.根据权利要求7所述的半导体器件，其中，所述第一APT层包括硅硼(SiB)或硅碳硼(SiCB)，并且其中，所述第二APT层包括硅硼磷(SiBP)或硅碳硼磷(SiCBP)。
10.一种形成半导体器件的方法，所述方法包括：
在半导体衬底上方形成抗穿通(APT)层，其中，所述APT层包括第一APT掺杂剂；
在所述APT层上方形成半导体层；
图案化所述半导体层和所述APT层以限定从所述半导体衬底向上延伸的第一鳍，其中，所述第一鳍包括第一APT层部分和第一半导体层部分；以及
在所述第一鳍的所述第一半导体层部分的顶面和侧壁上形成导电栅极堆叠件。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735674A (zh) * 2017-04-20 2018-11-02 台湾积体电路制造股份有限公司 用于源极/漏极外延区的灵活合并方案
CN109216277A (zh) * 2017-06-29 2019-01-15 中芯国际集成电路制造(上海)有限公司 半导体装置的制造方法
CN109728093A (zh) * 2017-10-31 2019-05-07 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN110957221A (zh) * 2018-09-27 2020-04-03 台湾积体电路制造股份有限公司 半导体器件及其形成方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3203529B1 (en) * 2013-09-25 2022-12-21 Tahoe Research, Ltd. Isolation well doping with solid-state diffusion sources for finfet architectures
KR102395108B1 (ko) * 2015-06-27 2022-05-09 인텔 코포레이션 선택적 산화에 의한 다중-높이 finfet 디바이스
US9871100B2 (en) 2015-07-29 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Trench structure of semiconductor device having uneven nitrogen distribution liner
US9564437B1 (en) * 2015-08-25 2017-02-07 International Business Machines Corporation Method and structure for forming FinFET CMOS with dual doped STI regions
WO2017052612A1 (en) 2015-09-25 2017-03-30 Intel Corporation Methods of doping fin structures of non-planar transistor devices
US9960273B2 (en) * 2015-11-16 2018-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
US9589965B1 (en) * 2016-01-22 2017-03-07 Globalfoundries Inc. Controlling epitaxial growth over eDRAM deep trench and eDRAM so formed
US9847330B2 (en) * 2016-02-05 2017-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9508604B1 (en) * 2016-04-29 2016-11-29 Globalfoundries Inc. Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers
CN107799421B (zh) * 2016-09-05 2021-04-02 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN107958873B (zh) 2016-10-18 2020-11-27 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
US9984937B1 (en) * 2017-04-20 2018-05-29 International Business Machines Corporation Vertical silicon/silicon-germanium transistors with multiple threshold voltages
CN109427676B (zh) * 2017-08-23 2021-08-13 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
KR102465356B1 (ko) 2018-02-09 2022-11-10 삼성전자주식회사 반도체 소자
US10840355B2 (en) * 2018-05-01 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Increasing source/drain dopant concentration to reduced resistance
US11257908B2 (en) * 2018-10-26 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with stacked semiconductor layers as channels
US11437372B2 (en) * 2019-09-26 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Liner structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426915A (zh) * 2012-05-16 2013-12-04 台湾积体电路制造股份有限公司 具有自对准互连件的半导体器件
CN103531477A (zh) * 2012-07-05 2014-01-22 台湾积体电路制造股份有限公司 具有位于下方的嵌入式抗穿通层的FinFET方法和结构
US20140057403A1 (en) * 2011-11-23 2014-02-27 United Microelectronics Corp. Method for fabricating semiconductor device
US20140191315A1 (en) * 2013-01-09 2014-07-10 Broadcom Corporation Multigate metal oxide semiconductor devices and fabrication methods

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7439594B2 (en) 2006-03-16 2008-10-21 Micron Technology, Inc. Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors
US8310013B2 (en) 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US8610201B1 (en) 2012-08-16 2013-12-17 Kabushiki Kaisha Toshiba FinFET comprising a punch-through stopper
US8841188B2 (en) 2012-09-06 2014-09-23 International Business Machines Corporation Bulk finFET with controlled fin height and high-K liner
US8759874B1 (en) 2012-11-30 2014-06-24 Stmicroelectronics, Inc. FinFET device with isolated channel

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140057403A1 (en) * 2011-11-23 2014-02-27 United Microelectronics Corp. Method for fabricating semiconductor device
CN103426915A (zh) * 2012-05-16 2013-12-04 台湾积体电路制造股份有限公司 具有自对准互连件的半导体器件
CN103531477A (zh) * 2012-07-05 2014-01-22 台湾积体电路制造股份有限公司 具有位于下方的嵌入式抗穿通层的FinFET方法和结构
US20140191315A1 (en) * 2013-01-09 2014-07-10 Broadcom Corporation Multigate metal oxide semiconductor devices and fabrication methods

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735674A (zh) * 2017-04-20 2018-11-02 台湾积体电路制造股份有限公司 用于源极/漏极外延区的灵活合并方案
US10985167B2 (en) 2017-04-20 2021-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Flexible merge scheme for source/drain epitaxy regions
US11856743B2 (en) 2017-04-20 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Flexible merge scheme for source/drain epitaxy regions
CN109216277A (zh) * 2017-06-29 2019-01-15 中芯国际集成电路制造(上海)有限公司 半导体装置的制造方法
US10763259B2 (en) 2017-06-29 2020-09-01 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device manufacturing method
CN109216277B (zh) * 2017-06-29 2021-03-16 中芯国际集成电路制造(上海)有限公司 半导体装置的制造方法
CN109728093A (zh) * 2017-10-31 2019-05-07 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN109728093B (zh) * 2017-10-31 2023-05-16 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN110957221A (zh) * 2018-09-27 2020-04-03 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN110957221B (zh) * 2018-09-27 2023-09-22 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11935955B2 (en) 2018-09-27 2024-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of forming same

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