CN109599372B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109599372B
CN109599372B CN201811139732.3A CN201811139732A CN109599372B CN 109599372 B CN109599372 B CN 109599372B CN 201811139732 A CN201811139732 A CN 201811139732A CN 109599372 B CN109599372 B CN 109599372B
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wall portion
semiconductor device
recess
insulating substrate
press
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CN109599372A (zh
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石桥秀俊
浅田晋助
木村义孝
江草稔
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Mitsubishi Electric Corp
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Abstract

抑制半导体装置整体的高度尺寸扩大，且兼顾半导体装置的电绝缘性和压接端子的变形容许度。半导体装置具备绝缘基板、设于绝缘基板上的半导体元件、壳体框、压接端子、设于绝缘基板上的内壁部内侧而封装半导体元件的封装材料。壳体框在绝缘基板的俯视观察时以包围半导体元件的方式设于绝缘基板周缘。壳体框由绝缘物构成，具备外壁部、与外壁部相比设于绝缘基板中央侧的内壁部、夹在外壁部和内壁部间而与外壁部及内壁部一起构成凹部的凹部底面。压接端子具备经由配线与半导体元件连接的根部、从根部立起的主体部、设于主体部上端的压入部，根部埋入至凹部底面，主体部从凹部底面立起，从而主体部在内壁部和外壁部之间延伸，压入部凸出至凹部的上方。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
当前，例如像日本特开2015-023226号公报所记载的那样，已知一种半导体装置，该半导体装置构成为，信号端子从在壳体框设置的凹部的底面立起。上述现有的半导体装置中的信号端子不是压接端子而是通常的端子。凹部被认为是为了供连接器插入而设置的。
专利文献1：日本特开2015-023226号公报
压接端子具备：根部；主体部，其从根部立起；以及压入部，其设置于主体部的端部。设置于压接端子的压入部被插入至印刷配线基板等的通孔。如果压入部插入至通孔，则通孔和压入部彼此强力挤压。利用彼此挤压的力，能够在印刷配线基板等与压接端子之间得到机械连接以及电连接。
优选压接端子能够在承受负载时容许一定程度的变形。如果对这一点进行说明，则是在向印刷配线基板的通孔嵌入压接端子的压入部时，对压入部施加负载。该向压入部的负载试图将压接端子沿轴向压缩。另外，在通孔与压入部存在位置偏离的情况下，还作用有使压接端子沿横向挠曲的力。对应于这些力，主体部作为弹簧而挠曲，从而压接端子能够承受上述的各种力。压接端子的主体部越长，越能够提高向压入部施加了负载时的压接端子的变形容许度。由于变形容许度是压接端子的连接原理上所需要的功能，因此，在现在的连接器用端子中不被重视。
在半导体元件由封装材料覆盖的情况下，封装材料越厚越能够提高半导体元件的绝缘性。如果使封装材料变厚，则封装材料的上表面也变高。在使压接端子从封装材料的上表面立起的情况下，如果使封装材料变厚，则压接端子的主体部的大部分被埋没于树脂。如果作为其对策而采用主体部从封装材料的上表面足够长地凸出的构造，则由于压接端子的长度和封装材料厚度的合计而使得半导体装置整体的高度尺寸增大。如上述所示，存在下述问题，即，如果要兼顾压接端子的变形容许度和由封装树脂实现的电绝缘性的确保这两者，则半导体装置的高度尺寸扩大。
发明内容
本发明就是为了解决上述课题而提出的，其目的在于提供一种以如下方式得到了改善的半导体装置，即，在抑制半导体装置的高度尺寸扩大的同时，兼顾半导体装置的电绝缘性和压接端子的变形容许度这两者。
本发明涉及的半导体装置，具备：
绝缘基板；
半导体元件，其设置于所述绝缘基板之上；
壳体框，其在所述绝缘基板的俯视观察时以包围所述半导体元件的方式设置于所述绝缘基板的周缘，由绝缘物构成，具备外壁部、内壁部、以及凹部底面，该内壁部与所述外壁部相比设置于所述绝缘基板的中央侧，该凹部底面夹在所述外壁部和所述内壁部之间，与所述外壁部以及所述内壁部一起构成凹部；
压接端子，其具备根部、主体部、以及压入部，该根部经由配线与所述半导体元件连接，该主体部从所述根部立起，该压入部设置于所述主体部的上端，所述根部埋入至所述凹部底面，所述主体部从所述凹部底面立起，从而所述主体部在所述内壁部和所述外壁部之间延伸，所述压入部凸出至所述凹部的上方；以及
封装材料，其设置于所述绝缘基板之上的所述内壁部的内侧，对所述半导体元件进行封装。
发明的效果
根据本发明，使用设置于壳体框的内壁部和凹部，能够兼顾以下两者，即：将封装材料设置得厚以及保证压接端子的主体部可自由变形。其结果，能够在抑制半导体装置的高度尺寸扩大的同时，兼顾半导体装置的电绝缘性和压接端子的变形容许度这两者。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。
图2是表示本发明的实施方式1涉及的半导体装置的侧视图。
图3是本发明的实施方式1涉及的半导体装置的沿图1的A-A线的剖视图。
图4是本发明的实施方式1涉及的半导体装置的沿图3的B-B线的剖视图。
图5是表示本发明的实施方式1涉及的半导体装置的压接端子的斜视图。
图6是本发明的实施方式1的变形例涉及的半导体装置的剖视图。
图7是本发明的实施方式1的变形例涉及的半导体装置的剖视图。
图8是本发明的实施方式2涉及的半导体装置的与图1的A-A线位置对应的剖视图。
图9是本发明的实施方式2的变形例涉及的半导体装置的剖视图。
标号的说明
1、101 半导体装置
2、102 壳体框
2a、12 内壁部
2b 凹部底面
2c 外壁部
2d 凹部
3 绝缘基板
4 基座板
6 绝缘层
7 电路图案
8 接合剂
9 半导体元件
10 金属线
11 封装材料
11a 上表面
20 压接端子
21 压入部
22 开口部
23 主体部
23a 缩颈部
24 根部
30 印刷配线基板
30a 通孔
102e 台阶
102f 外框部
120 外部电极端子
130 盖
具体实施方式
实施方式1
图1是表示本发明的实施方式1涉及的半导体装置1的俯视图。图2是表示本发明的实施方式1涉及的半导体装置1的侧视图。图3是本发明的实施方式1涉及的半导体装置1的沿图1的A-A线的剖视图。
图1以及图2示出半导体装置1的外观。半导体装置1具备：壳体框2；绝缘基板3；半导体元件9；封装材料11；以及压接端子20。为方便起见，一边参照上下方向一边对半导体装置1的构造进行说明。该上下方向是将绝缘基板3作为基准而确定的相对的方向。该上下方向只不过示出了相对于绝缘基板3的相对的位置关系，并不是限定与铅垂方向以及水平方向的关系。半导体装置1的各构造与铅垂方向、水平方向之间的关系是根据半导体装置1的安装方向而决定的。在图1以及图2等中，为方便起见，示出x y z正交坐标轴。z方向表示半导体装置1的“上”方向，该上方向即是半导体装置1的“高度”方向。z方向也是表示半导体装置1所具备的各构造的“厚度”的方向。x方向是表示半导体装置1的“长度尺寸”的方向，y方向是表示半导体装置1的“宽度尺寸”的方向。
参照图3，对半导体装置1的内部构造进行说明。绝缘基板3以及壳体框2构成了半导体装置1的壳体。绝缘基板3具备：基座板4；绝缘层6，其设置于基座板4的表面；以及电路图案7，其设置于绝缘层6之上。绝缘基板3也是在表面具有用于安装半导体元件9的电路图案7的电路基板。基座板4以及电路图案7的材质是金属。作为该金属材料，具体地说，也可以使用铝或者铜。对于绝缘层6，也可以使用向环氧树脂等加入了陶瓷类填料而得到的材料。
半导体元件9设置于绝缘基板3之上。具体地说，半导体元件9经由接合剂8而安装于在绝缘基板3之上设置的电路图案7之上。作为接合剂8的一个例子，是焊料。半导体元件9由铝线等金属线10进行配线。对于半导体元件9，也可以使用开关元件，具体地说，也可以使用IGBT或者MOS－FET。半导体元件9的材料既可以是硅，也可以是与硅相比带隙更大的宽带隙半导体。宽带隙半导体也可以是SiC、GaN或者金刚石。由半导体元件9以及绝缘基板3的电路构成逆变器电路。虽然未图示，但构成逆变器电路的二极管元件也可以内置于半导体装置1。
壳体框2在图1所示的绝缘基板3的俯视观察时，以包围半导体元件9的方式设置于绝缘基板3的周缘。壳体框2具备内壁部2a、凹部底面2b以及外壁部2c。内壁部2a相比于外壁部2c设置于绝缘基板3的中央侧。凹部底面2b夹在外壁部2c和内壁部2a之间，与外壁部2c以及内壁部2a一起构成凹部2d。壳体框2由绝缘物构成。优选壳体框2由具有高绝缘性能的工程塑料制作而成。
图4是本发明的实施方式1涉及的半导体装置1的沿图3的B-B线的剖视图。压接端子20具备：根部24；主体部23，其从根部24立起；以及压入部21，其设置于主体部23的上端。压接端子20的概略形状为L字型，固定于壳体框2。根部24和主体部23的连结部埋入至凹部底面2b。根部24的前端从壳体框2露出。根部24的前端经由金属线10与半导体元件9连接。主体部23从凹部底面2b直立地立起。主体部23在内壁部2a和外壁部2c之间延伸。压入部21凸出至凹部2d的上方。优选压接端子20由铜合金制作而成，优选在其表面形成Ni或者Sn等的镀层。此外，虽然在图4中是简化地图示的，但在实施方式1中，如后述的图5所示，在主体部23设置有缩颈部23a。
压入部21呈在中央具有开口部22的椭圆环状的构造。具有开口部22的压入部21发挥压接功能。通过将压入部21压入至印刷配线基板30的通孔30a，从而压接端子20与通孔30a电连接。压接端子20作为主电路以及控制电路的端子发挥功能。
图5是表示本发明的实施方式1涉及的半导体装置1的压接端子20的斜视图。主体部23具备缩颈部23a。缩颈部23a是主体部23的一部分的宽度变窄的部分。缩颈部23a在凹部2d的内侧与凹部底面2b相比位于上方。
半导体元件9通过由封装材料11覆盖，从而被绝缘封装。封装材料11填充至绝缘基板3之上的内壁部2a的内侧。封装材料11也可以设置至与内壁部2a的上端相同的高度，封装材料11的上表面11a也可以比内壁部2a的上端低。无论哪种情况，封装材料11的上表面11a都设置于比凹部底面2b高的位置。对于封装材料11，也可以使用加入了具有绝缘性能的二氧化硅的硬质环氧树脂，或者硅凝胶等。
在图3以及图4中，为方便起见，通过虚线对印刷配线基板30进行图示。在使半导体装置1实际工作时，印刷配线基板30配置为与封装材料11的上表面11a重叠。印刷配线基板30具备通孔30a。压接端子20的压入部21被插入至通孔30a。
根据半导体装置1，通过使主体部23从凹部底面2b立起，从而能够使主体部23之中未埋入至绝缘物的部分的长度增大。如果使压接端子20的主体部23的整体通过封装材料11固定，则相对于热应力的变形容许度降低，相对于印刷配线基板30的通孔30a的位置偏离等的变形容许度也降低。就这一点而言，在半导体装置1中通过确保未埋入至绝缘物的主体部23，从而能够提高向压入部21施加了负载时的压接端子20的变形容许度。特别地，在半导体元件9由SiC形成的情况下，由于SiC半导体设备能够进行高温工作，因此，半导体装置1的高温运转时产生的热应力也容易增大。根据半导体装置1，相对于那样的高温工作时的热应力，压接端子20能够发挥高的变形容许度。由于能够通过封装材料11对内壁部2a的内侧进行填埋以覆盖半导体元件9，因此能够将封装材料11设置至内壁部2a的上端附近。由此，能够确保覆盖半导体元件9的封装材料11的厚度，能够确保电绝缘性。
通过内壁部2a和外壁部2c之间的凹部2d，设置有能够供主体部23挠曲的开放空间。即使将封装材料11填充至内壁部2a的上端附近而使封装材料11增厚，主体部23也不会埋入至封装材料11。使用设置于壳体框2的内壁部2a以及凹部2d，能够兼顾以下两点，即：将封装材料11设置得厚；以及保证压接端子20的主体部23可自由变形。因此，能够在抑制半导体装置1整体的高度尺寸扩大的同时，兼顾半导体装置1的电绝缘性的确保和压接端子20的变形容许度的提高这两者。
在将封装材料11的材料向半导体元件9的上方投入时，由于在壳体框2设置有凹部2d，因此能够可靠地实现使压接端子20的主体部23从封装材料11露出。还具有能够简单地进行封装材料11的材料投入工序的优点。
在实施方式1中，设置有缩颈部23a。通过设置缩颈部23a，从而具有下述效果，即，压接端子20容易追随通孔30a的位置偏离以及由环境因素引起的热应力而进行变形。由此，能够进一步提高半导体装置1的可靠性。即使在印刷配线基板30的通孔30a和压接端子20的位置偏离的情况下，也能够通过使缩颈部23a容易地变形而吸收位置偏离。能够防止对压入部21施加过度的应力而导致压入部21的异常变形、通孔的损伤，能够使接触导通的品质稳定化。但是，作为压接端子20的变形例，也可以不设置缩颈部23a。
半导体装置1内置有逆变器电路。根据半导体装置1，如上所述，由于能够高维度地兼顾装置的薄型化、电绝缘性以及压接端子的连接可靠性，因此，能够得到品质稳定的小型逆变器单元。
图6是本发明的实施方式1的变形例涉及的半导体装置1的剖视图。在图6的变形例中，壳体框2成形为不具有内壁部2a的形状。在刚成形后的壳体框2没有设置内壁部2a，因而在图6的变形例中，通过随后将绝缘性部件固定于壳体框2的凹部底面2b，从而形成了内壁部12。即，通过对与壳体框2分开成形的绝缘性部件进行安装，从而设置了内壁部12。内壁部12的材料只要具有绝缘性即可，没有限定，例如也可以是树脂材料。如图1所示，在提供一体成型了内壁部2a和凹部底面2b的壳体框2的情况下，需要考虑树脂的成形性，以使得凹部2d为大于或等于一定的大小的方式制作模具。与此相对，通过如本变形例所示设为被分割为独立部件的内壁部12，从而能够将凹部2d的宽度最小化，能够使压接端子20与内壁部12、外壁部2c尽可能靠近。由此，能够使半导体装置1小型化。此外，在图6的变形例中，与内壁部12的上端相比，封装材料11的上表面11a低，其差为D1。但是，在图6的变形例中，也可以使封装材料11的上表面11a与内壁部12的上端对齐。
图7是本发明的实施方式1的变形例涉及的半导体装置1的剖视图。如图7所述，内壁部2a的上端也可以比压入部21的中央位置低，且比压入部21和主体部23的连接位置高。在图7中，压入部21的下端设置在与内壁部2a的上端相比以尺寸D2更靠下方的位置。通过将压入部21的下端配置于内壁部2a的下侧，从而能够使压接端子20的前端位置变低，能够期待半导体装置1的进一步薄型化。由于内壁部2a的上端比压入部21的中央位置低，因此，也不会妨碍压入部21向通孔30a的插入。能够防止在内壁部2a处封装材料11向压入部21附着，能够确保压接连接的可靠性。
压接端子20能够应用各种公知的压接构造。作为公知的压接端子，也存在具有“没有开口部22的压入部”的压接端子。这样的不具有开口部22的公知的压接端子也可以替代压接端子20进行使用。
作为绝缘基板3的变形例，也可以将绝缘层6以及电路图案7置换为陶瓷等制成的绝缘电路基板。由于将陶瓷绝缘电路基板重叠于基座板4的上表面的绝缘基板是已经公知的，所以这里省略更多的说明。
实施方式2
图8是本发明的实施方式2涉及的半导体装置101的与图1的A-A线位置对应的剖视图。实施方式1与实施方式2的不同在于压接端子20以及印刷配线基板30存在于半导体装置101的外部还是内部。实施方式2涉及的半导体装置101构成为，将压接端子20作为内部电极收容在半导体装置101的内部，将印刷配线基板30也收容在半导体装置101的内部。即使在作为内置了印刷配线基板30的智能功率模块而提供半导体装置101的情况下，也能够通过发挥实施方式1所说明的作用效果，而对半导体装置101的高度尺寸进行抑制。
与实施方式1不同，印刷配线基板30配置于壳体框102的内部，在印刷配线基板30的上方配置有盖130。优选壳体框102以及盖130由具有高绝缘性能的工程塑料制作而成。
壳体框102与实施方式1同样地具备内壁部2a、凹部底面2b以及外壁部2c。实施方式2涉及的壳体框102在壳体框102的外壁部2c的外侧追加有台阶102e以及外框部102f。印刷配线基板30的周缘部与台阶102e重叠。在外框部102f的上端设置有外部电极端子120。外部电极端子120经由未图示的配线与印刷配线基板30或者电路图案7等连接。
在壳体框102以与印刷配线基板30重叠的方式安装有盖130。利用盖130覆盖压接端子20以及印刷配线基板30。在实施方式2中，压接端子20作为半导体装置101的内部电极端子而发挥功能。
图9是本发明的实施方式2的变形例涉及的半导体装置101的剖视图。与图6的变形例同样地，也可以通过将绝缘性部件固定至凹部底面2b而形成内壁部12。
也可以实施与在实施方式1中使用图7所说明的变形同样的变形。即，内壁部2a的上端也可以比压入部21的中央位置低且比压入部21和主体部23的连接位置高。
除此之外，在实施方式2中也能够实施与实施方式1相同的各种变形。此外，虽然在图4以及图7中，在压入部21的上端图示了凸起部，但是，该凸起也可以省略，在图2、图3、图5等中为了简化而省略了图示。

Claims (4)

1.一种半导体装置，其具备：
绝缘基板；
半导体元件，其设置于所述绝缘基板之上；
壳体框，其在所述绝缘基板的俯视观察时以包围所述半导体元件的方式设置于所述绝缘基板的周缘，由绝缘物构成，具备外壁部、内壁部、以及凹部底面，该内壁部与所述外壁部相比设置于所述绝缘基板的中央侧，该凹部底面夹在所述外壁部和所述内壁部之间，与所述外壁部以及所述内壁部一起构成凹部；
压接端子，其具备根部、主体部、以及压入部，该根部经由配线与所述半导体元件连接，该主体部从所述根部立起，该压入部设置于所述主体部的上端，所述根部埋入至所述凹部底面，所述主体部从所述凹部底面立起，从而所述主体部在所述内壁部和所述外壁部之间延伸，所述压入部凸出至所述凹部的上方；以及
封装材料，其设置于所述绝缘基板之上的所述内壁部的内侧，对所述半导体元件进行封装，
所述主体部在所述凹部内能够挠曲，
所述内壁部的上端设置于与所述压入部的中央位置相比位于下方的位置。
2.根据权利要求1所述的半导体装置，其中，
所述主体部具备缩颈部，该缩颈部在所述凹部的内侧与所述凹部底面相比位于上方。
3.根据权利要求1所述的半导体装置，其中，
所述内壁部是固定于所述凹部底面的绝缘性的部件。
4.根据权利要求1所述的半导体装置，其中，
所述内壁部的上端设置于与所述压入部和所述主体部的连接位置相比位于上方的位置。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102500480B1 (ko) * 2017-12-22 2023-02-16 삼성전자주식회사 접촉 부재를 포함하는 전자 장치 및 그 제작 방법
JP7180570B2 (ja) * 2019-09-03 2022-11-30 三菱電機株式会社 半導体モジュール
JP7224272B2 (ja) * 2019-10-30 2023-02-17 三菱電機株式会社 パワー半導体装置
CN111162057B (zh) * 2020-01-06 2022-01-21 珠海格力电器股份有限公司 半导体功率器件及用于半导体功率器件的功率处理组件
EP3961697A1 (de) * 2020-08-25 2022-03-02 Siemens Aktiengesellschaft Halbleitermodul mit einer vertiefung
DE102022118268A1 (de) * 2022-07-21 2024-02-01 Semikron Elektronik Gmbh & Co. Kg Baugruppe mit einem Kunststoffformkörper und einer Mehrzahl von Lastanschlusselementen und Leistungshalbleitereinrichtung hiermit

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1722418A (zh) * 2004-06-08 2006-01-18 富士电机电子设备技术株式会社 半导体装置
CN1848427A (zh) * 2005-04-13 2006-10-18 株式会社电装 电子装置及其制造方法
CN101261966A (zh) * 2007-03-08 2008-09-10 富士电机电子设备技术株式会社 半导体装置及其制造方法
CN103210489A (zh) * 2010-11-16 2013-07-17 富士电机株式会社 半导体装置
CN103531555A (zh) * 2013-10-24 2014-01-22 江苏宏微科技股份有限公司 免焊接端子的功率模块
CN105074919A (zh) * 2013-02-26 2015-11-18 三菱电机株式会社 电力用半导体装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2928987B2 (ja) * 1995-03-31 1999-08-03 日本航空電子工業株式会社 コンタクト及びその製造方法
DE102006040435B3 (de) 2006-08-29 2008-01-31 Infineon Technologies Ag Anordnung und Verfahren zur Montage eines Leistungshalbleitermoduls
DE102010003367B4 (de) * 2010-03-26 2015-06-25 Infineon Technologies Ag Einpress-Verbindungen für Elektronikmodule
DE102010038727B4 (de) 2010-07-30 2015-07-16 Infineon Technologies Ag Leistungshaltleitermodul und Verfahren zur Herstellung eines Leistungshalbleitermoduls
JP5383621B2 (ja) * 2010-10-20 2014-01-08 三菱電機株式会社 パワー半導体装置
US9343388B2 (en) * 2012-01-25 2016-05-17 Mitsubishi Electric Corporation Power semiconductor device
JP5867966B2 (ja) * 2012-08-29 2016-02-24 新電元工業株式会社 半導体装置
JP2015026820A (ja) * 2013-06-18 2015-02-05 株式会社デンソー 電子装置
JP2015023226A (ja) 2013-07-23 2015-02-02 三菱電機株式会社 ワイドギャップ半導体装置
US20160240452A1 (en) * 2015-02-18 2016-08-18 Semiconductor Components Industries, Llc Semiconductor packages with sub-terminals and related methods
JP6541593B2 (ja) * 2015-05-15 2019-07-10 三菱電機株式会社 電力用半導体装置
US9979105B2 (en) * 2015-05-15 2018-05-22 Mitsubishi Electric Corporation Power semiconductor device
DE112016004757T5 (de) * 2015-12-10 2018-07-05 Hitachi Automotive Systems, Ltd. Elektronische steuervorrichtung
JP2017193299A (ja) 2016-04-22 2017-10-26 トヨタ自動車株式会社 車両のバッテリ搭載構造
JP6705394B2 (ja) * 2017-02-16 2020-06-03 三菱電機株式会社 半導体モジュールおよびインバータ装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1722418A (zh) * 2004-06-08 2006-01-18 富士电机电子设备技术株式会社 半导体装置
CN1848427A (zh) * 2005-04-13 2006-10-18 株式会社电装 电子装置及其制造方法
CN101261966A (zh) * 2007-03-08 2008-09-10 富士电机电子设备技术株式会社 半导体装置及其制造方法
CN103210489A (zh) * 2010-11-16 2013-07-17 富士电机株式会社 半导体装置
CN105074919A (zh) * 2013-02-26 2015-11-18 三菱电机株式会社 电力用半导体装置
CN103531555A (zh) * 2013-10-24 2014-01-22 江苏宏微科技股份有限公司 免焊接端子的功率模块

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