CN109564854A - 在衬底上使用双面外延的工艺增强 - Google Patents

在衬底上使用双面外延的工艺增强 Download PDF

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Publication number
CN109564854A
CN109564854A CN201780049783.4A CN201780049783A CN109564854A CN 109564854 A CN109564854 A CN 109564854A CN 201780049783 A CN201780049783 A CN 201780049783A CN 109564854 A CN109564854 A CN 109564854A
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CN
China
Prior art keywords
semiconductor layer
epitaxial semiconductor
epitaxial
layer
conduction type
Prior art date
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Pending
Application number
CN201780049783.4A
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English (en)
Chinese (zh)
Inventor
J·F·萨尔兹曼
B·D·苏彻尔
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Texas Instruments Inc
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Texas Instruments Inc
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Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN109564854A publication Critical patent/CN109564854A/zh
Pending legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191Manufacturing their doped wells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351Substrate regions of field-effect devices
    • H10D62/357Substrate regions of field-effect devices of FETs
    • H10D62/364Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/854Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2902Materials being Group IVA materials
    • H10P14/2905Silicon, silicon germanium or germanium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411Silicon, silicon germanium or germanium

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CN201780049783.4A 2016-08-16 2017-08-16 在衬底上使用双面外延的工艺增强 Pending CN109564854A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/238,445 2016-08-16
US15/238,445 US10002870B2 (en) 2016-08-16 2016-08-16 Process enhancement using double sided epitaxial on substrate
PCT/US2017/047148 WO2018035226A1 (en) 2016-08-16 2017-08-16 Process enhancement using double sided epitaxial on substrate

Publications (1)

Publication Number Publication Date
CN109564854A true CN109564854A (zh) 2019-04-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780049783.4A Pending CN109564854A (zh) 2016-08-16 2017-08-16 在衬底上使用双面外延的工艺增强

Country Status (6)

Country Link
US (3) US10002870B2 (https=)
EP (1) EP3501035A4 (https=)
JP (2) JP7070970B2 (https=)
KR (1) KR102469160B1 (https=)
CN (1) CN109564854A (https=)
WO (1) WO2018035226A1 (https=)

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Publication number Priority date Publication date Assignee Title
CN109727852B (zh) * 2018-12-29 2020-12-01 长江存储科技有限责任公司 一种改善晶圆翘曲的方法、装置和设备
US10879155B2 (en) 2019-05-09 2020-12-29 Texas Instruments Incorporated Electronic device with double-sided cooling
JP2021034584A (ja) * 2019-08-26 2021-03-01 キオクシア株式会社 半導体装置及び半導体装置の製造方法
WO2021205695A1 (ja) * 2020-04-10 2021-10-14 株式会社村田製作所 可変容量素子及びそれを備えた発振器
JP7334698B2 (ja) * 2020-09-11 2023-08-29 信越半導体株式会社 Soiウェーハの製造方法及びsoiウェーハ
JP7380517B2 (ja) * 2020-10-21 2023-11-15 信越半導体株式会社 Soiウェーハの製造方法及びsoiウェーハ
US12027582B2 (en) * 2021-10-05 2024-07-02 Globalfoundries U.S. Inc. IC structure including porous semiconductor layer under trench isolation
US12119352B2 (en) 2022-01-06 2024-10-15 Globalfoundries U.S. Inc. IC structure including porous semiconductor layer in bulk substrate adjacent trench isolation
WO2025106550A1 (en) * 2023-11-14 2025-05-22 Cornell University Increasing density of semiconductor devices on a substrate

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JP2002231634A (ja) * 2001-01-30 2002-08-16 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法
WO2009001833A1 (ja) * 2007-06-26 2008-12-31 Sumco Corporation エピタキシャルウェーハおよびその製造方法
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JPH10303207A (ja) * 1997-04-23 1998-11-13 Hitachi Ltd 半導体ウエハおよびその製造方法、ならびに半導体集積回路装置
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JP2002231634A (ja) * 2001-01-30 2002-08-16 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法
WO2009001833A1 (ja) * 2007-06-26 2008-12-31 Sumco Corporation エピタキシャルウェーハおよびその製造方法
US20110095358A1 (en) * 2009-10-28 2011-04-28 Stmicrolectronics S.R.L. Double-sided semiconductor structure and method for manufacturing same

Also Published As

Publication number Publication date
EP3501035A4 (en) 2019-09-04
US20180254272A1 (en) 2018-09-06
KR20190039138A (ko) 2019-04-10
US20180053764A1 (en) 2018-02-22
JP7070970B2 (ja) 2022-05-18
US10002870B2 (en) 2018-06-19
US10304827B2 (en) 2019-05-28
KR102469160B1 (ko) 2022-11-22
US20190296013A1 (en) 2019-09-26
EP3501035A1 (en) 2019-06-26
WO2018035226A1 (en) 2018-02-22
US11056490B2 (en) 2021-07-06
JP2022101678A (ja) 2022-07-06
JP2019528573A (ja) 2019-10-10

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