JP7070970B2 - 基板上の両面エピタキシャルを用いるプロセス拡張 - Google Patents
基板上の両面エピタキシャルを用いるプロセス拡張 Download PDFInfo
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Description
Claims (15)
- デバイスであって、
平面の第1の側と平面の第2の側とを含む第1の導電型の半導体基板と、
前記半導体基板の前記第1の側に形成される前記第1の導電型の第1の半導体層と、
前記半導体基板の前記第2の側に形成される前記第1の導電型の第2の半導体層と、
を含み、
前記第1及び第2の半導体層が前記半導体基板より軽くドープされ、
第2の導電型の領域が、前記第1の半導体層と前記第2の半導体層との一方のみに形成され、
前記第2の導電型の領域のどれも、前記第1の半導体層と前記第2の半導体層との他方と前記半導体基板とを介して電気的に接続されない、デバイス。 - 請求項1に記載のデバイスであって、
前記第1の導電型がp型であり、前記第2の導電型がn型である、デバイス。 - 請求項1に記載のデバイスであって、
前記第1の導電型がn型であり、前記第2の導電型がp型である、デバイス。 - 請求項1に記載のデバイスであって、
前記第2の導電型の領域の第1の領域と第2の領域とが、それぞれ、トランジスタのソースとドレインとを形成する、デバイス。 - 集積回路(IC)デバイスであって、
平面の第1の側と平面の第2の側とを含む第1の導電型の半導体基板と、
前記半導体基板の第1の側に形成される前記第1の導電型の第1のエピタキシャル半導体層と、
前記半導体基板の第2の側に形成される前記第1の導電型の第2のエピタキシャル半導体層と、
少なくとも部分的に前記第1のエピタキシャル半導体層の表面に形成される複数のトランジスタと、
を含み、
前記第1及び第2のエピタキシャル半導体層が前記半導体基板より軽くドープされ、
前記第2のエピタキシャル半導体層に如何なるトランジスタも形成されず、
前記第1のエピタキシャル半導体層のトランジスタのどれも、前記半導体基板と前記第2のエピタキシャル半導体層とを介して電気的に接続されない、ICデバイス。 - 請求項5に記載のICデバイスであって、
前記第1の導電型がp型である、ICデバイス。 - 請求項5に記載のICデバイスであって、
前記第1の導電型がn型である、ICデバイス。 - 半導体デバイスを製造するための方法であって、
第1の導電型の半導体基板の第1の側に前記第1の導電型の第1のエピタキシャル半導体層を形成することと、
前記半導体基板の第2の側に前記第1の導電型の第2のエピタキシャル半導体層を形成することと、
少なくとも部分的に前記第1のエピタキシャル半導体層内に第2の導電型の領域を形成することと、
を含み、
前記第1及び第2のエピタキシャル半導体層が前記半導体基板より軽くドープされ、
前記第2のエピタキシャル半導体層内に如何なる前記第2の導電型の領域も形成されず、
前記半導体基板が、前記第1のエピタキシャル半導体層から前記第2のエピタキシャル半導体層への如何なる導電経路も含まない、方法。 - 請求項8に記載の方法であって、
前記第2のエピタキシャル半導体層を形成する前に、前記第1のエピタキシャル半導体層の頂部側に保護層を形成することと、
前記第2のエピタキシャル半導体層を形成した後に、前記第1のエピタキシャル半導体層から前記保護層を取り除くことと、
を更に含む、方法。 - 請求項9に記載の方法であって、
前記保護層を形成することが、前記第2のエピタキシャル半導体層を形成する前に、前記第1のエピタキシャル半導体層の頂部側に窒化物材料を形成すること、又は、前記第2のエピタキシャル半導体層を形成する前に、前記第1のエピタキシャル半導体層の頂部側に酸化物層を形成することを含む、方法。 - 請求項9に記載の方法であって、
前記少なくとも部分的に前記第1のエピタキシャル半導体層内に第2の導電型の領域を形成することが、前記第1のエピタキシャル半導体層から前記保護層を取り除くことの後に行われる、方法。 - 請求項8に記載の方法であって、
前記第1の導電型がp型であり、前記第2の導電型がn型である、方法。 - 請求項8に記載の方法であって、
前記第1の導電型がn型であり、前記第2の導電型がp型である、方法。 - 請求項8に記載の方法であって、
前記第2のエピタキシャル半導体層を形成する前に、前記第1のエピタキシャル半導体層の頂部側に窒化物又は酸化物の保護層を形成することと、
前記第2のエピタキシャル半導体層を形成した後に、前記第1のエピタキシャル半導体層から前記保護層を取り除くことと、
を更に含む、方法。 - 請求項8に記載の方法であって、
前記第2のエピタキシャル半導体層内に隔離構造を形成せずに前記第1のエピタキシャル半導体層内に隔離構造を形成することを更に含む、方法。
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US15/238,445 US10002870B2 (en) | 2016-08-16 | 2016-08-16 | Process enhancement using double sided epitaxial on substrate |
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PCT/US2017/047148 WO2018035226A1 (en) | 2016-08-16 | 2017-08-16 | Process enhancement using double sided epitaxial on substrate |
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EP (1) | EP3501035A4 (ja) |
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KR (1) | KR102469160B1 (ja) |
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CN109727852B (zh) * | 2018-12-29 | 2020-12-01 | 长江存储科技有限责任公司 | 一种改善晶圆翘曲的方法、装置和设备 |
US10879155B2 (en) * | 2019-05-09 | 2020-12-29 | Texas Instruments Incorporated | Electronic device with double-sided cooling |
JP2021034584A (ja) * | 2019-08-26 | 2021-03-01 | キオクシア株式会社 | 半導体装置及び半導体装置の製造方法 |
WO2021205695A1 (ja) * | 2020-04-10 | 2021-10-14 | 株式会社村田製作所 | 可変容量素子及びそれを備えた発振器 |
JP7334698B2 (ja) * | 2020-09-11 | 2023-08-29 | 信越半導体株式会社 | Soiウェーハの製造方法及びsoiウェーハ |
JP7380517B2 (ja) * | 2020-10-21 | 2023-11-15 | 信越半導体株式会社 | Soiウェーハの製造方法及びsoiウェーハ |
US20230108712A1 (en) * | 2021-10-05 | 2023-04-06 | Globalfoundries U.S. Inc. | Ic structure including porous semiconductor layer under trench isolation |
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EP3501035A1 (en) | 2019-06-26 |
US10304827B2 (en) | 2019-05-28 |
US11056490B2 (en) | 2021-07-06 |
KR102469160B1 (ko) | 2022-11-22 |
JP2022101678A (ja) | 2022-07-06 |
US20180254272A1 (en) | 2018-09-06 |
US10002870B2 (en) | 2018-06-19 |
EP3501035A4 (en) | 2019-09-04 |
JP2019528573A (ja) | 2019-10-10 |
CN109564854A (zh) | 2019-04-02 |
US20190296013A1 (en) | 2019-09-26 |
KR20190039138A (ko) | 2019-04-10 |
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