CN109509722A - 形成嵌入式管芯衬底的半导体器件和方法，以及具有所述嵌入式管芯衬底的系统级封装模块 - Google Patents

形成嵌入式管芯衬底的半导体器件和方法，以及具有所述嵌入式管芯衬底的系统级封装模块 Download PDF

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CN109509722A
CN109509722A CN201811092945.5A CN201811092945A CN109509722A CN 109509722 A CN109509722 A CN 109509722A CN 201811092945 A CN201811092945 A CN 201811092945A CN 109509722 A CN109509722 A CN 109509722A
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substrate
semiconductor
submodule
sip
conductive
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CN109509722B (zh
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梁悳景
李勋择
金成洙
李喜秀
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Stats Chippac Pte Ltd
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New Kojinpeng Private Ltd
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Abstract

本发明公开了形成嵌入式管芯衬底的半导体器件和方法，以及具有所述嵌入式管芯衬底的系统级封装模块。一种半导体器件具有第一衬底。第一半导体组件被设置在所述第一衬底的第一表面上。第二衬底包括在所述第二衬底的第一表面上的垂直互连结构。第二半导体组件被设置在所述第二衬底的第一表面上。所述第一半导体组件或第二半导体组件是半导体封装。所述第一衬底被设置在所述第二衬底之上，其中所述第一半导体组件和第二半导体组件在所述第一衬底和第二衬底之间。第一密封剂被沉积在所述第一衬底和第二衬底之间。SiP子模块被设置在所述第一衬底或第二衬底之上，与密封剂相对。在SiP子模块之上形成屏蔽层。

Description

形成嵌入式管芯衬底的半导体器件和方法，以及具有所述嵌 入式管芯衬底的系统级封装模块
技术领域
本发明一般地涉及半导体器件，并且更具体地涉及形成嵌入式管芯衬底（EDS）的半导体器件和方法，以及具有所述EDS的系统级封装（SiP）模块。
背景技术
半导体器件通常存在于现代电子产品中。半导体器件执行各式各样的功能，诸如信号处理、高速计算、传送和接收电磁信号、控制电子设备、光电生成、以及创建用于电视显示器的视觉图像。半导体器件存在于通信、功率变换、网络、计算机、娱乐以及消费类产品的领域中。半导体器件还存在于军事应用、航空、汽车、工业控制器以及办公室装备中。
半导体封装通常利用若干有源半导体组件、分立无源组件以及集成无源器件（IPD）制成，所述若干有源半导体组件、分立无源组件以及集成无源器件（IPD）被一起封装成单封装系统，也称为系统级封装（SiP）模块。SiP模块提供相对于传统半导体封装更高的密度以及增强的电气功能性。
有源和无源组件被安装到用于结构支撑和电气互连的衬底。在更先进的三维（3D）封装中，半导体组件被嵌入到衬底中，有时被称为衬底中的嵌入式管芯（EDS）。在EDS封装的情况下，半导体管芯在衬底的形成期间被嵌入在多个层压的层内。半导体管芯然后通过衬底的导电通孔和导电迹线而电气地连接到衬底的顶部和底部表面上的组件。
EDS的制造需要在半导体管芯周围形成衬底，这限制可用于衬底的选项。另外，衬底中的制造缺陷不仅导致衬底的损失，而且还导致否则良好的半导体管芯。传统EDS封装具有如下附加问题：低产量、高成本、高翘曲以及低设计灵活性。因此，存在对于提供在衬底设计和组件选择方面的较高灵活性以及增加的制造产量的EDS及制造方法的需要。
附图说明
图1a-1c图示了具有通过锯道分离的多个半导体管芯的半导体晶圆；
图2a-2b图示了顶部衬底子模块的面板的形成；
图3a-3b图示了底部衬底子模块的形成；
图4a-4c图示了将顶部衬底子模块和底部衬底子模块组合成具有嵌入式半导体组件的单个衬底；
图5图示了由顶部和底部衬底子模块的组合形成的EDS；
图6a-6d图示了用于顶部和底部衬底子模块上的组件的潜在布局；
图7a-7c图示了利用可替换的互连结构来形成EDS；
图8a-8d图示了形成顶部SiP子模块以供EDS使用；
图9图示了具有EDS和顶部SiP子模块的SiP模块；
图10图示了利用导电微柱通过热压缩而将顶部SiP子模块安装到EDS；
图11a-11f图示了形成底部SiP子模块以供EDS使用；
图12图示了具有EDS以及顶部和底部SiP子模块二者的SiP模块；
图13a-13c图示了直接在EDS上形成顶部和底部SiP子模块；
图14a-14b图示了包括EDS与直接在EDS上形成的SiP子模块的SiP模块；
图15a-15c图示了具有被安装到EDS上的分离地封装的半导体组件的SiP子模块；
图16a-16c图示了形成ESD，其具有被嵌入在EDS中的分离地封装的半导体组件；
图17a-17c图示了用于具有分离地封装的半导体组件的EDS的电磁干扰（EMI）屏蔽选项；
图18a-18d图示了用于利用EDS制成的SiP模块的附加EMI屏蔽选项；以及
图19a-19b图示了具有被安装到PCB表面的SiP模块的印刷电路板（PCB）。
具体实施方式
参考各图、在以下描述中的一个或多个实施例中描述本发明，在所述各图中，相似的标号表示相同或类似的元件。虽然在用于实现发明的目的的最佳模式方面描述了本发明，但是本领域技术人员将领会到，意图覆盖如可以被包括在本发明的精神和范围内的可替换方案、修改和等同物，所述本发明的精神和范围如由所附权利要求及如受以下公开内容和附图所支持的等同物所限定。
如本文中所使用的术语“半导体管芯”是指词语的单数和复数形式二者，并且因此可以指代单个半导体器件和多个半导体器件二者。如本文中所使用的术语“半导体组件”是指由半导体管芯形成的有源器件以及可与半导体电路一起使用的其他有源或无源组件二者。
一般使用两个复杂的制造过程来制造半导体器件：前端制造和后端制造。前端制造涉及在半导体晶圆的表面上形成多个管芯。晶圆上的每个管芯包含有源和无源的电气组件，其被电气地连接以形成功能电气电路。有源电气组件，诸如晶体管和二极管具有控制电流流动的能力。无源电气组件，诸如电容器、电感器和电阻器创建对于执行电气电路功能而言必要的在电压和电流之间的关系。
后端制造是指将成品晶圆切割或单一化（singulate）成单独的半导体管芯，并且封装半导体管芯以用于结构支撑、电气互连和环境隔离。为了使半导体管芯单一化，晶圆沿着晶圆的被称为锯道或划线的非功能区而被刻划和断开。通过使用激光切割工具或锯片来使晶圆单一化。在单一化之后，单独的半导体管芯被安装到封装衬底，所述封装衬底包括引脚或接触焊盘以用于与其他系统组件互连。在半导体管芯上形成的接触焊盘然后被连接到封装内的接触焊盘。可以利用导电层、凸块（bump）、柱形凸块、导电膏或焊线来制成电气连接。密封剂或其他模塑材料被沉积在封装上以提供物理支撑和电气隔离。成品封装然后被插入到电气系统中，并且使得半导体器件的功能性可用于其他系统组件。
图1a示出了具有基体衬底材料102的半导体晶圆100，所述基体衬底材料102诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅、或用于结构支撑的其他块体材料。多个半导体管芯或组件104被形成在晶圆100上，通过非有源的、管芯间晶圆区域或锯道106分离。锯道106提供用以将半导体晶圆100单一化成单独的半导体管芯104的切割区域。在一个实施例中，半导体晶圆100具有100-450毫米（mm）的宽度或直径。
图1b示出了半导体晶圆100的一部分的横截面视图。每个半导体管芯104具有背部或非有源表面108以及有源表面110，所述有源表面110包含模拟或数字电路，其被实现为有源器件、无源器件、导电层以及介电层，它们形成在管芯内并且根据管芯的电气设计和功能而被电气互连。电路可以包括被形成在有源表面110内以实现模拟电路或数字电路的一个或多个晶体管、二极管以及其他电路元件，所述模拟电路或数字电路诸如数字信号处理器（DSP）、专用集成电路（ASIC）、存储器或其他信号处理电路。半导体管芯104还可以包含IPD，诸如电感器、电容器和电阻器，其被形成在半导体管芯的表面上的互连层中或其上，以用于RF信号处理。在一些实施例中，半导体管芯104包括多个有源表面，所述有源表面具有被形成在其中或其上的电路。
在有源表面110上、通过使用PVD、CVD、电解电镀、化学镀或其他合适的金属沉积过程来形成导电层112。导电层112可以是铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、银（Ag）或其他合适的导电材料的一个或多个层。导电层112作为被电气连接到有源表面110的电路的接触焊盘而起作用。
导电凸块材料通过使用蒸发、电解电镀、化学镀、球滴或丝网印刷过程而被沉积在导电层112上。凸块材料可以是Al、Sn、Ni、Au、Ag、铅（Pb）、铋（Bi）、Cu、焊料及其组合，具有可选的助焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸块材料通过使用合适的附接或接合过程而接合到导电层112。在一些实施例中，通过将材料加热到其熔点以上而使凸块材料回流，从而形成球或凸块114。在一个实施例中，凸块114被形成在凸块下金属化部（UBM）上，所述凸块下金属化部具有润湿层、屏障层和粘附层。凸块114还可以被压缩接合或热压缩接合到导电层112。凸块114表示可以被形成在导电层112上的一种类型的互连结构。互连结构还可以使用接合线、导电膏、柱形凸块、微凸块或其他电气互连。
在图1c中，通过使用锯片或激光切割工具118、通过锯道106而将半导体晶圆100单一化成单独的半导体管芯104。在单一化之前或之后，单独的半导体管芯104可以被检查并且电气测试以用于标识已知的良好管芯（KGD）。
图2a-2b图示了形成顶部衬底子模块的面板以用于组合成衬底的过程，所述衬底具有嵌入在衬底中的半导体管芯104。图2a示出了衬底150的横截面视图，所述衬底150包括多个区，其用于形成通过锯道152分离的顶部衬底子模块151。虽然示出了仅仅两个用于形成子模块151的区，但是在其他实施例中衬底150大得多，具有用以平行地形成数百或数千个子模块151的空间。由基体绝缘材料153形成衬底150，其具有被形成在绝缘层的两个主表面上的导电层154和156。在一个实施例中，绝缘材料153是经模塑的衬底。在一些实施例中，衬底150通过使用与多个导电层交错的多个绝缘层153而被形成，其允许更复杂的信号路由。导电层154和156的部分电气公通或电气隔离，这取决于正在形成的SiP模块的设计和功能。
导电层154和156可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一个或多个层。导电通孔158延伸通过绝缘层153以将导电层154的部分电气地连接到导电层156的部分。导电层154和156提供跨衬底150的水平电气互连，而导电通孔158提供通过衬底150的垂直电气互连。在一个实施例中，通过如下来形成导电通孔158：通过蚀刻、钻孔、激光烧蚀或另一合适的过程来提供通过绝缘层153的开口，然后将导电材料沉积或电镀到开口中。在一些实施例中，作为形成导电层154或156的部分，用于导电通孔174的导电材料被沉积到绝缘层153的开口中。
衬底150还可以是任何合适的层压插入件、PCB、晶圆形式、条带式插入件、引线框架或其他类型的衬底。衬底150可以包括具有酚醛棉纸、环氧树脂、树脂、玻璃织物、毛玻璃、聚酯以及其他增强纤维或织物的组合的聚四氟乙烯（PTFE）预浸渍的 （预浸材料）、FR-4、FR-1、CEM-1或 CEM-3的一个或多个层压的层。绝缘层153包含二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、阻焊剂、聚酰亚胺、苯并环丁烯（BCB）、聚苯并恶唑（PBO）以及具有类似的绝缘和结构性质的其他材料的一个或多个层。衬底150还可以是多层柔性层压制件、陶瓷、铜包层压制件、玻璃、或半导体晶圆，其包括有源表面，所述有源表面包含一个或多个晶体管、二极管以及其他电路元件用于实现模拟或数字电路。
在将半导体管芯和其他组件安装在衬底子模块上之前，顶部衬底子模块151可以在图2a中所见的当前阶段被测试。在图2b中，半导体管芯104与分立器件160和162被表面安装到导电层154上。半导体管芯104在安装到顶部衬底子模块151上之前可以针对KGD而被测试，用于避免在良好的衬底子模块上使用坏的管芯，从而不必要地浪费子模块。另外，在安装组件之前可以测试顶部衬底子模块151，并且具有制造缺陷的子模块可以被丢弃而不在坏的衬底上浪费KGD。在一些实施例中，坏的或空白的半导体管芯104被设置在坏的衬底子模块151上用于跨衬底150而保持重量分布均匀并且帮助控制翘曲。
图2b示出了每个子模块151具有两个分立器件160和162，所述分立器件可以是电感器、电容器、电阻器或其他无源的电路组件。分立器件160和162还可以是具有有源功能性的器件，例如功率晶体管、瞬态电压抑制二极管等等。在其他实施例中，有源和无源器件的任何组合可以如期望的那样被提供在衬底150上，用于实现最终SiP模块的所意图的功能性。在一个实施例中，分立器件160和162实现带通滤波器或另一射频（RF）信号处理网络。在另一实施例中，分立器件160和162对到半导体管芯104的功率信号进行滤波。分立器件160和162可以实现任何期望的电气功能。
分立器件160和162通过焊料或焊膏166而被机械地接合并且电气地连接到导电层154。在一个实施例中，焊膏166被印刷到衬底150上，在分立器件160和162物理接触的情况下回流，然后被去焊。半导体管芯104通过导电凸块114而机械地接合并且电气地连接到导电层154。在一些实施例中，凸块114和焊膏166同时回流用于在单个步骤中表面安装所有组件。区151a指示其中有源和无源组件位于子模块151上的区。
图3a-3b图示了形成底部衬底子模块。过程开始于图3a，其中衬底200具有用于形成通过锯道202分离的多个底部衬底子模块201的位置。衬底200类似于衬底150。衬底200包括在衬底的相对侧上的一个或多个绝缘层203以及导电层204和206。导电层204和206的部分经由通过衬底200的导电通孔208而电气地连接到彼此。导电柱210形成在导电层204的接触焊盘上。通过将Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一个或多个层沉积到掩蔽层的开口中而形成导电柱210。在其他实施例中，通过另一合适的金属沉积技术来形成导电柱210。很像顶部衬底子模块151，底部衬底子模块201可以在安装组件之前被测试，并且组件也可以在安装之前被测试。
在图3b中，半导体管芯104和分立器件160-162通过焊膏166和导电凸块114而被表面安装到衬底200上并且电气地连接到导电层204。底部衬底子模块201的半导体管芯104和分立器件160-162可以与顶部衬底子模块151相同或不同。在一个实施例中，半导体管芯104针对衬底150和200二者是相同的存储器芯片，并且与在稍后步骤处提供的微处理器一起被使用。在另一实施例中，衬底150或200上的一个半导体管芯104是存储器芯片，而另一半导体管芯104是微处理器。区201a指示其中有源和无源组件位于子模块201上的区。
图4a-4c图示了将衬底子模块151和201组合成嵌入式管芯衬底（EDS）。在图4a中，具有顶部衬底子模块151的衬底150被翻转并且设置在具有底部衬底子模块201的衬底200上。在一些实施例中，在顶部和底部衬底子模块的组合之前，衬底150、衬底200或二者可以被单一化。顶部衬底子模块151和底部衬底子模块201上的组件分别被限制到区151a和201a内。区151a和201a的布局被设计使得当顶部衬底子模块151被翻转并且安装在底部衬底子模块201上的时候，组件不彼此干扰。也就是说，当衬底子模块中的一个被翻转并且与另一子模块对准的时候，两个子模块的所有组件都在彼此的组件的占用空间外。如图4a中所定向的，子模块151仅仅在子模块的右半部上包括组件，而子模块201仅仅在左半部上包括组件。其他布局是可能的，如以下参考图6a-6d所解释的。
虽然图4a图示了将衬底150堆叠在衬底200上，但是在其他实施例中衬底200也可以在顶部。在一个实施例中，底部衬底150或200利用可选的双侧带、热释放层、UV释放层或其他适当的界面层被设置在载体上以用于物理支撑。在一些实施例中，顶部衬底150或200在设置于底部衬底150或200上之前被单一化。
图4b示出了被设置到底部子模块201上的顶部子模块151。顶部子模块151上的半导体管芯104和分立器件160-162在底部子模块201上的半导体管芯和分立器件的高度内延伸，而在顶部和底部组件之间没有接触。将顶部和底部组件保持在彼此的占用空间之外允许形成较薄的衬底，因为顶部和底部衬底组件可以占据相同的垂直区。然而，在其中设计参数允许的实施例中，在最终器件中，顶部子模块151和底部子模块201的一部分或所有组件可以直接在彼此之上。
在图4b中，密封剂或模塑化合物220通过使用膏体印刷（paste printing）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其他合适的涂敷器而被沉积在衬底150和200之间，并且在半导体管芯104和分立器件160-162上。密封剂220可以是聚合物复合材料，诸如环氧树脂、环氧丙烯酸酯、或者具有或没有填充剂的聚合物。密封剂220是非导电的，提供结构支撑，并且在环境上保护半导体器件免受外部元件和污染物的影响。密封剂220在半导体管芯104下方在导电凸块114之间流动，并且在分立器件160-162下方在焊膏166之间流动，用于完全地填充在衬底150和200之间的空间。衬底150和200与密封剂220形成面板224。
在图4c中，通过衬底150、衬底200和密封剂220而将面板224单一化成多个嵌入式管芯衬底（EDS）230。图5图示了完成的EDS 230。在一些实施例中，面板224直到稍后的制造阶段才被单一化成单独的EDS 230，尤其是当附加的组件被安装到衬底150或200上的时候，如在以下各种实施例中所示。分立器件160和162通过导电层154、156、204和206而被电气耦合到相同衬底150或200的半导体管芯104。一个衬底的半导体管芯104和分立器件160-162通过柱210而被电气连接到相对衬底上的组件。分立器件160-162被电气连接到半导体管芯104以提供期望的无源功能性。图5中的EDS 230构成半导体封装。衬底150或衬底200可以与密封剂220相对地凸块化（bumped），然后EDS 230通过使用凸块而被安装到电子设备的印刷电路板（PCB）或其他衬底。附加的有源或无源器件可以被安装在相对衬底的顶部，并且在最终电子设备中被密封或保持暴露。
通过如下来形成EDS 230：将组件设置在两个分离的衬底上，将所述衬底设置在彼此上，其中组件在衬底之间，然后在两个衬底之间沉积密封剂用于覆盖组件。所述形成EDS230的方法允许衬底和组件的灵活设计，增加产量，降低成本，并且帮助在制造期间控制翘曲。可以在安装半导体管芯104之前测试衬底子模块151和201，从而减少废管芯的数量。
当组合衬底以制成EDS 230的时候，衬底150和200上的组件被形成、安装或设置在彼此的占用空间之外的区域内。在以上实施例中，衬底200上的组件被形成在器件的一半上，在图6a中被示出为衬底200a的区201a。衬底150上的组件被形成在器件的另一半中，在图6a中被示出为衬底150a的区151a。图6a-6d图示了当从EDS 230的顶部观看时（如由图5中的线6a-6d所指示的）的衬底150和200的不同实施例。当衬底150a和200a被堆叠的时候，区151a和201a不重叠。衬底150和200上的组件可以位于相同的垂直高度内，因为组件水平地在不同位置中。衬底150和200上的每个组件可以占据多达衬底150和200之间的整个高度，因为相对的衬底没有干扰组件。在两个衬底上具有这样非重叠的组件允许衬底上的较高组件和/或允许衬底利用较短的柱210被安装得更靠近于彼此。
衬底150和200上的组件可以以任何期望的布局来被设置，并且衬底150和200上的布局不需要是对称的。图6b图示了衬底200b的区201b，其显著大于衬底150b的区151b。在图6b的实施例中，相比于衬底150b的区151b，更多的组件、具有更大占用空间的组件、或这二者被设置在区201b内的衬底200b上。然而，区151b和201b保持不重叠，使得相对衬底的组件仍彼此不干扰。
图6c示出了如匹配非矩形形状的、不彼此重叠的衬底200c的区201c和衬底150c的区151c。在图6d中，区201d和151d是不连续的区。组件可以以任何期望的图案而被设置在衬底150和200上。在一些实施例中，相对衬底的一些组件重叠，而其他不重叠。例如，较短的组件可以被安置在彼此的顶部，其被连接到它们的相应衬底150和200，而其他较高的组件被设置在其中相对衬底没有组件的位置中。在一个实施例中，半导体管芯104被背部研磨到比衬底150和200之间的距离的一半更小的高度，使得两个半导体管芯当被对准的时候将配合于衬底之间处于彼此顶部上。衬底中的每一个包括在半导体管芯周围的分立组件，所述分立组件显著高于管芯，并且因此被设置在半导体管芯周围的非重叠区中。
图7a-7c图示了针对将衬底150电气连接到衬底200的垂直互连结构的选项，作为对于导电柱210的可替换方案。图7a示出了代替于导电柱210而具有被安装到衬底200的导电层204上的导电凸块236的EDS 234。导电凸块236被回流或热压缩接合从而将凸块附接到导电层204。衬底150被设置在凸块上。凸块被回流到导电层154上以将衬底150物理地且电气地连接到衬底200。在其他实施例中，凸块236被热压缩接合到衬底150。凸块236类似于凸块114。
图7b图示了其中导电柱210被铜芯焊料球（CCSB）240-242取代的EDS 238。通过使用被涂覆在焊料242中的铜芯240来形成CCSB。在一些实施例中，焊料242被电镀到铜芯240上。在一个实施例中，镍层被电镀在焊料242和铜芯240之间。与导电凸块236类似地使用CCSB 240-242。CCSB提供对改善的耐电迁移性，提供更结实的凸块以维持在衬底150和200之间的偏移，并且增加在衬底之间的导热性。
图7c图示了将e-Bar或PCB单元246用于在衬底150和200之间的电气互连的EDS244。PCB单元246包括核衬底247，所述核衬底247具有通过核衬底而形成的导电通孔248。在一些实施例中，接触焊盘被形成在PCB单元246的顶部和底部表面上。焊料掩蔽层可以被用在接触焊盘上。在一些实施例中，通过在通孔248和导电层204之间使用焊料或焊膏，PCB单元246被安装到衬底200上。附加的焊料或焊膏可以用于将衬底150连接到通孔248。在一些实施例中，每个PCB单元246在面板224中的两个相邻的器件230之间延伸，并且图4c中对面板的单一化切穿PCB单元。先前描述的或以下实施例中的任何实施例可以通过使用凸块236、CCSB 240-242或PCB单元246而不是导电柱210来被形成。
图8a-8d图示了形成顶部SiP子模块的面板以用于与EDS 230组合成系统级封装（SiP）模块的过程。图8a示出了衬底250的横截面视图，所述衬底250包括多个区，用于形成通过锯道252分离的顶部SiP子模块251。虽然示出了仅仅两个用于形成子模块251的区，但是在其他实施例中衬底250大得多，具有用以平行地形成数百或数千个子模块251的空间。由基体绝缘材料253与被形成在绝缘层的两个主表面上的导电层254和256形成衬底250。衬底250大体上类似于上文中对衬底150和200的描述，尽管在衬底之间一些特性可不同。
在图8b中，分立器件260、262和264被表面安装到导电层254上。图8b示出了被安装到衬底250上的电感器260、电阻器262和电容器264，但是有源和无源器件的任何组合可以如期望的那样被提供以实现SiP模块的所意图的功能性。在一个实施例中，分立器件260-264实现带通滤波器或另一RF信号处理网络。分立器件260-264通过焊料或焊膏266而被机械地接合并且电气地连接到导电层254。在一个实施例中，焊膏266被印刷到衬底250上，在分立器件260-264物理接触的情况下回流，然后被去焊。
在图8c中，密封剂或模塑化合物270被沉积在分立器件260-264和衬底250上。密封剂270类似于密封剂220。在一些实施例中，密封剂270被沉积具有用以完全覆盖分立器件260-264的厚度。在其他实施例中，被安装在衬底250上的有源或无源组件可以通过使用膜辅助的模塑而保持从密封剂270暴露。
在图8d中，通过研磨机272可选地移除密封剂270的一部分用于暴露或创建密封剂270的新背部表面274。研磨机272使密封剂270平面化以形成表面274。可替换地，通过使用化学机械平面化（CMP）、蚀刻过程或激光直接烧蚀（LDA）来使密封剂270平面化。在一些实施例中，连同密封剂270一起，研磨机272还使被设置在衬底250上的一些有源或无源组件平面化。将密封剂270模塑到比必要的更大的厚度，然后进行背部研磨有助于控制面板翘曲。密封衬底250和分立器件260-264创建顶部SiP子模块251的条带或面板280。
图9图示了被设置在EDS 230上以形成SiP模块276的顶部SiP子模块251中的一个。SiP子模块251可以从面板280被单一化并且被设置在单一化的EDS 230上。在一个实施例中，在单一化成单独EDS 230之前，单一化的SiP子模块251被设置在面板224上。在另一实施例中，面板280被设置在面板224上，并且这两个面板在导电凸块282被回流以将面板物理并且电气地连接在一起之后被一起单一化。导电凸块282在EDS 230和顶部SiP子模块251之间回流以用于在衬底250和衬底150之间的机械接合与电气互连。半导体管芯104通过导电层204、206、154、156、254和256、导电通孔158、208和258、导电柱210、以及导电凸块282而被电气地连接到分立器件260-264。半导体管芯104和分立器件160、162、260、 262和264通过衬底150、200和250、导电凸块282以及导电柱210而被电气耦合到导电凸块284。
在其他实施例中，凸块282被热压缩接合。热压缩接合可以针对每个顶部SiP子模块251分离地发生，或者每个顶部SiP子模块可以一次成群地热压缩接合到面板224。与半导体管芯104的凸块114类似地形成凸块282。凸块282可以在将面板280单一化成顶部SiP子模块251之前或之后被形成在衬底250上，或可以被形成在衬底150上。凸块284被形成在导电层206上。以与凸块114类似的方式施加凸块284。在一些实施例中，在将面板224单一化成EDS 230之前，在导电层206上形成凸块284。凸块284用于将SiP模块276安装到电子设备的更大衬底，如图19a-19b中所示。
图10图示了其中导电凸块282被导电微柱290取代的可替换实施例。在一个实施例中，通过将铜或另一适当导电材料电镀到导电层256的接触焊盘上而形成微柱290。焊料帽292被电镀到微柱290上。在一个实施例中，微柱290与焊料帽292与彼此一起被沉积到共同掩蔽层开口中。可选的非导电膜（NCF）或膏（NCP）294被设置到衬底150上以帮助将焊料帽292热压缩接合到导电层156。焊料帽292可以可替换地在有或没有NCP 294的情况下回流到导电层156上。微柱290可以在以上或以下描述的实施例中的任何实施例的情况下被使用，其中SiP子模块被安装到EDS 230的顶部或底部。
图11a-11f图示了形成底部SiP子模块。过程开始于图11a，其中衬底300具有用于形成通过锯道302分离的多个底部SiP子模块301的位置，类似于衬底150、200和250。衬底300包括在衬底的相对侧上的一个或多个绝缘层303以及导电层304和306。导电层304和306的部分经由通过衬底300的导电通孔308而电气地连接到彼此。导电柱310形成在导电层304的接触焊盘上。通过将Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一个或多个层沉积到掩蔽层的开口中而形成导电柱310。在其他实施例中，通过另一合适的金属沉积技术来形成导电柱310。在一些实施例中，代替于导电柱310而使用导电凸块236、CCSB 240-242或PCB单元246。
在图11b中，半导体管芯104和分立器件312通过焊膏314和导电凸块114而被表面安装到衬底300上并且电气地连接到导电层304。半导体管芯104可以执行与EDS 230的半导体管芯104相同的功能或不同的功能。图11c示出了被沉积在衬底300、导电柱310、半导体管芯104和分立器件312上的密封剂320，其类似于密封剂220。在图11d中，通过使用研磨机322来对密封剂320进行背部研磨。对面板330进行背部研磨导致与导电柱310的顶部表面共面的密封剂320的新背部表面324。在一些实施例中，半导体管芯104在相同的步骤中被暴露或被进一步背部研磨。在一个实施例中，在背部研磨之后，一些密封剂保持覆盖导电柱310。
在图11e中，导电柱310的侧表面通过使用利用激光331的LDA或另一合适的蚀刻过程而从密封剂中暴露，用于形成部分地围绕或完全地围着导电柱的可选槽口或凹槽332。每个单独的凹槽332可以完全围绕一个导电柱310、在近似圆圈中延伸。在一个实施例中，凹槽332内的密封剂320的表面近似线性地从导电柱310延伸到每个导电柱的整个周界周围的密封剂的表面324。在其他实施例中，凹槽332内的密封剂320的表面包括其他剖面形状。在其中在背部研磨之后密封剂320保持覆盖导电柱310或不执行背部研磨的实施例中，激光331也用于暴露导电柱的顶部表面。
在图11f中，通过使用锯片、激光切割工具或水切割工具336，面板330通过衬底330和密封剂320而被单一化成多个底部SiP子模块301。单独的底部SiP子模块301中的每一个包括半导体管芯104、分立器件312或电气组件的任何其他期望的组合。
图12图示了具有被安装到EDS 230的顶部SiP子模块251和底部SiP子模块301二者的SiP模块340。顶部SiP子模块251和EDS 230被组合，如以上关于图9和10所讨论的那样。在一个实施例中，底部SiP面板330、EDS面板224和顶部SiP面板280在单一化之前全部被堆叠，其中凸块282在顶部面板和EDS面板之间，并且凸块342在EDS面板和底部面板之间。凸块282和342同时回流，用于在使三个面板中任一个单一化之前机械并且电气地连接所有三个面板。在其他实施例中，在附接顶部SiP子模块251之前或之后，使EDS面板224翻转。在面板330的单一化之后将SiP子模块301安装到衬底200上，或者面板330可以作为整体被安装。
凸块344被形成在柱310的暴露的端部上，并且延伸到凹槽332中。以与凸块114类似的方式施加凸块344。在一些实施例中，在将面板330单一化成底部SiP子模块301之前，在柱310上形成凸块344。凸块344提供与图9中的凸块284类似的功能。凸块344用于将SiP模块340安装到较大电子设备的衬底，因而将SiP模块功能性并入到电子设备中。
图13a-13c图示了形成SiP模块，其中顶部和底部SiP子模块直接被形成在EDS的衬底上。在图13a中，顶部SiP面板350基于图2b中的衬底150而被形成。分立器件260-264以及密封剂270在图13a中被提供，如在图8a-8d中那样，但是被直接设置到衬底150的导电层156上而不是分离的衬底250上。在图13b中，底部SiP面板360基于来自图3b的衬底200而被形成。导电柱310、半导体管芯104、分立器件312、密封剂320以及导电凸块344如在图11a-11f中那样被提供，但是被直接设置到衬底200的导电层206上，而不是到分离的衬底300上。在图13c中，面板350和360被一起安装，其中衬底150和200通过如图4a中的导电柱210被连接。
密封剂220被沉积在衬底150和200之间，然后面板350和360被单一化成多个SiP模块370，如图14a中所示。SiP模块370包括被安装在衬底150和200的顶部和底部表面上的分立组件和半导体管芯的任何期望的组合。被安装到衬底150和200上的所有组件被电气连接到彼此并且通过衬底和导电柱210和310被电气连接到凸块344，用于进一步的系统集成。图14b图示了SiP模块380的实施例，其由如图13a中的顶部SiP面板350形成，但是具有如在图3b中所使用的底部衬底200。凸块284被设置在如图9中的导电层206上。
图15a-15c图示了使用分离地封装的半导体管芯来由EDS 230形成SiP模块。图15a示出了SiP模块390，其类似于SiP模块340，但是其中半导体封装392取代裸半导体管芯104。半导体管芯394被凸块化有导电凸块396并且利用密封剂398被密封以形成封装392。在其他实施例中，其他类型的半导体封装392被安装在衬底300上。半导体封装392可以包括用于封装的引线框架或衬底。在各种实施例中，本文中公开的半导体管芯中的任一个可以用任何封装类型的经封装的管芯来取代。
图15b图示了被设置在EDS 230的衬底200上的两个分离的底部SiP子模块400和410。底部SiP子模块400类似于底部SiP子模块301，并且包括半导体管芯104、分立器件312和导电柱310。底部SiP子模块410是分离地封装的半导体管芯412。半导体管芯412通过使用导电凸块416而被设置在衬底414上并且被模塑在密封剂418内。任何其他类型的半导体封装可以被安装到衬底200的导电层206，与底部SiP子模块400相邻，作为底部SiP子模块410。底部SiP子模块410可以包括其他类型的衬底或引线框架，或可以在没有衬底的情况下被形成，与图15a中的半导体封装392一样。底部SiP子模块410可以包括导电柱310或其他垂直互连结构，以允许通过底部SiP子模块410而连接到如图19a-19b中的较大系统的底层衬底。底部SiP子模块410还可以并入底部SiP子模块400或301的分立器件和任何其他特征。
在图15c中，SiP模块420包括来自图13a的面板350，其与图3b中的衬底200相组合。面板350被形成有延伸通过密封剂170的导电柱422以及在柱上的导电凸块424以用于随后的系统集成。顶部SiP子模块426包括被安装在衬底430上的分立器件428与半导体封装431。半导体封装431类似于图15b中的半导体封装410。如所图示的，半导体封装431包括半导体管芯104，所述半导体管芯104被安装在衬底432上，利用密封剂434被模塑，并且利用导电凸块436被安装到衬底430。在其他实施例中使用其他半导体封装类型。图15c中的半导体管芯104可以都是相同的，或具有变化的功能。
图16a-16c图示了形成EDS，其中嵌入式组件在集成到EDS中之前被模塑。图16a图示了衬底150，所述衬底150具有被安装到衬底上的半导体管芯104和分立器件160和162。半导体管芯104和分立器件160-162在衬底150上的处置之前被模塑在密封剂中以形成半导体封装440。在一个实施例中，用于多个衬底150或200的半导体管芯104和分立器件160-162被设置在载体上、彼此相邻，并且被密封在载体上以形成封装440的面板。导电凸块114和焊料166被直接设置在载体上并且不完全被密封剂所覆盖。半导体封装440的经密封的面板被单一化成单独的封装以供衬底150或200使用。半导体封装440利用导电层154上的凸块114和焊料166而被设置在衬底150上。
被设置在衬底150或200上的组件的一部分可以被封装在一起，而其他分立组件或半导体管芯被设置在密封剂外部。为了图示的目的，图16a图示了被密封在封装440中的衬底150上的每个组件，而图16b图示了衬底200，所述衬底200具有在半导体封装442内的半导体管芯104以及在封装外部的分立器件160-162。在一个实施例中，在衬底150和衬底200二者上使用相同的封装配置。在其他实施例中，半导体管芯、半导体封装和其他组件的任何组合可以被表面安装到衬底150和200上。在衬底150和200上所使用的半导体封装包括任何类型的半导体封装，并且在一些实施例中包括在封装内的衬底或引线框架。
在图16c中，衬底150和200面对面堆叠并且被密封，如图4a-4b中那样，用于形成EDS 446。EDS 446可以被单一化，如图4c中那样，或被留作较大的面板直到添加了附加的SiP模块组件为止。
图17a-17c图示了在衬底150和200之间具有半导体封装的情况下，用于对SiP模块的电磁干扰（EMI）屏蔽的选项。图17a图示了具有半导体封装440和442的EDS 450。半导体封装442包括在封装上形成的屏蔽层452。半导体封装440包括在封装上形成的屏蔽层454。在一个实施例中，在封装442和440的制造期间施加屏蔽层452和454。经密封的组件的面板通过密封剂被单一化但是被留在载体上。单一化移除在相邻封装中每一个之间的密封剂材料。导电材料被电镀在封装的顶部上，并且被电镀到通过单一化所创建的封装之间的空间中。通过CVD、PVD、化学镀或其他合适的金属沉积过程来执行电镀。屏蔽层452和454包括Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一个或多个层。在安装于衬底150和200上之前，器件通过其屏蔽层被单一化以最终分离器件中的每一个。在其他实施例中，封装440和442在安装到衬底150和200上之后通过在衬底的其他区域上使用掩蔽层而被电镀有屏蔽层452和454。
屏蔽层452和454分别覆盖封装442和440的顶部和侧表面。在一些实施例中，屏蔽层452和454被电气地连接到衬底的导电层以提供电气接地。屏蔽层452和454可以被施加在与衬底150和200一起使用的任何合适类型的半导体封装上。屏蔽层452和454通过使用用于在半导体封装上形成屏蔽层的任何合适的过程来被形成。屏蔽层452和454减小击中封装442和440的电磁辐射的量，所述电磁辐射到达半导体管芯104以及封装内的其他组件。EDS450可以形成用于本文中所公开的SiP模块中的任何SiP模块的基础。
图17b图示了基于EDS 446而被制造的SiP模块460。分立器件260-264被安装到衬底250上并且利用密封剂270被模塑。在分立器件260-264和密封剂270被添加之后，在整个SiP模块460上形成屏蔽层462。在一个实施例中，多个SiP模块460被形成为面板并且在载体上单一化。在单一化之后屏蔽层462被沉积在面板上，而单元保留在载体上。屏蔽层462大体上类似于屏蔽层452和454，但是在SiP模块级而不是在半导体封装级被形成。
图17c图示了SiP模块470，其形成有来自图17a的屏蔽层452和454以及来自图17b的屏蔽层462二者。
图18a-18d图示了用于具有EDS衬底的SiP模块的附加EMI屏蔽选项。图18a图示了SiP模块480，其具有被形成在顶部SiP子模块251上的屏蔽层482。顶部SiP子模块251如图8a-8d中那样被形成，并且屏蔽层482在单一化之后被形成在单元的面板上。在一些实施例中，导电层254或导电层256横向地延伸到衬底250的边缘以接触屏蔽层482并且提供接地连接。
图18b示出了SiP模块490，其添加了如图12中的下部SiP子模块301，其中屏蔽层494被形成在下部SiP子模块之上。底部SiP子模块301被形成，如图11a-11f中所示。在图11f中的单一化之后，但是在从单一化发生在其上的载体移除单元之前，面板被电镀有屏蔽层494。通过屏蔽层494蚀刻开口以暴露导电柱310，用于进一步的系统集成。在一些实施例中，在形成了屏蔽层494之后，在柱310周围形成凹槽332。
图18c图示了SiP模块500，其通过向图14b中的SiP模块380添加屏蔽层502而被形成。图18d图示了SiP模块510，其通过向图14a中的SiP模块370添加屏蔽层512而被形成。以与以上的屏蔽层452、454和462类似的方式来形成屏蔽层502和512。
图19a-19b图示了将以上描述的SiP模块和EDS衬底并入到电子设备中。图19a图示了来自图14b的、被安装到PCB或其他衬底520上作为电子设备的一部分的SiP模块380的部分横截面。凸块284回流到导电层522上，用于将SiP模块380物理地附接且电气地连接到PCB520。以上描述的SiP模块或EDS衬底中的任何单独地可以类似地被安装到PCB 520上。在其他实施例中，使用热压缩或其他合适的附接和连接方法。在一些实施例中，在SiP模块380和PCB 520之间使用粘附或底部填充层。
半导体管芯104通过凸块114、衬底200和150、导电柱210和导电凸块284而被电气地耦合到导电层522。分立器件260-264通过衬底150、导电柱210、衬底200和导电凸块284而被耦合到导电层522和半导体管芯104。
图19b图示了电子设备524，其包括PCB 520，所述PCB 520具有被安装在PCB的表面上的多个半导体封装，包括SiP模块380。电子设备524可以具有一种类型的半导体封装，或多种类型的半导体封装，这取决于应用。
电子设备524可以是独立系统，其使用半导体封装来执行一个或多个电气功能。可替换地，电子设备524可以是较大系统的子组件。例如，电子设备524可以是平板电脑、蜂窝电话、数字相机、通信系统或其他电子设备的部分。电子设备524还可以是图形卡、网络接口卡、或被插入到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、ASIC、逻辑电路、模拟电路、RF电路、分立的有源或无源器件、或其他半导体管芯或电气组件。
在图19b中，PCB 520提供一般的衬底以用于被安装在PCB上的半导体封装的结构支撑和电气互连。在一些实施例中，PCB 520根据以上描述被制造为EDS，并且包括被嵌入在PCB内的有源和无源组件。导电信号迹线522通过使用蒸发、电解电镀、化学镀、丝网印刷或其他合适的金属沉积过程而被形成在PCB 520的表面上或PCB 520的层内。信号迹线522提供在半导体封装、所安装的组件以及其他外部系统或组件中每一个之间的电气通信。根据需要，迹线522还向半导体封装中的每一个提供功率和接地连接。
在一些实施例中，半导体器件具有两个封装层级。第一层级封装是用于将半导体管芯机械地并且电气地附接到中间衬底的技术。第二层级封装涉及将中间衬底机械地并且电气地附接到PCB。在其他实施例中，半导体器件可仅仅具有第一层级封装，其中管芯被机械地并且电气地直接安装到PCB。
为了说明的目的，在PCB 520上示出若干类型的第一层级封装，包括接合线封装526和倒装芯片528。另外，若干类型的第二层级封装、包括球栅阵列（BGA）530、凸块芯片载体（BCC）532、接点栅格阵列（LGA）536、多芯片模块（MCM） 538、方形扁平无引脚封装（QFN）540、嵌入式晶圆级球栅阵列（eWLB）544以及晶圆级芯片尺度封装（WLCSP）546被示出为连同SiP模块380一起被安装在PCB 520上。在一个实施例中，eWLB 544是扇出型晶圆级封装（Fo-WLP），并且WLCSP 546是扇入型晶圆级封装（Fi-WLP）。
取决于系统需要，利用第一和第二层级封装式样的任何组合而被配置的半导体封装以及其他电子组件的任何组合可以被连接到PCB 520。在一些实施例中，电子设备524包括单个附接的半导体封装，而其他实施例需要多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预制的组件并入到电子设备和系统中。因为半导体封装包括复杂的功能性，所以可以通过使用不太昂贵的组件和流线型制造过程来制造电子设备。结果产生的器件不太可能出故障，并且制造起来不太昂贵，从而导致对于消费者的较低成本。
虽然本发明的一个或多个实施例已经被详细说明，但是技术技工将领会到，可以做出对那些实施例的修改和改编，而不脱离如在所附权利要求中阐明的本发明的范围。

Claims (15)

1.一种制作半导体器件的方法，包括：
提供第一衬底；
将第一半导体组件设置在所述第一衬底的第一表面上；
提供第二衬底，其包括在所述第二衬底的第一表面上的垂直互连结构；
将第二半导体组件设置在所述第二衬底的第一表面上；
将所述第一衬底设置在所述第二衬底之上，其中所述第一半导体组件和第二半导体组件在所述第一衬底和第二衬底之间；以及
将第一密封剂沉积在所述第一衬底和第二衬底之间。
2.根据权利要求1所述的方法，还包括将SiP子模块设置在第一衬底或第二衬底之上，与密封剂相对。
3.根据权利要求2所述的方法，还包括在SiP子模块之上形成屏蔽层。
4.根据权利要求1所述的方法，其中所述第一半导体组件或第二半导体组件是半导体封装。
5.根据权利要求1所述的方法，还包括将第三半导体组件设置在第一衬底的第二表面之上。
6.根据权利要求5所述的方法，还包括将第二密封剂设置在第一衬底的第二表面和第三半导体组件之上。
7.一种制作半导体器件的方法，包括：
提供第一衬底；
提供第二衬底；
将第一半导体组件设置在所述第一衬底和第二衬底之间；以及
将第一密封剂沉积在所述第一衬底和第二衬底之间。
8.根据权利要求7所述的方法，还包括将第一SiP子模块设置在第一衬底之上，其中所述第一SiP子模块包括第二密封剂以及延伸通过所述密封剂的垂直互连结构。
9.根据权利要求8所述的方法，还包括将第二SiP子模块设置在第一衬底之上。
10.一种半导体器件，包括：
第一衬底；
第二衬底；
被设置在所述第一衬底和第二衬底之间的第一半导体组件；以及
被沉积在所述第一衬底和第二衬底之间的密封剂。
11.根据权利要求10所述的半导体器件，还包括在所述第一衬底和第二衬底之间的垂直互连结构。
12.根据权利要求10所述的半导体器件，还包括第二半导体组件，所述第二半导体组件被设置在第一衬底之上，与所述第一半导体组件相对。
13.根据权利要求10所述的半导体器件，还包括SiP子模块，所述SiP子模块被设置在第一衬底之上，与所述第一半导体组件相对。
14.根据权利要求13所述的半导体器件，其中所述SiP子模块包括垂直互连结构。
15.根据权利要求10所述的半导体器件，其中所述第一半导体组件包括屏蔽层。
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