CN109390407B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109390407B
CN109390407B CN201810812764.9A CN201810812764A CN109390407B CN 109390407 B CN109390407 B CN 109390407B CN 201810812764 A CN201810812764 A CN 201810812764A CN 109390407 B CN109390407 B CN 109390407B
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CN109390407A (zh
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闵宣基
卢东贤
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET

Abstract

一种半导体装置包含：第一有源图案以及第二有源图案，在衬底上；第一源极/漏极区，在第一有源图案上；第二源极/漏极区，在第二有源图案上；以及装置隔离层，填充第一有源图案中的相邻第一有源图案之间的第一沟槽以及第二有源图案中的相邻第二有源图案之间的第二沟槽。内衬层设置在第二有源图案中的相邻第二有源图案之间的装置隔离层上。第一有源图案中的相邻第一有源图案之间的装置隔离层在第一源极/漏极区下方具有凹槽，且第二有源图案中的相邻第二有源图案之间的内衬层的底部表面高于凹槽。

Description

半导体装置
相关申请的交叉引用
本专利申请案请求2017年8月3日在韩国知识产权局提交的韩国专利申请案第10-2017-0098636号的优先权，所述专利申请案的公开内容特此以全文引用的方式并入。
技术领域
本发明概念的实施例涉及半导体装置，且更具体地说涉及包含场效应晶体管的半导体装置。
背景技术
由于半导体装置的尺寸小、多功能特性和/或低制造成本，因此半导体装置广泛地用于电子行业中。半导体装置可分类为存储逻辑数据的半导体存储器装置、处理逻辑数据的半导体逻辑装置以及具有半导体存储器装置的功能和半导体逻辑装置的功能的混合半导体装置中的任何一种。随着电子行业的发展，对具有优良特性的半导体装置的需求也在不断增加。举例来说，对高可靠、高速和/或多功能半导体装置的需求在不断增加。为了满足需求，半导体装置已变得高度集成且半导体装置的结构已变得越来越复杂。
发明内容
本发明概念的实施例可提供一种包含具有改进的电气特性的场效应晶体管的半导体装置。
在一方面，一种半导体装置包含衬底上的第一有源图案和第二有源图案、第一有源图案上的第一源极/漏极区、第二有源图案上的第二源极/漏极区以及填充第一有源图案中的相邻第一有源图案之间的第一沟槽和第二有源图案中的相邻第二有源图案之间的第二沟槽的装置隔离层。内衬层设置在第二有源图案中的相邻第二有源图案之间的装置隔离层上。第一有源图案中的相邻第一有源图案之间的装置隔离层在第一源极/漏极区下方具有凹槽，且第二有源图案中的相邻第二有源图案之间的内衬层的底部表面高于凹槽。
在一方面，一种半导体装置包含具有第一区和第二区的衬底、第一区上的第一有源图案、第二区上的第二有源图案以及定义第一区和第二区上的第一有源图案和第二有源图案的装置隔离层。残留间隔层设置在第一有源图案中的相邻第一有源图案之间的装置隔离层上。内衬层设置在第二有源图案中的相邻第二有源图案之间的装置隔离层上。第二有源图案之间的间距大于第一有源图案之间的间距，且残留间隔层的底部表面高于内衬层的底部表面。
在一方面，一种半导体装置包含衬底上的有源鳍、覆盖有源鳍的下部部分的侧壁的装置隔离层、有源鳍上的源极/漏极区以及覆盖有源鳍的上部部分的侧壁和源极/漏极区的保护绝缘层。有源鳍的上部部分的侧壁上的保护绝缘层的厚度大于源极/漏极区上的保护绝缘层的厚度。
附图说明
鉴于附图和随附详细描述，本发明概念将变得更清楚。
图1是说明根据本发明概念的一些实施例的半导体装置的平面视图。
图2A到图2H是分别沿图1的线A-A'、线B-B'、线C-C'、线D-D'、线E-E'、线F-F'、线G-G'以及线H-H'截取的横截面视图。
图3、图6、图8以及图10是说明制造根据本发明概念的一些实施例的半导体装置的方法的平面视图。
图4A和图5A是沿图3的线A-A'截取的横截面视图。
图4B和图5B是沿图3的线B-B'截取的横截面视图。
图4C和图5C是沿图3的线C-C'截取的横截面视图。
图4D和图5D是沿图3的线D-D'截取的横截面视图。
图7A、图9A以及图11A是分别沿图6、图8以及图10的线A-A'截取的横截面视图。
图7B、图9B以及图11B是分别沿图6、图8以及图10的线B-B'截取的横截面视图。
图7C、图9C以及图11C是分别沿图6、图8以及图10的线C-C'截取的横截面视图。
图7D、图9D以及图11D是分别沿图6、图8以及图10的线D-D'截取的横截面视图。
图7E、图9E以及图11E是分别沿图6、图8以及图10的线E-E'截取的横截面视图。
图7F、图9F以及图11F是分别沿图6、图8以及图10的线F-F'截取的横截面视图。
图7G、图9G以及图11G是分别沿图6、图8以及图10的线G-G'截取的横截面视图。
图7H、图9H以及图11H是分别沿图6、图8以及图10的线H-H'截取的横截面视图。
图12是沿图1的线C-C'截取的说明根据本发明概念的一些实施例的半导体装置的横截面视图。
图13是说明根据本发明概念的一些实施例的半导体装置的平面视图。
图14A到图14F是分别沿图13的线A-A'、线B-B'、线C-C'、线D-D'、线E-E'以及线F-F'截取的横截面视图。
图15是说明制造根据本发明概念的一些实施例的半导体装置的方法的平面视图。
图16A、图17A、图18A以及图19A是沿图15的线A-A'截取的横截面视图。
图16B、图17B、图18B以及图19B是沿图15的线B-B'截取的横截面视图。
图16C、图17C、图18C以及图19C是沿图15的线C-C'截取的横截面视图。
图16D、17D、图18D以及图19D是沿图15的线D-D'截取的横截面视图。
附图标号说明
100：衬底；
140：第一层间绝缘层；
150：第二层间绝缘层；
A-A'、B-B'、C-C'、D-D'、E-E'、F-F'、G-G'、H-H'：线
AC：接触件；
AG1：第一气隙；
AG2：第二气隙；
AO：绝缘图案；
AP：有源图案；
AP1：第一有源图案；
AP2：第二有源图案；
CH1：第一沟道区；
CH2：第二沟道区；
D1：第一方向；
D2：第二方向；
ESL：蚀刻停止层；
GE：栅极电极；
GI：栅极介电图案；
GP：栅极顶盖图案；
GS：栅极间隔件；
LIN：内衬层；
LIN1：第一内衬层；
LIN2：第二内衬层；
LV1：第一水平；
LV2：第二水平；
MA：掩模图案
MO：模制层
MP：硬掩模图案；
NR：NMOSFET区；
P1：第一距离；
P2：第二距离；
PA1：第一部分；
PA2：第二部分；
PIN：保护绝缘层；
PP：牺牲图案；
PR：PMOSFET区；
RG1：第一区；
RG2：第二区；
RG3：第三区；
RG4：第四区；
RSG：凹进区；
RSL：残留间隔层；
RS：凹进的顶部表面；
SD1：第一源极/漏极区；
SD2：第二源极/漏极区；
ST：装置隔离层；
T1：厚度；
T2：厚度；
TR1：第一沟槽；
TR2：第二沟槽。
具体实施方式
图1是说明根据本发明概念的一些实施例的半导体装置的平面视图。图2A到图2H是分别沿图1的线A-A'、线B-B'、线C-C'、线D-D'、线E-E'、线F-F'、线G-G'以及线H-H'截取的横截面视图。
可设置具有第一区RG1和第二区RG2的衬底100。首先，将在下文参考图1和图2A到图2C详细描述衬底100的第一区RG1。衬底100的第一区RG1可包含PMOSFET区PR和NMOSFET区NR。衬底100可为包含硅、锗或硅锗的半导体衬底，或可为化合物半导体衬底。举例来说，衬底100可为硅衬底。第一区RG1可为其上设置有构成半导体装置的逻辑电路的逻辑晶体管的逻辑单元区。举例来说，构成处理器核心的逻辑晶体管可设置在衬底100的第一区RG1(即，逻辑单元区)上。逻辑晶体管中的一些可设置在第一区RG1上。
装置隔离层ST可设置于衬底100的上部部分中。装置隔离层ST可包含例如氧化硅层等绝缘材料。PMOSFET区PR和NMOSFET区NR可通过将装置隔离层ST插入其间沿第一方向D1使彼此间隔开。第一方向D1可平行于衬底100的顶部表面。PMOSFET区PR和NMOSFET区NR可在与第一方向D1相交的第二方向D2上延伸。PMOSFET区PR与NMOSFET区NR之间的装置隔离层ST相较于有源图案AP1或有源图案AP2之间的装置隔离层ST可更深。
在第二方向D2上延伸的多个有源图案AP1和有源图案AP2可设置于PMOSFET区PR和NMOSFET区NR上。有源图案AP1和有源图案AP2可包含PMOSFET区PR上的第一有源图案AP1和NMOSFET区NR上的第二有源图案AP2。第一有源图案AP1和第二有源图案AP2可为从衬底100的表面突出的衬底100的部分。第一有源图案AP1和第二有源图案AP2可沿第一方向D1布置。
第一沟槽TR1可定义在彼此相邻的第一有源图案AP1之间及彼此相邻的第二有源图案AP2之间。第二沟槽TR2可定义在彼此相邻的PMOSFET区PR与NMOSFET区NR之间。装置隔离层ST可填充第一沟槽TR1和第二沟槽TR2。
填充第一沟槽TR1的装置隔离层ST可定义第一有源图案AP1和第二有源图案AP2。装置隔离层ST可直接覆盖第一有源图案AP1和第二有源图案AP2的下部部分的侧壁。在图1、图2B以及图2C中，三个第一有源图案AP1示出于PMOSFET区PR上，且三个第二有源图案AP2示出于NMOSFET区NR上。然而，本发明概念的实施例不限于此。
第一有源图案AP1和第二有源图案AP2的上部部分可高于装置隔离层ST的顶部表面。第一有源图案AP1和第二有源图案AP2的上部部分可从装置隔离层ST竖直地突出。第一有源图案AP1和第二有源图案AP2的上部部分可具有从装置隔离层ST突出的鳍状物。
第一有源图案AP1的上部部分可包含第一沟道区CH1和第一源极/漏极区SD1。第一源极/漏极区SD1可为P型掺杂剂区。第一沟道区CH1中的每一个可设置在一对彼此相邻的第一源极/漏极区SD1之间。在一些实施例中，在第一方向D1上彼此相邻的三个第一有源图案AP1可共用一个第一源极/漏极区SD1。
第二有源图案AP2的上部部分可包含第二沟道区CH2和第二源极/漏极区SD2。第二源极/漏极区SD2可为N型掺杂剂区。第二沟道区CH2中的每一个可设置在一对彼此相邻的第二源极/漏极区SD2之间。在一些实施例中，在第一方向D1上彼此相邻的三个第二有源图案AP2可共用一个第二源极/漏极区SD2。
第一源极/漏极区SD1和第二源极/漏极区SD2可包含通过选择性外延生长(selective epitaxial growth；SEG)工艺形成的外延图案。第一源极/漏极区SD1和第二源极/漏极区SD2的顶部表面可设置在相较于第一沟道区CH1和第二沟道区CH2的顶部表面较高的水平处。在一些实施例中，PMOSFET区PR上的在第一方向D1上彼此相邻的外延图案可彼此连接以在第一有源图案AP1上构成一个第一源极/漏极区SD1。NMOSFET区NR上的在第一方向D1上彼此相邻的外延图案可彼此连接以在第二有源图案AP2上构成一个第二源极/漏极区SD2。
第一源极/漏极区SD1可包含半导体元素，所述半导体元素的晶格常数大于衬底100的半导体元素的晶格常数。因此，第一源极/漏极区SD1可对第一沟道区CH1提供压缩应力。举例来说，第一源极/漏极区SD1可包含硅锗(SiGe)。第二源极/漏极区SD2可包含半导体元素，所述半导体元素的晶格常数等于或小于衬底100的半导体元素的晶格常数。举例来说，第二源极/漏极区SD2可包含与衬底100相同的半导体元素(例如，硅)。
残留间隔层RSL可设置在第一源极/漏极区SD1与装置隔离层ST之间以及第二源极/漏极区SD2与装置隔离层ST之间。残留间隔层RSL中的每一层可覆盖装置隔离层ST的顶部表面。残留间隔层RSL可包含与栅极间隔件GS相同的材料。
第一气隙AG1可定义在第一源极/漏极区SD1与残留间隔层RSL之间。残留间隔层RSL可定义第一气隙AG1的底部。第二气隙AG2可定义在第二源极/漏极区SD2与残留间隔层RSL之间。残留间隔层RSL可定义第二气隙AG2的底部。
在第一方向D1上延伸的栅极电极GE可设置于第一有源图案AP1和第二有源图案AP2上，以使第一有源图案AP1和第二有源图案AP2相交。栅极电极GE可在第二方向D2上彼此间隔开。栅极电极GE可与第一沟道区CH1和第二沟道区CH2竖直重叠。栅极电极GE中的每一个可环绕第一沟道区CH1和第二沟道区CH2中的每一个的顶部表面和两个侧壁(参看图2B)。举例来说，栅极电极GE可包含导电金属氮化物(例如，氮化钛或氮化钽)或金属材料(例如，钛、钽、钨、铜或铝)中的至少一种。
一对栅极间隔件GS可分别设置在栅极电极GE中的每一个的两个侧壁上。栅极间隔件GS可在第一方向D1上沿栅极电极GE延伸。栅极间隔件GS的顶部表面可高于栅极电极GE的顶部表面。栅极间隔件GS的顶部表面可与稍后将描述的第一层间绝缘层140的顶部表面共面。栅极间隔件GS可包含SiCN、SiCON或SiN中的至少一种。在某些实施例中，栅极间隔件GS中的每一个可具有由SiCN、SiCON或SiN中的至少两种形成的多层结构。
栅极介电图案GI可设置在栅极电极GE与有源图案AP1和有源图案AP2之间。栅极介电图案GI中的每一个可沿栅极电极GE中的每一个的底部表面延伸。栅极介电图案GI中的每一个可覆盖第一沟道区CH1和第二沟道区CH2中的每一个的顶部表面和两个侧壁。栅极介电图案GI可包含高k介电材料。举例来说，高k介电材料可包含氧化铪、氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化锂、氧化铝、氧化铅钪钽或铌酸铅锌中的至少一种。
栅极顶盖图案GP可设置于栅极电极GE中的每一个上。栅极顶盖图案GP可在第一方向D1上沿栅极电极GE延伸。栅极顶盖图案GP可包含相对于稍后将描述的第一层间绝缘层140和第二层间绝缘层150具有蚀刻选择性的材料。举例来说，栅极顶盖图案GP可包含SiON、SiCN、SiCON或SiN中的至少一种。
第一层间绝缘层140可设置于衬底100上。第一层间绝缘层140可覆盖栅极间隔件GS和第一源极/漏极区SD1和第二源极/漏极区SD2。第一层间绝缘层140的顶部表面可与栅极顶盖图案GP的顶部表面和栅极间隔件GS的顶部表面大体上共面。
蚀刻停止层ESL可设置在第一层间绝缘层140与栅极间隔件GS之间、第一层间绝缘层140与源极/漏极区SD1和源极/漏极区SD2之间、以及第一层间绝缘层140与装置隔离层ST之间。举例来说，蚀刻停止层ESL可包含氮化硅层。第二层间绝缘层150可设置在第一层间绝缘层140和栅极顶盖图案GP上。举例来说，第一层间绝缘层140和第二层间绝缘层150中的每一个可包含氧化硅层。
在第一方向D1上彼此间隔开的第一沟道区CH1与第二沟道区CH2之间的装置隔离层ST的顶部表面可高于在第一方向D1上彼此间隔开的第一源极/漏极区SD1与第二源极/漏极区SD2之间的装置隔离层ST的顶部表面(参看图2B和图2C)。换句话说，栅极电极GE下方的装置隔离层ST的顶部表面可高于第一层间绝缘层140下方的装置隔离层ST的顶部表面。
至少一个接触件AC可穿过一对栅极电极GE之间的第二层间绝缘层150和第一层间绝缘层140以便电性连接到第一源极/漏极区SD1和/或第二源极/漏极区SD2。举例来说，接触件AC可包含选自例如铝、铜、钨、钼以及钴等金属材料中的至少一种。
即使未在附图中示出，势垒层可设置在接触件AC与源极/漏极区SD1和源极/漏极区SD2之间。势垒层可包含金属层和/或金属氮化物层。金属层可包含钛、钽、钨、镍、钴或铂中的至少一种。金属氮化物层可包含氮化钛层、氮化钽层、氮化钨层、氮化镍层、氮化钴层或氮化铂层中的至少一种。
在下文中，将参考图1和图2D到图2H详细描述衬底100的第二区RG2。在下文中，出于解释的容易和便利性目的，将省略或简要地提及与参考图1和图2A到图2C所提到的相同的技术特征的描述。
衬底100的第二区RG2可包含PMOSFET区PR和NMOSFET区NR。第二区RG2可为半导体装置的外围电路区。在一些实施例中，第二区RG2可为其上设置有构成输入/输出(input/output；I/O)端子的高压晶体管的外围电路区。
第一有源图案AP1可设置于PMOSFET区PR上，且第二有源图案AP2可设置于NMOSFET区NR上。第二区RG2的第一有源图案AP1之间的在第一方向D1上的距离(或间距)可大于第一区RG1的第一有源图案AP1之间的在第一方向D1上的距离(或间距)。第二区RG2的第二有源图案AP2之间的在第一方向D1上的距离(或间距)可大于第一区RG1的第二有源图案AP2之间的在第一方向D1上的距离(或间距)。第二区RG2的第一有源图案AP1和第二有源图案AP2中的每一个的宽度可大体上等于第一区RG1的第一有源图案AP1和第二有源图案AP2中的每一个的宽度。
第一有源图案AP1的上部部分可包含第一沟道区CH1和第一源极/漏极区SD1。第二有源图案AP2的上部部分可包含第二沟道区CH2和第二源极/漏极区SD2。在一些实施例中，在第一方向D1上彼此相邻的第一有源图案AP1的第一源极/漏极区SD1可构成一个图案(即，一个第一源极/漏极区SD1)，在所述图案中在第一方向D1上彼此相邻的三个外延图案彼此合并。在第一方向D1上彼此相邻的第二有源图案AP2的第二源极/漏极区SD2可构成一个图案(即，一个第二源极/漏极区SD2)，在所述图案中在第一方向D1上彼此相邻的三个外延图案彼此合并。
第二区RG2的第一源极/漏极区SD1的尺寸可大于第一区RG1的第一源极/漏极区SD1的尺寸，且第二区RG2的第二源极/漏极区SD2的尺寸可大于第一区RG1的第二源极/漏极区SD2的尺寸。
在第二区RG2上，第一源极/漏极区SD1下方的第一气隙AG1可大于第二源极/漏极区SD2下方的第二气隙AG2。第一气隙AG1下方的装置隔离层ST可具有凹进的顶部表面RS。换句话说，第一气隙AG1下方的装置隔离层ST可朝向衬底100的底部表面凹进。第一气隙AG1下方的装置隔离层ST的凹进的顶部表面RS可低于第二气隙AG2下方的装置隔离层ST的顶部表面。在一些实施例中，不同于第一区RG1，残留间隔层RSL可能不会存在于第二区RG2的第一气隙AG1和第二气隙AG2中。
保护绝缘层PIN可设置于第二区RG2的NMOSFET区NR上。保护绝缘层PIN可包含第二内衬层LIN2和蚀刻停止层ESL。第二内衬层LIN2可覆盖第二区RG2的NMOSFET区NR上的装置隔离层ST的顶部表面。第二内衬层LIN2还可覆盖第二源极/漏极区SD2下方的第二有源图案AP2的上部部分的侧壁。第二内衬层LIN2可定义第二区RG2的第二气隙AG2的底部。第二内衬层LIN2可能不会存在于第二沟道区CH2与栅极电极GE之间。第二内衬层LIN2的底部表面可高于第一气隙AG1下方的装置隔离层ST的凹进的顶部表面RS。
第二内衬层LIN2可防止第二有源图案AP2倾斜。更详细地说，第二内衬层LIN2可将施加到第二有源图案AP2的应力减少或减到最小。举例来说，第二内衬层LIN2可包含与蚀刻停止层ESL相同的材料(例如，氮化硅层)。氮化硅层可向第二有源图案AP2提供张应力，且由此可改进N沟道MOS场效应晶体管(N-channel MOS field effect transistor；NMOSFET)的电特性。另外，氮化硅层可保护第二源极/漏极区SD2。
保护绝缘层PIN可覆盖第二有源图案AP2的上部部分的侧壁和第二源极/漏极区SD2。第二有源图案AP2中的至少一个的上部部分的侧壁上的保护绝缘层PIN的厚度T1可大于第二源极/漏极区SD2上的保护绝缘层PIN的厚度T2。这可能是因为第二有源图案AP2中的至少一个的上部部分的侧壁上的保护绝缘层PIN包含第二内衬层LIN2和蚀刻停止层ESL，而第二源极/漏极区SD2上的保护绝缘层PIN仅包含蚀刻停止层ESL。
第二区RG2的栅极电极GE中的每一个的宽度可大于第一区RG1的栅极电极GE中的每一个的宽度。第二区RG2的PMOSFET区PR上的装置隔离层ST的凹进的顶部表面RS可低于与其相邻的栅极电极GE的底部表面。绝缘图案AO可设置在第二区RG2的NMOSFET区NR上的第二内衬层LIN2与栅极电极GE之间。第二区RG2的第二气隙AG2可由彼此相邻的栅极间隔件GS、彼此相邻的绝缘图案AO、第二源极/漏极区SD2以及第二内衬层LIN2包围(参看图2E和图2H)。举例来说，绝缘图案AO可包含与装置隔离层ST相同的材料(例如，氧化硅层)。
图3、图6、图8以及图10是说明制造根据本发明概念的一些实施例的半导体装置的方法的平面视图。图4A和图5A是沿图3的线A-A'截取的横截面视图。图4B和图5B是沿图3的线B-B'截取的横截面视图。图4C和图5C是沿图3的线C-C'截取的横截面视图。图4D和图5D是沿图3的线D-D'截取的横截面视图。图7A、图9A以及图11A是分别沿图6、图8以及图10的线A-A'截取的横截面视图。图7B、图9B以及图11B是分别沿图6、图8以及图10的线B-B'截取的横截面视图。图7C、图9C以及图11C是分别沿图6、图8以及图10的线C-C'截取的横截面视图。图7D、图9D以及图11D是分别沿图6、图8以及图10的线D-D'截取的横截面视图。图7E、图9E以及图11E是分别沿图6、图8以及图10的线E-E'截取的横截面视图。图7F、图9F以及图11F是分别沿图6、图8以及图10的线F-F'截取的横截面视图。图7G、图9G以及图11G是分别沿图6、图8以及图10的线G-G'截取的横截面视图。图7H、图9H以及图11H是分别沿图6、图8以及图10的线H-H'截取的横截面视图。
参考图3和图4A到图4D，可设置具有第一区RG1和第二区RG2的衬底100。第一区RG1可为逻辑单元区，且第二区RG2可为外围电路区。衬底100可被图案化以形成有源图案AP1和有源图案AP2。更详细地说，有源图案AP1和有源图案AP2的形成可包含在衬底100上形成掩模图案，以及使用掩模图案作为蚀刻掩模各向异性地蚀刻衬底100。第一沟槽TR1可在有源图案AP1与有源图案AP2之间形成。
第一区RG1上的有源图案AP1之间的在第一方向D1上的距离(即，间距)与有源图案AP2之间的在第一方向D1上的距离(即，间距)可为第一距离P1。第二区RG2上的有源图案AP1之间的在第一方向D1上的距离(即，间距)与有源图案AP2之间的在第一方向D1上的距离(即，间距)可为第二距离P2。可执行图案化工艺使得第二距离P2大于第一距离P1。在一些实施例中，第一区RG1上的有源图案AP1和有源图案AP2中的每一个的宽度可大体上等于第二区RG2上的有源图案AP1和有源图案AP2中的每一个的宽度。
第一区RG1的PMOSFET区PR和NMOSFET区NR上的有源图案AP1和有源图案AP2可保留，而第一区RG1的另一区上的有源图案AP1和有源图案AP2可被去除。更详细地说，可形成掩模图案以覆盖第一区RG1的PMOSFET区PR和NMOSFET区NR，且可使用掩模图案作为蚀刻掩模来执行蚀刻工艺。因此，第一有源图案AP1可保留在PMOSFET区PR上，且第二有源图案AP2可保留在NMOSFET区NR上。第二区RG2的PMOSFET区PR和NMOSFET区NR上的有源图案AP1和有源图案AP2也可保留，而第二区RG2的另一区上的有源图案AP1和有源图案AP2也可被去除。
比第一沟槽TR1更深的第二沟槽TR2可形成于第一区RG1的PMOSFET区PR与NMOSFET区NR之间。详细地说，第二沟槽TR2可通过蚀刻第一区RG1的PMOSFET区PR与NMOSFET区NR之间的衬底100的上部部分而形成。
可形成装置隔离层ST以填充衬底100的第一区RG1和第二区RG2的第一沟槽TR1和第二沟槽TR2。更详细地说，可形成绝缘层(例如，氧化硅层)以完全填充第一沟槽TR1和第二沟槽TR2。绝缘层可完全覆盖第一有源图案AP1和第二有源图案AP2。绝缘层可凹进直到暴露第一有源图案AP1和第二有源图案AP2的上部部分。
第一区RG1上的绝缘层可凹进(或被蚀刻)，使得第一区RG1的装置隔离层ST的顶部表面可设置在第一水平LV1处。第二区RG2上的绝缘层可凹进(或被蚀刻)，使得第二区RG2的装置隔离层ST的顶部表面可设置在第二水平LV2处。第二水平LV2可低于第一水平LV1。由于第二区RG2上的有源图案AP1之间的第二距离P2与有源图案AP2之间的第二距离P2大于第一区RG1上的有源图案AP1之间的第一距离P1与有源图案AP2之间的第一距离P1，因此第二区RG2上的绝缘层可被蚀刻大于第一区RG1上的绝缘层。换句话说，第二区RG2上的绝缘层的蚀刻量可大于第一区RG1上的绝缘层的蚀刻量。
可形成第一内衬层LIN1以覆盖第一区RG1和第二区RG2上的第一有源图案AP1的暴露的上部部分。可形成第二内衬层LIN2以覆盖第一区RG1和第二区RG2上的第二有源图案AP2的暴露的上部部分。第一内衬层LIN1和第二内衬层LIN2可由氮化硅层、多晶硅层或氧化硅层中的至少一种形成。第一内衬层LIN1和第二内衬层LIN2可包含彼此相同的材料或可包含彼此不同的材料。在本实施例中，第一内衬层LIN1可包含多晶硅层，且第二内衬层LIN2可包含氮化硅层。
第一内衬层LIN1和第二内衬层LIN2可分别选择性地在第一有源图案AP1和第二有源图案AP2上形成。举例来说，第一内衬层LIN1可通过使用选择性地打开PMOSFET区PR的掩模在第一有源图案AP1上形成，且第二内衬层LIN2可通过使用选择性地打开NMOSFET区NR的掩模在第二有源图案AP2上形成。
第一内衬层LIN1和第二内衬层LIN2可防止第一有源图案AP1和第二有源图案AP2倾斜。更详细地说，第一内衬层LIN1和第二内衬层LIN2可将施加到第一有源图案AP1和第二有源图案AP2的应力减少或减到最小。
参考图3和图5A到图5D，绝缘图案AO可在第二区RG2的第一内衬层LIN1和第二内衬层LIN2上形成。更详细地说，额外绝缘层可在衬底100的整个顶部表面上形成以完全覆盖第一有源图案AP1和第二有源图案AP2。额外绝缘层可被蚀刻直到暴露第一有源图案AP1和第二有源图案AP2的上部部分。第二区RG2上的额外绝缘层可被蚀刻以形成绝缘图案AO。
在一些实施例中，可执行蚀刻工艺直到第一区RG1上的第一内衬层LIN1和第二内衬层LIN2被去除。在某些实施例中，蚀刻工艺可在第一区RG1上的第一内衬层LIN1和第二内衬层LIN2被完全去除之前完成。因此，第一内衬层LIN1和第二内衬层LIN2还可保留在第一区RG1上，即使未在附图中示出。
由于第二区RG2上的装置隔离层ST的顶部表面低于第一区RG1上的装置隔离层的顶部表面，因此第一内衬层LIN1和第二内衬层LIN2的部分可在蚀刻工艺之后保留在第二区RG2上。第一内衬层LIN1和第二内衬层LIN2上的绝缘图案AO也可保留。保留在第二区RG2上的第一内衬层LIN1和第二内衬层LIN2可覆盖第二区RG2的第一有源图案AP1和第二有源图案AP2的侧壁的至少部分。
参考图6和图7A到图7H，可对衬底100执行热处理工艺。由于第一内衬层LIN1是由本实施例中的多晶硅层构成，因此第一内衬层LIN1可在热处理工艺期间被氧化。因此，氧化硅层可由第二区RG2上的第一内衬层LIN1形成。氧化的第一内衬层LIN1和绝缘图案AO可构成装置隔离层ST(或包含在其中)(参看图7G和图7H)。相反，第二区RG2上的第二内衬层LIN2可在热处理工艺之后保留。
可形成牺牲图案PP以使第一有源图案AP1和第二有源图案AP2相交。牺牲图案PP可具有在第一方向D1上延伸的线性形状或杆形状。更详细地说，牺牲图案PP的形成可包含在衬底100的整个顶部表面上形成牺牲层，在牺牲层上形成硬掩模图案MP，以及使用硬掩模图案MP作为蚀刻掩模来图案化牺牲层。牺牲层可包含多晶硅层。第二区RG2上的牺牲图案PP中的每一个的宽度可大于第一区RG1上的牺牲图案PP中的每一个的宽度。
一对栅极间隔件GS可分别在牺牲图案PP中的每一个的两个侧壁上形成。栅极间隔件GS的形成可包含在衬底100的整个顶部表面上保形地形成间隔层，以及各向异性地蚀刻间隔层。举例来说，间隔层可包含SiCN、SiCON或SiN中的至少一种。对于另一实例，间隔层可由包含SiCN、SiCON或SiN中的至少两种的多层形成。
牺牲图案PP中的每一个的两侧处的有源图案AP1和有源图案AP2上的间隔层可通过各向异性蚀刻工艺蚀刻，且由此可形成残留间隔层RSL。残留间隔层RSL可与栅极间隔件GS同时形成，且可包含与栅极间隔件GS相同的材料。由于第二区RG2上的有源图案AP1之间的第二距离P2与有源图案AP2之间的第二距离P2大于第一区RG1上的有源图案AP1之间的第一距离P1与有源图案AP2之间的第一距离P1，因此第二区RG2上的残留间隔层RSL的蚀刻可大于第一区RG1上的残留间隔层RSL的蚀刻。因此，第二区RG2上的残留间隔层RSL的厚度可小于第一区RG1上的残留间隔层RSL的厚度。
参考图8和图9A到图9H，第一源极/漏极区SD1可在PMOSFET区PR上的牺牲图案PP中的每一个的两侧形成，且第二源极/漏极区SD2可在NMOSFET区NR上的牺牲图案PP中的每一个的两侧形成。
更详细地说，可使用硬掩模图案MP和栅极间隔件GS作为蚀刻掩模来蚀刻第一有源图案AP1和第二有源图案AP2的上部部分以形成凹进区RSG。由于第一区RG1上的残留间隔层RSL相对较厚，因此其部分可在蚀刻工艺之后保留。第一区RG1上的残留间隔层RSL可保护在蚀刻工艺期间设置在其下方的装置隔离层ST。
由于第二区GR2上的残留间隔层RSL相对较薄，因此第二区RG2上的残留间隔层RSL在蚀刻工艺期间可被完全去除。由于残留间隔层RSL完全去除，因此第二区RG2的PMOSFET区PR上的装置隔离层ST可能在蚀刻工艺期间过蚀刻。因此，第二区RG2的PMOSFET区PR上的装置隔离层ST可具有凹进的顶部表面RS。第二区RG2的NMOSFET区NR上的第二内衬层LIN2可保护在蚀刻工艺期间设置在其下方的装置隔离层ST。因此，第二区RG2的NMOSFET区NR上的装置隔离层ST的顶部表面可设置在相较于第二区RG2的PMOSFET区PR上的装置隔离层ST的凹进的顶部表面RS的较高水平处。
第一源极/漏极区SD1可通过执行使用第一有源图案AP1的凹进区RSG的内部表面作为晶种层的选择性外延生长(SEG)来形成。由于形成了第一源极/漏极区SD1，因此第一沟道区CH1可限定在一对第一源极/漏极区SD1之间。举例来说，SEG工艺可包含化学气相沉积(chemical vapor deposition；CVD)工艺或分子束外延(molecular beam epitaxy；MBE)工艺。第一源极/漏极区SD1可包含半导体元素，所述半导体元素的晶格常数大于衬底100的半导体元素的晶格常数。举例来说，第一源极/漏极区SD1可包含硅锗(SiGe)。
第二源极/漏极区SD2可通过执行使用第二有源图案AP2的凹进区RSG的内部表面作为晶种层的SEG工艺来形成。由于形成了第二源极/漏极区SD2，因此第二沟道区CH2可限定在一对第二源极/漏极区SD2之间。举例来说，第二源极/漏极区SD2可包含硅。
第一源极/漏极区SD1和第二源极/漏极区SD2可通过彼此不同的工艺依次形成。换句话说，第一源极/漏极区SD1可不与第二源极/漏极区SD2同时形成。
在本实施例中，外延图案可在SEG工艺期间彼此合并，且由此可在第一方向D1上彼此相邻的第一有源图案AP1上形成一个第一源极/漏极区SD1。因此，第一气隙AG1可在第一源极/漏极区SD1与装置隔离层ST之间形成。在本实施例中，外延图案可在SEG工艺期间彼此合并，且由此可在第一方向D1上彼此相邻的第二有源图案AP2上形成一个第二源极/漏极区SD2。因此，第二气隙AG2可在第二源极/漏极区SD2与装置隔离层ST之间形成。
参考图10和图11A到图11H，蚀刻停止层ESL可保形地在衬底100的整个顶部表面上形成。蚀刻停止层ESL可直接覆盖第一源极/漏极区SD1和第二源极/漏极区SD2。蚀刻停止层ESL可包含氮化硅层。在第二区RG2的NMOSFET区NR上，蚀刻停止层ESL和第二内衬层LIN2可构成保护绝缘层PIN。
可形成第一层间绝缘层140以覆盖第一源极/漏极区SD1和第二源极/漏极区SD2、硬掩模图案MP以及栅极间隔件GS。举例来说，第一层间绝缘层140可包含氧化硅层。
可使第一层间绝缘层140平坦化直到暴露牺牲图案PP的顶部表面。可使用回蚀刻工艺或化学机械抛光(chemical mechanical polishing；CMP)工艺来执行第一层间绝缘层140的平坦化工艺。可在平坦化工艺期间完全地去除硬掩模图案MP。因此，第一层间绝缘层140的顶部表面可与牺牲图案PP的顶部表面和栅极间隔件GS的顶部表面大体上共面。
牺牲图案PP可分别用栅极电极GE置换。更详细地说，可选择性地去除暴露的牺牲图案PP。可使用选择性地蚀刻硅的湿式蚀刻工艺来执行牺牲图案PP的去除。在湿式蚀刻工艺期间，可通过第二区RG2的PMOSFET区PR上的第一气隙AG1向第一源极/漏极区SD1提供蚀刻溶液。然而，由于第一源极/漏极区SD1是由硅锗(SiGe)构成，因此即使将蚀刻溶液提供到第一源极/漏极区SD1，第一源极/漏极区SD1也可能不被蚀刻。在另一方面，由于第二源极/漏极区SD2是由硅形成，因此如果将蚀刻溶液提供到第二源极/漏极区SD2，那么第二源极/漏极区SD2可被蚀刻。然而，根据本发明概念的一些实施例，第二内衬层LIN2可保留在牺牲图案PP下方以防止蚀刻溶液被提供到第二区RG2的第二气隙AG2中。在第一区RG1上，残留间隔层RSL可存在于牺牲图案PP与第二源极/漏极区SD2之间以防止第二源极/漏极区SD2在湿式蚀刻工艺期间被蚀刻。
栅极介电图案GI、栅极电极GE以及栅极顶盖图案GP可在通过去除牺牲图案PP而形成的空隙中的每一个中形成。栅极介电图案GI可保形地在空隙中形成且可能不完全填充所述空隙。可使用原子层沉积(atomic layer deposition；ALD)工艺或化学氧化工艺来形成栅极介电图案GI。栅极介电图案GI可包含高k介电材料。举例来说，高k介电材料可包含氧化铪、氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化锂、氧化铝、氧化铅钪钽或铌酸铅锌中的至少一种。
可形成栅极电极层以完全填充空隙，且可对栅极电极层执行平坦化工艺以形成栅极电极GE。举例来说，栅极电极层可包含导电金属氮化物(例如，氮化钛或氮化钽)或金属材料(例如，钛、钽、钨、铜或铝)中的至少一种。
随后，可使栅极电极GE的上部部分凹进。栅极顶盖图案GP可分别在凹进的栅极电极GE上形成。栅极顶盖图案GP可分别完全填充栅极电极GE上的凹进区。举例来说，栅极顶盖图案GP可包含SiON、SiCN、SiCON或SiN中的至少一种。
再次参考图1和图2A到图2H，第二层间绝缘层150可在第一层间绝缘层140和栅极顶盖图案GP上形成。第二层间绝缘层150可包含氧化硅层或低k氧化层。举例来说，低k氧化层可包含掺杂有碳的氧化硅层，例如SiCOH。第二层间绝缘层150可通过CVD工艺形成。
可形成接触件AC以穿过第二层间绝缘层150和第一层间绝缘层140。接触件AC可连接到第一源极/漏极区SD1和第二源极/漏极区SD2。更详细地说，接触件AC的形成可包含形成穿过第二层间绝缘层150和第一层间绝缘层140的接触孔，以及形成填充接触孔的导电层。举例来说，导电层可包含铝、铜、钨、钼或钴中的至少一种。
随后，即使未在附图中示出，额外的层间绝缘层和金属内连线可在第二层间绝缘层150上形成。
图12是沿图1的线C-C'截取的说明根据本发明概念的一些实施例的半导体装置的横截面视图。在本实施例中，出于解释的容易和便利性目的，将省略与图1和图2A到图2H的实施例中相同的技术特征的描述。换句话说，将在下文中主要描述本发明实施例与图1和图2A到图2H的实施例之间的差异。
参考图1、图2H以及图12，第二内衬层LIN2可设置于第一区RG1的NMOSFET区NR以及第二区RG2的NMOSFET区NR上。第一区RG1的NMOSFET区NR的第二内衬层LIN2可设置在装置隔离层ST与残留间隔层RSL之间。第一区RG1的NMOSFET区NR上的第二内衬层LIN2和蚀刻停止层ESL可构成第一区RG1的保护绝缘层PIN。第一区RG1的NMOSFET区NR上的第二内衬层LIN2的底部表面的水平可高于第二区RG2的NMOSFET区NR上的第二内衬层LIN2的底部表面的水平。
图13是说明根据本发明概念的一些实施例的半导体装置的平面视图。图14A到图14F是分别沿图13的线A-A'、线B-B'、线C-C'、线D-D'、线E-E'以及线F-F'截取的横截面视图。在本实施例中，出于解释的容易和便利性目的，将省略与图1和图2A到图2H的实施例中相同的技术特征的描述。换句话说，将在下文中主要描述本发明实施例与图1和图2A到图2H的实施例之间的差异。
参考图13和图14A到图14F，可设置具有第三区RG3和第四区RG4的衬底100。第三区RG3和第四区RG4可为其上设置有构成逻辑电路的逻辑晶体管的逻辑单元区或其上设置有构成I/O端子的高压晶体管的外围电路区。
在第二方向D2上延伸的多个有源图案AP可设置于第三区RG3和第四区RG4上。第三区RG3上的有源图案AP的宽度可大体上等于第四区RG4上的有源图案AP的宽度。第三区RG3上彼此相邻的有源图案AP之间的距离(或间距)可大体上等于第四区RG4上彼此相邻的有源图案AP之间的距离(或间距)。
第一沟槽TR1可限定在第三区RG3上彼此相邻的有源图案AP之间。第二沟槽TR2可限定在第四区RG4上彼此相邻的有源图案AP之间。第二沟槽TR2相较于第一沟槽TR1可更深。换句话说，第三区RG3上的有源图案AP的高度(即，竖直长度)可小于第四区RG4上的有源图案AP的高度。
第四区RG4上的有源图案AP中的每一个可包含第一部分PA1和第一部分PA1上的第二部分PA2。第一部分PA1可对应于有源图案AP的下部部分，且第二部分PA2可对应于有源图案AP的上部部分。第一方向D1上的有源图案AP的宽度可随与衬底100的底部表面的距离增加而减小。有源图案AP的宽度在第一部分PA1与第二部分PA2之间的边界处可急剧地(不连续地)减小。换句话说，有源图案AP的侧壁可具有第一部分PA1与第二部分PA2之间的边界处的阶梯式轮廓。
内衬层LIN可设置于第四区RG4上的有源图案AP的第二部分PA2的两个侧壁上。内衬层LIN的外侧壁可与有源图案AP的第一部分PA1的侧壁对准。举例来说，内衬层LIN可包含氮化硅层、氧化硅层或多晶硅层中的至少一种。在某些实施例中，内衬层LIN可具有由氮化硅层、氧化硅层或多晶硅层中的至少两种形成的多层结构。在另一方面，内衬层可能不存在于第三区RG3上。
在本实施例中，第三区RG3和第四区RG4上的所有晶体管可为P沟道MOS场效应晶体管(P-channel MOS field effect transistor；PMOSFET)或N沟道MOS场效应晶体管(N-channel MOS field effect transistor；NMOSFET)。或者，第三区RG3的晶体管的导电类型可不同于第四区RG4的晶体管的导电类型。然而，本发明概念的实施例不限于此。
图15是说明制造根据本发明概念的一些实施例的半导体装置的方法的平面视图。图16A、图17A、图18A以及图19A是沿图15的线A-A'截取的横截面视图。图16B、图17B、图18B以及图19B是沿图15的线B-B'截取的横截面视图。图16C、图17C、图18C以及图19C是沿图15的线C-C'截取的横截面视图。图16D、图17D、图18D以及图19D是沿图15的线D-D'截取的横截面视图。在本实施例中，出于解释的容易和便利性目的，将省略与图3到图11H的实施例中相同的技术特征的描述。换句话说，将在下文中主要描述本发明实施例与图3到图11H的实施例之间的差异。
参考图15和图16A到图16D，可设置具有第三区RG3和第四区RG4的衬底100。第三区RG3和第四区RG4可为逻辑单元区或外围电路区。衬底100可被图案化以形成有源图案AP。有源图案AP的形成可包含在衬底100上形成掩模图案MA，以及使用掩模图案MA作为蚀刻掩模各向异性地蚀刻衬底100。第一沟槽TR1可在有源图案AP之间形成。
参考图15和图17A到图17D，模制层MO可在第三区RG3上形成。模制层MO可完全覆盖第三区RG3上的有源图案AP。模制层MO可暴露第四区RG4。
可形成内衬层LIN以覆盖第四区RG4上的有源图案AP的暴露的侧壁。更详细地说，内衬层LIN可保形地在衬底100上形成，且保形内衬层LIN可各向异性地蚀刻。因此，具有间隔物形状的内衬层LIN可在第四区RG4的有源图案AP的侧壁上形成。在另一方面，第三区RG3可由模制层MO保护，且由此内衬层LIN可能并不在第三区RG3的有源图案AP上形成。
参考图15和图18A到图18D，可使用模制层MO、掩模图案MA以及内衬层LIN作为蚀刻掩模来蚀刻衬底100以在第四区RG4的衬底100中形成第二沟槽TR2。由于模制层MO，第三区RG3的衬底100可能不在蚀刻工艺期间被蚀刻。第四区RG4的第二沟槽TR2相较于第三区RG3的第一沟槽TR1可更深。同时，第四区RG4上的有源图案AP中的每一个可包含第一部分PA1和第一部分PA1上的第二部分PA2。
由于内衬层LIN在蚀刻工艺中被用作蚀刻掩模，因此第四区RG4的有源图案AP的第一部分PA1的侧壁可与内衬层LIN的外侧壁对准。第四区RG4的有源图案AP的侧壁可具有第一部分PA1与第二部分PA2之间的边界处的阶梯式轮廓。
参考图15和图19A到图19D，可去除模制层MO。装置隔离层ST可在第一沟槽TR1和第二沟槽TR2中形成。更详细地说，绝缘层可在衬底100上形成以完全覆盖有源图案AP。可使绝缘层平坦化直到暴露有源图案AP的顶部表面。此时，可去除掩模图案MA。此后，平坦化的绝缘层可凹进以暴露有源图案AP的上部部分。凹进的绝缘层可对应于装置隔离层ST。当绝缘层凹进时，也可使内衬层LIN凹进。
再次参考图13和图14A到图14F，如上文参考图6到图11H所描述，可形成牺牲图案，源极/漏极区SD可在牺牲图案中的每一个的两侧形成，且牺牲图案可由栅极电极GE置换。
在根据本发明概念的一些实施例的半导体装置中，内衬层可设置在有源图案之间的距离相对较宽的区上。内衬层可保护NMOSFET的源极/漏极。另外，内衬层可防止有源图案倾斜，且可向NMOSFET的沟道提供张应力。
虽然已参考实例实施例描述本发明概念，但对于所属领域的技术人员显而易见的是可在不脱离本发明概念的精神和范围的情况下作出各种改变和修改。因此，应理解，以上实施例并非限制性的，而是说明性的。因此，本发明概念的范围将通过所附权利要求和其等效物的最广泛容许的解释来确定，且将不受前述描述的约束或限制。

Claims (17)

1.一种半导体装置，其特征在于，包括：
在衬底上的第一有源图案以及第二有源图案；
第一源极/漏极区，在所述第一有源图案上；
第二源极/漏极区，在所述第二有源图案上；
装置隔离层，填充所述第一有源图案中的相邻第一有源图案之间的第一沟槽以及所述第二有源图案中的相邻第二有源图案之间的第二沟槽；
内衬层，在所述第二有源图案中的所述相邻第二有源图案之间的所述装置隔离层上；以及
蚀刻停止层，在所述内衬层上，
其中所述第一有源图案中的所述相邻第一有源图案之间的所述装置隔离层在所述第一源极/漏极区下方具有凹槽，且其中所述相邻第二有源图案之间的所述内衬层的底部表面高于所述凹槽，
其中第一气隙限定在所述第一源极/漏极区与所述凹槽之间，以及其中第二气隙限定在所述第二源极/漏极区与所述内衬层之间。
2.根据权利要求1所述的半导体装置，其中所述内衬层覆盖所述第二有源图案的上部部分的侧壁以及所述第二有源图案之间的所述装置隔离层的顶部表面。
3.根据权利要求1所述的半导体装置，进一步包括：
第一沟道区，在所述第一有源图案的上部部分中；
第二沟道区，在所述第二有源图案的上部部分中；
第一栅极电极，在所述第一沟道区上；
第二栅极电极，在所述第二沟道区上；以及
绝缘图案，设置在所述第二栅极电极与所述内衬层之间。
4.根据权利要求1所述的半导体装置，其中所述内衬层包括氮化硅层。
5.根据权利要求1所述的半导体装置，其中所述第一有源图案和所述第二有源图案中的每一个具有从所述装置隔离层竖直突出的上部部分。
6.一种半导体装置，其特征在于，包括：
衬底，具有第一区以及第二区；
第一有源图案，在所述第一区上；
第二有源图案，在所述第二区上；
装置隔离层，限定所述第一区以及所述第二区上的所述第一有源图案以及所述第二有源图案；
残留间隔层，在所述第一有源图案中的相邻第一有源图案之间的所述装置隔离层上；
内衬层，在所述第二有源图案中的相邻第二有源图案之间的所述装置隔离层上；以及
蚀刻停止层，在所述内衬层上，
其中所述第二有源图案之间的间距大于所述第一有源图案之间的间距，以及
其中所述残留间隔层的底部表面高于所述内衬层的底部表面。
7.根据权利要求6所述的半导体装置，进一步包括：
第一栅极电极，穿过所述第一有源图案；
第二栅极电极，穿过所述第二有源图案；以及
栅极间隔件，在所述第一栅极电极以及所述第二栅极电极中的每一个的两个侧壁上，
其中所述残留间隔层包含与所述栅极间隔件相同的材料。
8.根据权利要求7所述的半导体装置，其中所述第一栅极电极的宽度小于所述第二栅极电极的宽度。
9.根据权利要求6所述的半导体装置，其中所述内衬层覆盖所述第二有源图案中的所述相邻第二有源图案的上部部分的侧壁以及所述第二有源图案中的所述相邻第二有源图案之间的所述装置隔离层的顶部表面。
10. 根据权利要求6所述的半导体装置，进一步包括：
第一源极/漏极区，在所述第一有源图案上；以及
第二源极/漏极区，在所述第二有源图案上，
其中第一气隙限定在所述第一源极/漏极区与所述残留间隔层之间，以及
其中第二气隙限定在所述第二源极/漏极区与所述内衬层之间。
11.根据权利要求10所述的半导体装置，其中所述第一源极/漏极区以及所述第二源极/漏极区具有相同的导电类型或不同的导电类型。
12.根据权利要求6所述的半导体装置，其中所述第一有源图案中的每一个的宽度等于所述第二有源图案中的每一个的宽度。
13.根据权利要求6所述的半导体装置，其中所述内衬层包括第一内衬层，以及其中所述半导体装置进一步包括：
第二内衬层，设置在所述残留间隔层与所述装置隔离层之间，所述装置隔离层设置在所述第一有源图案中的所述相邻第一有源图案之间，
其中所述第二内衬层的底部表面高于所述第一内衬层的所述底部表面。
14.根据权利要求6所述的半导体装置，其中所述第一有源图案以及所述第二有源图案中的每一个具有从所述装置隔离层竖直突出的上部部分。
15.一种半导体装置，其特征在于，包括：
有源鳍，在衬底上；
装置隔离层，覆盖所述有源鳍的下部部分的侧壁；
源极/漏极区，在所述有源鳍上；
保护绝缘层，覆盖所述有源鳍的上部部分的侧壁以及所述源极/漏极区，其中所述保护绝缘层包括：
内衬层，从所述有源鳍的所述上部部分的所述侧壁延伸到所述装置隔离层的顶部表面上；以及
蚀刻停止层，在所述内衬层上且覆盖所述源极/漏极区以及所述有源鳍的所述上部部分的所述侧壁；
栅极电极，穿过所述有源鳍；以及
绝缘图案，设置在所述栅极电极与所述内衬层之间，其中所述绝缘图案的顶部表面低于所述有源鳍的顶部表面，
其中在所述有源鳍的所述上部部分的所述侧壁上的所述保护绝缘层的厚度大于在所述源极/漏极区上的所述保护绝缘层的厚度。
16.根据权利要求15所述的半导体装置，其中所述内衬层以及所述蚀刻停止层中的每一个包含氮化硅层。
17.根据权利要求15所述的半导体装置，其中设置多个所述有源鳍，
其中所述装置隔离层设置在相邻的有源鳍之间，
其中所述源极/漏极区设置在所述相邻的有源鳍上，以及
其中气隙限定在所述源极/漏极区与所述装置隔离层之间。
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