CN109326515A - 半导体装置的形成方法 - Google Patents
半导体装置的形成方法 Download PDFInfo
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- CN109326515A CN109326515A CN201711205277.8A CN201711205277A CN109326515A CN 109326515 A CN109326515 A CN 109326515A CN 201711205277 A CN201711205277 A CN 201711205277A CN 109326515 A CN109326515 A CN 109326515A
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- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910021354 zirconium(IV) silicide Inorganic materials 0.000 description 1
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Abstract
本公开实施例提供一种半导体装置的形成方法,包含在半导体鳍上形成虚设栅极结构,在虚设栅极结构的相对两侧上形成介电层,以及移除虚设栅极结构,以在介电层中形成凹陷。此方法还包含在凹陷的侧壁和底部上依序形成栅极介电层和至少一导电层,以及用含氟的化学物质处理栅极介电层和上述至少一导电层。
Description
技术领域
本公开实施例涉及半导体装置制造技术,且具体涉及鳍式场效晶体管的半导体装置及其形成方法。
背景技术
由于各种电子元件(例如:晶体管、二极管、电阻器、电容器等)的集成密度(integration density)不断的提升,半导体产业已经历快速成长。在大多数情况下,集成密度的提升来自于最小部件(feature)尺寸的不断缩减,其使得更多的元件能被整合至指定的面积内。
鳍式场效晶体管(Fin Field-Effect Transistor,FinFET)装置越来越常用于集成电路之中。鳍式场效晶体管装置具有三维结构,其包含半导体鳍自基底突出。栅极结构配置为控制鳍式场效晶体管装置的导电沟道中的电荷载体的流动,且栅极结构围绕半导体鳍。举例而言,在三栅极(tri-gate)鳍式场效晶体管装置中,栅极结构围绕半导体鳍的三个面,借此在半导体鳍的三个面上形成导电沟道。
发明内容
根据一些实施例,半导体装置的形成方法包含在半导体鳍上形成虚设栅极结构,在虚设栅极结构的相对两侧上形成介电层,移除虚设栅极结构,以在介电层中形成凹陷,在凹陷的侧壁和底部上依序形成栅极介电层和至少一导电层,以及用含氟(F)的化学物质处理栅极介电层和上述至少一导电层。
根据一些实施例,鳍式场效晶体管(Fin Field-Effect Transistor,FinFET)的形成方法包含提供基底,其具有鳍突出于隔离结构的上表面上方,且隔离结构设置于鳍的相对两侧上,在鳍上形成第一栅极结构,形成层间介电层围绕第一栅极结构,且层间介电层露出第一栅极结构的上表面,移除第一栅极结构,以在层间介电层中形成凹陷,以及在凹陷内形成层堆叠,其中形成层堆叠包含在凹陷内顺应地形成高介电常数介电层,在高介电常数介电层上顺应地形成导电盖层,及在导电盖层上顺应地形成导电的阻挡层。此方法还包含使用包含氟的化学物质对层堆叠执行表面处理工艺,其中表面处理工艺驱使氟进入高介电常数介电层,以及在表面处理工艺之后,执行热退火工艺。
根据又一些实施例,半导体装置的形成方法包含形成介电层,用至少一导电层覆盖介电层,在上述至少一导电层上供应含氟前驱物,以及驱使含氟前驱物的氟进入介电层。
附图说明
为了更完整的理解本公开实施例及其优点,以下配合所附附图作详细说明。
图1为鳍式场效晶体管(FinFET)的透视示意图。
图2至图20为根据一些实施例的鳍式场效晶体管装置在各个制造阶段的剖面示意图。
图21为根据一些实施例说明半导体装置的形成方法的流程图。
附图标记说明:
30 鳍式场效晶体管;
32 基底;
34 隔离区;
36 鳍;
38 栅极介电层;
40 栅极电极;
42、44 源极/漏极区;
50 基底;
52 垫氧化物层;
56 垫氮化物层;
58 掩模;
60 半导体条;
61 沟槽;
62 隔离区;
64 鳍(半导体鳍);
65 轻掺杂漏极区;
66 虚设栅极介电层;
68 虚设栅极层;
70 掩模层;
72 第一栅极闸隔物;
75 虚设栅极结构;
80 外延源极/漏极区;
82 区域(硅化物区);
84 前驱物(化学物质、含氟气体、含氟等离子体);
86 第二栅极间隔物;
87 栅极间隔物;
88 膜;
90 第一层间介电层;
91、93 接触开口;
92 凹陷;
94 栅极介电层;
95 第二层间介电层;
96 盖层;
97 栅极结构(取代栅极);
98、104 阻挡层;
99 栅极电极;
100 鳍式场效晶体管装置;
102 接触件;
108 籽晶层;
110 导电材料;
121 层堆叠;
510、610 热退火工艺;
1000 方法;
1010、1020、1030、1040、1050 步骤;
A-A、B-B、C-C 剖面。
具体实施方式
以下内容提供许多不同实施例或范例,用于实现本公开实施例的不同部件(feature)。以下描述各部件及其排列方式的具体范例,以简化本公开实施例。当然,这些仅仅是范例,而非意图限制本公开实施例。例如,在以下描述中提及在第二部件上方或其上形成第一部件,其可包含第一部件和第二部件以直接接触的方式形成的实施例,并且也可包含在第一部件和第二部件之间形成额外的部件,使得第一部件和第二部件不直接接触的实施例。此外,本公开实施例可在各个范例中重复参考标号和/或字母。此重复是为了简单和清楚的目的,其本身并非用于指定所讨论的各个实施例和/或配置之间的关系。
再者,为了容易描述,在此可以使用例如“在…底下”、“在…下方”、“下”、“在…上方”、“上”等空间相关用语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件之间的关系。除了图中所示的方位外,空间相关用语可涵盖装置在使用或操作中的不同方位。装置可以采用其他方位定向(旋转90度或在其他方位上),并且在此使用的空间相关描述可以同样地作出相应的解释。
本公开实施例在形成半导体装置的背景下进行讨论,且特别是在改善鳍式场效晶体管装置的栅极氧化物的可靠度的背景下进行讨论。然而,本领域普通技术人员可轻易理解的是,本公开实施例所公开的方法可用于其它装置或应用中,例如平面式(planar)装置。
图1示出说明鳍式场效晶体管(FinFET)30的一范例的透视示意图。鳍式场效晶体管30包含具有鳍36的基底32。基底32具有形成在其上的隔离区34,且鳍36从相邻的隔离区34之间突出于隔离区34之上。栅极介电层38沿着鳍36的侧壁且在鳍36的顶面上,且栅极电极40在栅极介电层38上。源极/漏极区42和44在鳍36中,且位于栅极介电层38和栅极电极40的相对两侧。图1更示出在后续附图中所使用的参考剖面。剖面B-B沿鳍式场效晶体管30的栅极电极40的纵轴延伸。剖面C-C平行于剖面B-B,且跨过源极/漏极区42。剖面A-A垂直于剖面B-B且沿着鳍36的纵轴,并且在例如源极/漏极区42和44之间的电流方向上。为了清楚明了,后续附图参照这些参考剖面。
图2至图20示出根据一些实施例的鳍式场效晶体管装置100在各个制造阶段的剖面示意图。除了多个鳍以外,鳍式场效晶体管装置100类似于图1的鳍式场效晶体管30。图2至图5示出鳍式场效晶体管装置100沿着剖面B-B的剖面示意图,且图6至图20示出沿着剖面A-A的剖面示意图。
图2绘示基底50的剖面示意图。基底50可为半导体基底,例如整体半导体(bulksemiconductor)、绝缘体上的半导体(semiconductor-on-insulator,SOI)基底或类似基底,且基底50可被掺杂(例如,用P型或N型的掺杂物)或不掺杂。基底50可为晶片,例如硅晶片。一般而言,绝缘体上的半导体(SOI)基底包含一层半导体材料形成在绝缘层上。绝缘层例如可为埋藏氧化物(buried oxide,BOX)层、氧化硅层或类似绝缘层。在基底上提供绝缘层,基底通常为硅或玻璃基底。也可使用其它基底,例如多层或梯度基底(gradientsubstrate)。在一些实施例中,基底50的半导体材料可包含硅;锗;化合物半导体,其包含碳化硅(silicon carbide)、砷化镓(gallium arsenic)、磷化镓(gallim phosphide)、磷化铟(indium phosphide)、砷化铟(indium arsenide)和/或锑化铟(indium antimonide);合金半导体,其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或前述的组合。
基底50可包含集成电路装置(未示出)。如本领域普通技术人员所了解的,可于基底50中和/或上形成各式各样的集成电路装置,例如晶体管(transistor)、二极管(diode)、电容器(capacitor)、电阻器(resistor)、类似的装置或前述的组合,以产生用于鳍式场效晶体管的结构和功能上的设计需求。可使用任何合适的方法形成集成电路装置。
参阅图3,使用例如光刻(photolithography)和蚀刻技术将图2所示的基底50图案化。举例而言,于基底50上形成掩模层,掩模层例如为垫氧化物(pad oxide)层52和上方的垫氮化物层56。垫氧化物层52可为薄膜,其包含例如使用热氧化工艺形成的氧化硅。垫氧化物层52可作为基底50和上方的垫氮化物层56之间的粘着层,且可作为蚀刻垫氮化层56的蚀刻停止层(etch stop layer)。在一些实施例中,垫氮化物层56由氮化硅(siliconnitride)、氮氧化硅(silicon oxynitride)、碳化硅(silicon carbide)、氮碳化硅(silicon carbonnitride)、类似材料或前述的组合形成,且例如可使用低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)或等离子体增强化学气相沉积(plasma enhanced chemical vapor deposition,PECVD)形成垫氮化物层56。
可使用光刻技术将掩模层图案化。一般而言,光刻技术使用光致抗蚀剂材料(未示出),并将光致抗蚀剂材料沉积、照辐射(曝光)和显影,以移除部分的光致抗蚀剂材料。剩余的光致抗蚀剂材料保护底下的材料,例如在此范例中的掩模层,使其免于受到后续的工艺步骤例如蚀刻的伤害。在此范例中,使用光致抗蚀剂材料将垫氧化物层52和垫氮化物层56图案化,以形成图案化的掩模58,如图3所示出。
图案化的掩模58接着用来将基底50露出的部分图案化,以形成沟槽61,借此在相邻的沟槽61之间定义出半导体条(strips)60,如图3所示出。在一些实施例中,通过在基底50中蚀刻出沟槽来形成半导体条60,其使用例如反应性离子蚀刻(reactive ion etch,RIE)、中性束蚀刻(neutral beam etch,NBE)、类似蚀刻或前述的组合,蚀刻可为异向性。在一些实施例中,沟槽61可为彼此平行的条状(从顶部看)且紧密地与彼此隔开。在一些实施例中,沟槽61可为连续的且围绕半导体条60。在半导体条60形成之后,可通过蚀刻或任何合适的方法移除图案化的掩模58。
图4示出在相邻的半导体条60之间形成绝缘材料,以形成隔离区62。绝缘材料可为氧化物例如氧化硅、氮化物、类似材料或前述的组合,且可通过高密度等离子体化学气相沉积(high density plasma chemical vapor deposition,HDP-CVD)、可流动的化学气相沉积(flowable CVD,FCVD)(例如:在远距等离子体系统中以化学气相沉积为基础的材料沉积,且之后硬化使沉积材料转变为另一材料,例如氧化物)、类似沉积或前述的组合来形成。可使用其它绝缘材料和/或其它形成工艺。在说明的实施例中,绝缘材料为利用可流动的化学气相沉积(FCVD)工艺形成的氧化硅。一旦形成绝缘材料,就可执行退火工艺。平坦化工艺,例如化学机械研磨(chemical mechanical polish,CMP),可移除任何多余的绝缘材料(和图案化的掩模58,如果有的话),且形成共平面(未示出)的隔离区62的顶面和半导体条60的顶面。
在一些实施例中,隔离区62包含衬垫(liner),例如衬垫氧化物(未示出),其位于隔离区62和基底50/半导体条60之间的界面。在一些实施例中,形成衬垫氧化物,以减少在基底50和隔离区62之间的界面处的结晶缺陷。类似地,衬垫氧化物也可用于减少在半导体条60和隔离区62之间的界面处的结晶缺陷。衬垫氧化物(例如氧化硅)可为热氧化物,其通过将基底50的表层热氧化而形成,尽管其它合适的方法也可用于形成衬垫氧化物。
接着,将隔离区62凹陷,以形成浅沟槽隔离(shallow trench isolation,STI)区。将隔离区62凹陷,使得半导体条60的上部从相邻的隔离区62之间突出,并形成半导体鳍64(也称为鳍64)。隔离区62的顶面可具有平坦表面(如图所示)、外凸表面、内凹表面(例如碟状)或前述的组合。通过合适的蚀刻,隔离区62的顶面可形成为平坦、外凸和/或内凹。可使用可接受的蚀刻工艺,例如对隔离区62的材料有选择性的蚀刻,将隔离区62凹陷。例如,可使用化学氧化物移除,其利用蚀刻或Applied Materials SICONI设备或稀释氢氟酸(diluted hydrofluoric acid,dHF)。
图2至图4示出形成鳍64的实施例,但可在各种不同工艺中形成鳍。在一些范例中,可在基底的顶面上形成介电层;可穿过介电层蚀刻出沟槽;可在沟槽中外延成长同质外延结构;以及可将介电层凹陷,使得同质外延结构从介电层突出,以形成鳍。在另一些示范例中,可使用异质外延结构用于鳍。例如,可将半导体条凹陷,以及在凹陷处中外延生长与半导体条不同的材料。
在又一些范例中,可在基底的顶面上形成介电层;可穿过介电层蚀刻出沟槽;可使用与基底不同的材料在沟槽中外延生长异质外延结构;以及可将介电层凹陷,使得异质外延结构从介电层突出,以形成鳍。
在一些外延生长同质外延或异质外延结构的实施例中,生长的材料可在生长过程中进行原位(in situ)掺杂,其可免除之前或后续的注入,尽管原位和注入掺杂可一起使用。再者,在NMOS区中外延生长与PMOS区的材料不同的材料可能是有好处的。在各种实施例中,鳍可包含硅锗(silicon germanium)(SixGe1-x,其中x可介于大约0和1之间)、碳化硅、纯或大致上纯的锗、第III-V族化合物半导体、第II-VI族化合物半导体或类似材料。例如,用于形成第III-V族化合物半导体的可用材料包含,但不限于,InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP及类似材料。
图5示出在半导体鳍64上形成虚设栅极结构75。在一些实施例中,虚设栅极结构75包含虚设栅极介电层66和虚设栅极层68。虚设栅极结构75可还包含掩模层70。为了形成虚设栅极结构75,在半导体鳍64和隔离区62上形成虚设栅极介电层66。虚设栅极介电层66例如可为氧化硅、氮化硅、多层的前述材料、或类似材料,且可根据可接受的技术沉积或热生长虚设栅极介电层66。在一些实施例中,虚设栅极介电层66可为高介电常数介电材料,且在这些实施例中,虚设栅极介电层66可具有大于约7.0的介电常数值,且可包含Hf、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或硅酸盐、多层的前述材料和前述的组合。虚设栅极介电层66的形成方法可包含分子束沉积(molecular-beam deposition,MBD)、原子层沉积(atomiclayer deposition,ALD)、等离子体增强化学气相沉积(PECVD)和类似方法。
在虚设栅极介电层66上形成虚设栅极层68,且在虚设栅极层68上形成掩模层70。虚设栅极层68可沉积于虚设栅极介电层66上,然后例如通过化学机械研磨(CMP)将虚设栅极层68平坦化。掩模层70可沉积于虚设栅极层68上。虚设栅极层68可由例如多晶硅形成,尽管其它材料也可使用。在一些实施例中,虚设栅极层68可包含含金属的材料,例如TiN、TaN、TaC、Co、Ru、Al、前述的组合或多层的前述材料。掩模层70可由例如氮化硅或类似材料形成。
在这些层(例如虚设栅极介电层66、虚设栅极层68和掩模层70)形成之后,使用可接受的光刻和蚀刻技术将掩模层70图案化,以形成图案化的掩模层70。然后通过可接受的蚀刻技术,可将掩模层70的图案转移至虚设栅极层68和虚设栅极介电层66,以分别形成图案化的虚设栅极层68和图案化的虚设栅极介电层66。虚设栅极层68和虚设栅极介电层66覆盖半导体鳍64各自的沟道。虚设栅极层68也可具有纵向方向,其大致上垂直于各自的半导体鳍64的纵向方向。
图6至图20示出沿剖面A-A(沿鳍的纵轴),鳍式场效晶体管装置100的进一步工艺的剖面示意图。如图6所示出,在鳍64中形成轻掺杂漏极(lightly doped drain,LDD)区65。可通过等离子体掺杂工艺形成轻掺杂漏极区65。等离子体掺杂工艺可将N型或P型杂质注入鳍64中,以形成轻掺杂漏极区65。在一些实施例中,轻掺杂漏极区65邻接鳍式场效晶体管装置100的沟道区。部分的轻掺杂漏极区65可延伸至虚设栅极层68底下,且进入鳍式场效晶体管装置100的沟道区。图6示出的轻掺杂漏极区65的范例并未限定本公开实施例。轻掺杂漏极区65也可能有其它配置、形状和形成方法,并且这些都包含在本公开实施例的范围内。举例而言,可在第一栅极间隔物72形成之后,形成轻掺杂漏极区65。
继续参阅图6,在形成轻掺杂漏极区65之后,在虚设栅极结构上形成栅极间隔物87。栅极间隔物87可包含第一栅极间隔物72和第二栅极间隔物86。在图6的范例中,在虚设栅极层68的相对两侧壁和虚设栅极介电层66的相对两侧壁上形成第一栅极间隔物72。第一栅极间隔物72也可延伸至半导体鳍64的上表面和隔离区62的上表面(见图5)上。如图6所示,在第一栅极间隔物72上形成第二栅极间隔物86。第一栅极间隔物72可由氮化物,例如氮化硅、氮氧化硅(silicon oxynitride)、碳化硅(silicon carbide)、碳氮化硅(siliconcarbonitride)、类似材料或前述的组合形成,且可使用例如热氧化、化学气相沉积(CVD)或其它合适合沉积工艺而形成。第二栅极间隔物86可由氮化硅、碳氮化硅(SiCN)、前述的组合或类似材料,使用合适的沉积方法形成。
在一些示范的实施例中,通过先在鳍式场效晶体管装置100上顺应性地沉积第一栅极间隔物72,然后在沉积的第一栅极间隔物72上顺应性地沉积第二栅极间隔物86,以形成栅极间隔物87。如本领域普通技术人员所理解的,在本公开实施例中,顺应的(conformal)(或顺应性地(conformally))意思为在工艺变化(process variation)中是顺应的(或顺应性地)。举例而言,顺应的第一栅极间隔物72的水平部分和垂直部分可具有大致上相同的厚度,垂直部分的垂直厚度和水平部分的水平厚度的差值小于,例如水平厚度的20%。接着,执行异向性蚀刻工艺,例如干式蚀刻工艺,以移除第二栅极间隔物86的第一部分,其位于鳍式场效晶体管装置100的上表面(例如半导体鳍64的上表面)上,且保留第二栅极间隔物86的第二部分沿着虚设栅极结构的侧壁设置。在异向性蚀刻工艺之后,保留第二栅极间隔物86的第二部分形成第二栅极间隔物86。异向性蚀刻工艺也移除部分的第一栅极间隔物72,其位于第二栅极间隔物86的侧壁之外,且第一栅极间隔物72的剩余部分形成第一栅极间隔物72。
图6所示的第一栅极间隔物72和第二栅极间隔物86的形状和形成方法仅为范例,而非限定本公开实施例,且其它形状和形成方法也有可能。举例而言,第二栅极间隔物86可在形成外延源极/漏极区80(见图7)之后形成。在一些实施例中,在图7所示的外延源极/漏极区80的外延工艺之前,在第一栅极间隔物72上形成虚设栅极间隔物,且在外延源极/漏极区80形成之后,移除虚设栅极间隔物并用第二栅极间隔物86取代。
接着,如图7所示出,形成外延源极/漏极区80。外延源极/漏极区80的形成是通过蚀刻鳍64以形成凹陷,并且使用合适的方法在凹陷中外延生长材料,合适的方法例如金属有机化学气相沉积(metal-organic CVD,MOCVD)、分子束外延(molecular beam epitaxy,MBE)、液相外延(liquid phase epitaxy,LPE)、气相外延(vapor phase epitaxy,VPE)、选择性外延生长(selective epitaxial growth,SEG)、类似方法或前述的组合。在外延生长外延源极/漏极区80之后,可通过合适的方法,例如蚀刻,移除掩模层70。
如图7所示,外延源极/漏极区80可具有从鳍64的各自表面升起的表面(例如升起高过鳍64的未凹陷部分),且可具有小切面(facet)。在一些实施例中,相邻的鳍64的外延源极/漏极区80可合并在一起,以形成连续的外延源极/漏极区80。在一些实施例中,相邻的鳍64的外延源极/漏极区80不会合并在一起,且维持分开的外延源极/漏极区80。在产生的鳍式场效晶体管为N型鳍式场效晶体管的一些示范实施例中,外延源极/漏极区80包含碳化硅(SiC)、磷化硅(SiP)、掺杂磷的碳化硅(SiCP)或类似材料。在产生的鳍式场效晶体管为P型鳍式场效晶体管的另一些示范实施例中,外延源极/漏极区80包含SiGe和P型杂质,例如硼或铟。
可将掺杂物注入外延源极/漏极区80,以形成源极/漏极区80,之后执行退火。注入工艺可包含形成掩模及将掩模图案化,掩模例如为光致抗蚀剂,以覆盖鳍式场效晶体管被保护而免于注入工艺的区域。外延源极/漏极区80的杂质(例如掺杂物)浓度可在约10E19cm-3至约10E21cm-3的范围内。在一些实施例中,在生长期间可对外延源极/漏极区80进行原位(in situ)掺杂。
接着,如图8所示出,在图7所示的结构上形成第一层间介电层(interlayerdielectric,ILD)90,且执行栅极后(gate-last)工艺(有时称为取代栅极(replacementgate)工艺)。在栅极后工艺中,虚设栅极层68和虚设栅极介电层66(见图7)被视为虚设结构,且会被移除并用主动栅极和主动栅极介电层取代,这些可统称为取代栅极。
在一些实施例中,第一层间介电层90由介电材料形成,例如磷硅酸盐玻璃(phosphosilicate glass、PSG)、硼硅酸盐玻璃(borosilicate glass,BSG)、掺杂硼的磷硅酸盐玻璃(boron-doped phosphosilicate Glass,BPSG)、无掺杂的硅酸盐玻璃(undopedsilicate glass,USG)或类似材料,并且可通过合适的方法,例如化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)或可流动的化学气相沉积(FCVD)来沉积介电材料。可执行平坦化工艺,例如化学机械研磨(CMP)工艺,以将第一层间介电层90的顶面平坦化,使得第一层间介电层90的顶面与虚设栅极层68(见图7)的顶面齐平。因此,在一些实施例中,于化学机械研磨工艺之后,露出虚设栅极层68的顶面。
根据一些实施例,在蚀刻步骤中移除虚设栅极层68和在虚设栅极层68正下方的虚设栅极介电层66,使得凹陷92在每一个鳍64中形成。每一个凹陷92露出各自的鳍64的沟道区。每一个沟道区设置于相邻的一对外延源极/漏极区80之间。在移除虚设栅极结构的期间,当蚀刻虚设栅极层68时,虚设栅极介电层66可作为蚀刻停止层(etch stop layer)。在移除虚设栅极层68之后,可接着移除虚设栅极介电层66。
接着,在图9中,在鳍式场效晶体管装置100上依续形成栅极介电层94、盖层96和阻挡层98。如图9所示,在凹陷92中和第一层间介电层90的顶面上顺应性地沉积栅极介电层94。在栅极介电层94上顺应性地形成盖层96和阻挡层98,其中盖层96在栅极介电层94和阻挡层98之间。盖层96可作为鳍式场效晶体管装置100的功函数层(work function layer),且阻挡层98可作为鳍式场效晶体管装置100的蚀刻停止层。在下文中,栅极介电层94、盖层96和阻挡层98可统称为层堆叠121。
根据一些实施例,栅极介电层94包含氧化硅、氮化硅或多层的前述材料。在另一些实施例中,栅极介电层94包含高介电常数介电材料,且在这些实施例中,栅极介电层94可具有大于约7.0的介电常数值,且可包含Hf、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或硅酸盐,和前述的组合。栅极介电层94的形成方法可包含分子束沉积(MBD)、原子层沉积(ALD)、等离子体增强化学气相沉积(PECVD)和类似方法。在一些示范的实施例中,栅极介电层94为包含HfO2的高介电常数介电材料,且通过合适的方法形成,例如原子层沉积(ALD)。在一些实施例中,栅极介电层94为高介电常数介电材料,且在栅极介电层94和鳍64之间形成氧化硅层(例如SiO2)。可通过将鳍64的材料氧化或通过任何合适的沉积方法,例如化学气相沉积(CVD)、物理气相沉积(PVD)或原子层沉积(ALD),形成氧化硅层。
接着,在栅极介电层94上顺应性地形成盖层96。盖层96包含任何适用于功函数层的材料。栅极结构97(见图15)所包含的示范P型功函数金属包含TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其它合适的P型功函数金属或前述的组合。栅极结构97所包含的示范N型功函数金属包含Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其它合适的N型功函数金属或前述的组合。功函数值与功函数层的材料组成有关,因此选择第一功函数层的材料,以调整其功函数值,使得在各自的区域形成的装置达到目标的临界电压(threshold voltage,Vt)。可通过化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)和/或其它合适的工艺沉积功函数层。
接着,在盖层96上顺应性地形成阻挡层98。阻挡层98可包含导电材料,例如氮化钛(titanium nitride),尽管其它材料也可替代使用,例如氮化钽(tantalum nitride)、钛、钽或类似材料。可使用化学气相沉积(CVD)工艺形成阻挡层98,例如等离子体增强化学气相沉积(PECVD)。然而,也可替代地使用其它替代工艺,例如溅镀(supttering)或金属有机化学气相沉积(MOCVD)、原子层沉积(ALD)。在一些实施例中,阻挡层98和盖层96包含不同的材料,以在阻挡层98和盖层96之间提供蚀刻选择性。在一些示范的性实施例中,盖层96包含TiN且阻挡层98包含TaN,并且可使用合适的沉积方法,例如原子层沉积(ALD),形成盖层96和阻挡层98。
接着,如图10至图11所示出,使用含氟的化学物质(也可称为含氟前驱物)通过表面处理工艺处理层堆叠121,以将栅极介电层94掺杂氟,且后续执行热退火工艺,以进一步增加栅极介电层94的掺杂物(例如氟)的浓度。特别是,图10示出表面处理工艺包含浸泡(soak)工艺的实施例,其中层堆叠121浸泡于前驱物84中,其可为含氟气体或含氟等离子体,且图11示出在浸泡工艺后,执行热退火工艺。图12和图13示出表面处理工艺对栅极介电层94进行掺杂的实施例,其通过使用含氟前驱物,在层堆叠121上沉积薄膜88(见图12),且热退火工艺(见图13)更驱使掺杂物(例如氟)进入栅极介电层94。表面处理工艺和热退火工艺的细节在下文讨论。
根据一些实施例,表面处理工艺驱使氟(例如氟自由基(fluorine radical))从层堆叠121的上表面(例如阻挡层98的上表面)进入栅极介电层94,有效地将栅极介电层94掺杂氟,且增加栅极介电层94中的氟浓度。在一些实施例中,用氟掺杂栅极介电层94可改善鳍式场效晶体管装置100的时依性介电层崩溃(time-dependent dielectric breakdown,TDDB)表现。
在金属氧化物半导体场效晶体管(metal-oxide-semiconductor field-effecttransistor,MOSFET)中,时依性介电层崩溃(TDDB)为失效机制,在此栅极氧化物崩溃为长时间应用相对低的电场的结果(与立即的崩溃相反,其由强的电场造成)。当金属氧化物半导体场效晶体管在接近或超出其特定操作电压操作时,由于电子穿隧电流(electrontunneling current)形成通过栅极氧化物到基底的导电路径而造成崩溃。
根据一些实施例,表面处理工艺包含让层堆叠121受到含氟的化学物质(例如化学物质84)影响。化学物质(例如化学物质84)的分子组成可以用MFx表示,其中F代表氟,M代表另一合适的元素,且x代表F与M的分子比值。在一些实施例中,元素M为金属,例如钨(W)、钼(Mo)、钛(Ti)、铁(Fe)、镍(Ni)、钴(Co)、铬(Cr)、铜(Cu)、铝(Al)、锰(Mn)、硅(Si)、钙(Ca)、锆(Zr)、铌(Nb)、铪(Hf)、钽(Ta)、铅(Pb)或类似金属。在其它实施例中,元素M可为非金属,例如氮(N)、碳(C)、硫(S)、氯(Cl)或类似非金属。化学物质84的范例可包含六氟化钨(WF6)、三氟化氮(NF3)、六氟化钼(MoF6)、FeF2、FeF3、NiF2、CoF2、CrF2、CrF3、CuF、MoF3、TiF3、TiF4、AlF3、SiF4、MnF2、ZrF4、NbF5、HfF4、TaF5、NaF、KF、LiF、MgF2、CaF2、BaF2、ZnF2、PbF2、CF4、C2F6、SF6、C3F8或CHF3。
现在参阅图10,在一些实施例中,表面处理工艺为热工艺,其使用含氟气体作为化学物质84。举例而言,可使用WF6、FeF2、FeF3、NiF2、CoF2、CrF2、CrF3、CuF、MoF3、TiF3、TiF4、AlF3、SiF4、MnF2、ZrF4、NbF5、HfF4、TaF5、NaF、KF、LiF、MgF2、CaF2、BaF2、ZnF2、PbF2、CF4、C2F6、SF6、C3F8或CHF3气体作为化学物质84。如图10所示,供应含氟气体84与阻挡层98的表面接触。可用载体气体运送含氟气体84,载体气体可为惰性气体,例如N2、Ar、He、类似气体或前述的组合。在一些实施例中,热工艺的能量(例如热能量)打断F和元素M之间的键结(例如,使用WF6作为化学物质84时,F和W之间的键结),并且产生氟的自由基。作为范例,WF6的分解可用以下化学方程式(1)表示。
WF6→W+6F(1)
在热工艺之后,可在阻挡层98上形成包含元素M(例如钨(W))的层(未示出)。热工艺驱使氟的自由基进入层堆叠121并朝向栅极介电层94。在一些实施例中,通过热工艺驱使氟的自由基进入栅极介电层94。氟的自由基可补偿在栅极介电层94和相邻的介电层(例如第一层间介电层90和/或第一栅极间隔物72)之间的界面处的俘获态(trap state),借此减少在界面处的俘获态密度(Dit)。
可调整表面处理工艺的参数,例如温度和/或表面处理工艺的持续时间、化学物质84的流速,以达到在栅极介电层94中的氟的目标浓度。举例而言,低温(例如低于200℃)和/或短持续时间(例如短于30秒)可能无法驱使足够的氟进入栅极介电层94来达到目标氟浓度。另一方面,高温(例如高于650℃)和/或长持续时间(例如超过于30秒)可驱使氟通过栅极介电层94且进入相邻的介电层(例如第一层间介电层90或第一栅极间隔物72)。
在一些示范的实施例中,使用WF6气体在约200℃和约650℃之间的温度执行热工艺。WF6的流速可在约5标准立方公分每分钟(standard cubic centimeter per minute,sccm)和约10000sccm之间,例如1000sccm。载体气体的流速可在约5sccm和约10000sccm之间,例如6000sccm。热工艺的压力可在约0.5torr和约300torr之间,例如20torr,且热工艺的持续时间可在约0.1秒和约300秒之间,例如100秒。
继续参阅图10,在一些实施例中,表面处理工艺为等离子体工艺,其使用含氟等离子体作为化学物质84。举例而言,可将NF3气体活化成等离子体,并作为化学物质84。可用载体气体运送化学物质(含氟等离子体)84,载体气体可为惰性气体,例如N2、Ar、He、类似气体或前述的组合。如图10所示,供应化学物质(含氟等离子体)84与阻挡层98的表面接触。等离子体工艺的能量(例如放电能量)打断F和元素M(例如,F和N)之间的键结,并且产生氟的自由基。举例而言,NF3等离子体轰击阻挡层98的表面,因此打断F和N之间的键结,且引发许多化学反应。NF3等离子体的分解由以下化学方程式(2)和(3)说明。
NF3→NF++2F (2)
NF3→NF2 ++F (3)
来自化学物质84的分解的元素M(例如N)可形成副产物,其可从鳍式场效晶体管装置100所在的沉积腔(未示出)中抽出(例如用泵),或是可在阻挡层98上形成包含元素M的层(未示出)。等离子体工艺的能量驱使氟的自由基进入层堆叠121朝向栅极介电层94。在一些实施例中,通过等离子体工艺驱使氟的自由基进入栅极介电层94。
在一些示范的实施例中,使用NF3气体的等离子体在温度约20℃和约400℃之间执行等离子体工艺。等离子体工艺的能量在约5伏特(volt)和约10000volt之间,例如500volt。NF3的流速可在约10sccm和约5000sccm之间,例如200sccm。载体气体的流速可在约5sccm和约10000sccm之间,例如3000sccm。等离子体工艺的压力在约0.5托(torr)和约300torr之间,例如15torr,且等离子体工艺的持续时间可在约0.1秒和约300秒之间,例如100秒。
接着,如图11所示出,在表面处理工艺(例如热工艺或等离子体工艺)之后,可执行选择性的热退火工艺510,以进一步驱使层堆叠121所含的氟(例如,盖层96和阻挡层98中的氟自由基)进入栅极介电层94。在一些示范的实施例中,在温度约400℃和约700℃之间,例如550℃,执行热退火工艺510,且持续时间在约0.1秒和约300秒之间,例如30秒。在热退火工艺510后,氟的浓度范围达到在1E15/cm2和1E17/cm2之间。
现在参阅图12和图13。图12和图13分别地示出表面处理工艺的另一些实施例和后续的热退火工艺。如图12所示出,表面处理工艺包含使用含氟前驱物(未示出)在阻挡层98上形成膜88。举例而言,可使用六氟化钨(WF6)或六氟化钼(MoF6)作为含氟前驱物,以形成膜88。其它可用于形成膜88的含氟前驱物包含FeF2、FeF3、NiF2、CoF2、CrF2、CrF3、CuF、MoF3、TiF3、TiF4、AlF3、SiF4、MnF2、ZrF4、NbF5、HfF4、TaF5、NaF、KF、LiF、MgF2、CaF2、BaF2、ZnF2和PbF2。可通过载体气体运送前驱物,载体气体可为惰性气体,例如N2、Ar、He、类似气体或前述的组合。可使用合适的沉积方法,例如原子层沉积(ALD)、物理气相沉积(PVD)、化学气相沉积(CVD)、类似沉积或前述的组合,以形成膜88。
在一些实施例中,含氟前驱物(例如WF6或MoF6)在沉积工艺的期间分解,借此打断前驱物的F和元素M(例如W或Mo)之间的键结。在前驱物分解之后,前驱物的元素M形成膜88,且在分解之后,沉积工艺的能量(例如热能量)驱使氟进入层堆叠121朝向栅极介电层94。举例而言,当在沉积工艺中使用WF6或MoF6作为前驱物时,膜88可包含钨(W)层或钼(Mo)层。膜88也可含有氟和少量的未分解前驱物。在一些实施例中,于沉积工艺期间驱使氟进入栅极介电层94。
在一些示范的实施例中,表面处理工艺包含使用含氟前驱物在约200℃和约500℃之间的温度下,例如350℃形成膜88。前驱物的流速可在约10sccm和约5000sccm之间,例如500sccm。载体气体的流速可在约5sccm和约10000sccm之间,例如3000sccm。沉积工艺用于形成膜88的压力可在约0.5torr和约300torr之间,例如20torr。膜88的厚度可在约和约之间,例如尽管其它尺寸也有可能。
接着,如图13所示出,在图12的表面处理工艺之后,可执行选择性的热退火工艺610,以进一步驱使层堆叠121所含的氟(例如盖层96和阻挡层98中的氟自由基)进入栅极介电层94。在一些示范的实施例中,热退火工艺610在温度约400℃和约700℃之间,例如550℃执行,且持续时间在约0.1秒和约300秒之间,例如30秒。在热退火工艺610后,氟的浓度范围达到在1E15/cm2和1E17/cm2之间。
如前文所讨论,表面处理工艺(例如热工艺、等离子体工艺或膜沉积工艺)可在阻挡层98的表面上形成包含元素M(例如W、Mo)的层(未示出)。在一些实施例中,在填充凹陷92之前,通过合适的工艺,例如蚀刻,移除这层元素M。在另一些实施例中,未移除包含元素M的层。作为替代地,包含元素M的层保留在阻挡层98上,且用来作为部分的功函数层,以调整鳍式场效晶体管装置100的临界电压Vt。为了简化,包含元素M的层(如果没移除)未示出于后续的附图中。
表面处理工艺的实施例具有许多好处。随着半导体装置的尺寸在高级工艺节点(advanced processing node)中愈变愈小,由于例如鳍和/或栅极结构太过靠近,可用于掺杂鳍式场效晶体管装置的栅极介电层的离子注入工艺的注入角度受到限制。因此,离子注入工艺可能无法掺杂栅极介电层的某些区域,使其达到目标掺杂浓度。本公开实施例提供各种非破坏性和有效的方法来掺杂栅极介电层。因此,鳍式场效晶体管装置100的时依性介电层崩溃(TDDB)表现得以改善。在公开的表面处理工艺中所使用的工艺步骤,例如浸泡工艺、膜沉积和蚀刻,其在半导体制造中为成熟的工艺步骤,且可轻易地使用。此外,在表面处理工艺中使用的原材料为低成本的材料,因此允许低成本的表面处理工艺。再者,公开的表面处理工艺可轻易地与现有的取代栅极(replacement gate)工艺整合。举例而言,在此公开的表面处理工艺不会改变所形成的金属栅极膜堆叠,因此确保与现有的工艺流程有良好的相容性。
接着,如图14至图20所示出,在图10至图13所示的表面处理工艺之后,继续执行工艺。参阅图14,栅极电极99沉积于阻挡层98之上,且填充凹陷92的剩余部分。栅极电极99可由含金属的材料制成,例如Cu、Al、W、类似材料、前述材料的组合或多层的前述材料,且可通过例如电镀(electroplating)、无电解电镀(electroless plating)、物理气相沉积(PVD)、化学气相沉积(CVD)或其它合适的方法形成。
接着,如图15所示出,可执行平坦化工艺,例如化学机械研磨,以移除栅极介电层94、盖层96、阻挡层98和栅极电极99的材料的多余部分,多余部分在第一层间介电层90的顶面上。栅极电极99、阻挡层98、盖层96和栅极介电层94的材料所产生的剩余部分因此而形成所产生的鳍式场效晶体管装置100的取代栅极97。
接着,在图16中,沉积第二层间介电层95于第一层间介电层90之上。在一些实施例中,第二层间介电层95为可流动的膜,其通过可流动的化学气相沉积(CVD)法形成。在一些实施例中,第二层间介电层95由介电材料形成,例如磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)、无掺杂的硅酸盐玻璃(USG)或类似材料,且可通过任何合适的方法沉积,例如化学气相沉积(CVD)和等离子体增强化学气相沉积(PECVD)。用于接触件102(见图20)的接触开口91和93穿过第一层间介电层90和/或第二层间介电层95形成。举例而言,接触开口91穿过第二层间介电层95形成,且露出取代栅极97,且接触开口93穿过第一层间介电层90和第二层间介电层95形成,且露出外延源极/漏极区80。在单一剖面图中示出接触开口91/93作为范例,接触开口91/93可在不同的剖面图中。
接着,在图17中,在第二层间介电层95上形成阻挡层104。在一些实施例中,阻挡层104在第二层间介电层95上顺应性地形成,且衬垫于接触开口91/93的侧壁和底部。阻挡层104可包含导电材料,例如钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或类似材料,且可使用化学气相沉积(CVD)形成,例如等离子体增强化学气相沉积(PECVD)。然而,其它替代工艺也可使用,例如溅镀或金属有机化学气相沉积(MOCVD)、物理气相沉积(PVD)、原子层沉积(ALD)。
在一些实施例中,在外延源极/漏极区80上方,例如在外延源极/漏极区80和阻挡层104之间,形成硅化物区82。可在形成阻挡层104之前,形成硅化物区82,尽管也可在形成阻挡层104的工艺期间形成硅化物区82。硅化物区82的形成可通过在外延源极/漏极区80上先沉积能与半导体材料(例如硅、锗)反应的金属来形成硅化物(silicide)或锗化物(germanide)区,前述金属例如为镍、钴、钛、钽、铂、钨、其它贵重金属(noble metal)、其它难熔金属(refractory metal)、稀土金属(rare earth metal)或前述的合金,,然后执行热退火工艺,以形成硅化物区82。然后移除沉积的金属的未反应的部分,例如通过蚀刻工艺。尽管区域82称为硅化物区,区域82也可为锗化物区或硅锗化物(silicon germanide)区(例如含有硅和锗的区域)。
接着,如图18所示出,在阻挡层104上形成籽晶层(seed layer)108。可通过物理气相沉积(PVD)、原子层沉积(ALD)或化学气相沉积(CVD)来沉积籽晶层108,且籽晶层108可由钨、铜或铜合金形成,尽管其它合适的方法和材料也可替代使用。
一旦已经形成籽晶层108,如图19所示出,可形成导电材料110至籽晶层108上,导电材料110填充且过度填充接触开口91/93。导电材料110可包含钨,尽管其它合适的材料也可替代使用,例如铝、铜、氮化鵭(tungsten nitride)、钌(ruthenium)、银、金、铑(rhodium)、钼、镍、钴、镉(cadmium)、锌、前述的合金、前述的组合和类似材料。也可使用任何合适的沉积方法和回焊(reflow)形成导电材料110,沉积方法例如为物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)、电镀(plating)(例如电解电镀(electroplating))。
参阅图20,一旦已填充接触开口91/93,可通过平坦化工艺,例如化学机械研磨(CMP),移除接触开口91/93之外多余的阻挡层104、籽晶层108和导电材料110,尽管也可使用任何合适的移除工艺。因此,在接触开口91/93中形成接触件(插塞)102。
在此公开的实施例有可能有各种变化和修改。举例而言,可结合前文所讨论的表面处理工艺的各种实施例,以进一步改善栅极介电层94中的氟浓度。作为范例,参考图10,可执行前文所讨论的使用含氟气体(例如WF6)的浸泡工艺,接着参考图12,可执行前文所讨论的膜沉积工艺,然后可执行如图13所讨论的热退火工艺,以进一步驱使氟进入栅极介电层94。其它变化是有可能的。举例而言,可执行图10至图11所示出的工艺,然后可接着执行图12至图13所示出的工艺。因此,图10至图14可说明表面处理工艺的另一些实施例。本公开的实施例讨论使用氟作为栅极介电层94的掺杂物。在使用除了氟以外的元素作为掺杂物以改善栅极介电层94的时依性介电层崩溃(TDBB)表现的实施例中,可修改表面处理工艺,使其使用含有除了氟以外的掺杂物的化学物质或前驱物。这些和其它对本公开实施例的修改是有可能的,且完全包含在本公开实施例的范围内。
图21说明根据一些实施例的制造半导体装置的方法1000的流程图。应理解的是,图21所示的实施例方法仅为许多可能的实施例方法中的一个范例。本领域普通技术人员可理解许多变化、替代和修改。举例而言,可以增加、移除、取代,重排和重复图21中说明的各种步骤。
参阅图21,在步骤1010,在半导体鳍上形成虚设栅极结构。在步骤1020,在虚设栅极结构的相对两侧上形成介电层。在步骤1030,移除虚设栅极结构,以在介电层中形成凹陷。在步骤1040,在凹陷的侧壁和底部上依序形成栅极介电层和至少一导电层。在步骤1050,用含氟(F)的化学物质处理栅极介电层和前述至少一导电层
本公开实施例可达成许多优点。在本公开实施例中公开的表面处理工艺提供各种非破坏性和有效的方法来掺杂栅极介电层。因此,改善了半导体装置的时依性介电层崩溃(TDDB)表现。在公开的表面处理工艺中所使用的工艺步骤,例如浸泡工艺、膜沉积和蚀刻,皆为成熟的半导体工艺步骤,且容易使用。在表面处理工艺中所使用的原材料为低成本的材料。再者,所公开的表面处理工艺能轻易地与现有的取代栅极工艺整合。举例而言,使用在此公开的方法所形成的金属栅极膜堆叠不会有改变,因此确保与现有的工艺流程有良好的相容性。
在一些实施例中,半导体装置的形成方法包含在半导体鳍上形成虚设栅极结构,在虚设栅极结构的相对两侧形成介电层,以及移除虚设栅极结构,以在介电层中形成凹陷。此方法还包含在凹陷的侧壁和底部上依序形成栅极介电层和至少一导电层,以及用含氟(F)的化学物质处理栅极介电层和上述至少一层导电层。
在一些实施例中,其中形成栅极介电层和上述至少一导电层包含在凹陷的侧壁和底部上形成栅极介电层,在栅极介电层上形成盖层,盖层包含第一导电材料,以及在盖层上形成阻挡层,阻挡层包含不同于第一导电材料的第二导电材料。
在一些实施例中,其中栅极介电层包含高介电常数(high-K)介电材料。
在一些实施例中,其中盖层包含氮化钛(TiN),且阻挡层包含氮化钽(TaN)。
在一些实施例中,其中栅极介电层的处理驱使氟进入栅极介电层。
在一些实施例中,其中栅极介电层的处理包含使用六氟化钨(WF6)执行热工艺。
在一些实施例中,其中栅极介电层的处理包含使用三氟化氮(NF3)执行等离子体工艺。
在一些实施例中,其中栅极介电层的处理包含使用含氟前驱物在上述至少一导电层上形成膜。
在一些实施例中,其中含氟前驱物包含六氟化钨(WF6)或六氟化钼(MoF6)。
在一些实施例中,前述方法还包含在处理栅极介电层之后,执行热退火工艺。
在一些实施例中,其中栅极介电层的处理包含使栅极介电层和上述至少一导电层受到包含氟的气体或包含氟的等离子体影响,使用包含氟的前驱物在上述至少一导电层上沉积膜,以及在沉积膜之后,执行热退火工艺。
在一些实施例中,前述方法还包含在处理栅极介电层之后,使用导电材料填充凹陷。
在一些实施例中,鳍式场效晶体管(Fin Field-Effect Transistor,FinFET)的形成方法包含提供基底,其具有鳍突出于隔离结构的上表面上方,且隔离结构设置于鳍的相对两侧,在鳍上形成第一栅极结构,形成层间介电层围绕第一栅极结构,且层间介电层露出第一栅极结构的上表面,以及移除第一栅极结构,以在层间介电层中形成凹陷。此方法还包含在凹陷中形成层堆叠,其中形成层堆叠包含在凹陷中顺应地形成高介电常数介电层,在高介电常数介电层上顺应地形成导电盖层,和在导电盖层上顺应地形成导电的阻挡层。此方法还包含使用包含氟的化学物质对层堆叠执行表面处理工艺,其中表面处理工艺驱使氟进入高介电常数介电层,以及在表面处理工艺之后,执行热退火工艺。
在一些实施例中,其中执行表面处理工艺包含将层堆叠浸泡于包含氟的气体中,将层堆叠浸泡于包含氟的等离子体中,或使用含氟前驱物在导电的阻挡层上沉积膜。
在一些实施例中,其中执行表面处理工艺包含将层堆叠浸泡于含氟气体或含氟等离子体中,以及于前述浸泡之后,使用含氟前驱物在导电的阻挡层上沉积膜。
在一些实施例中,前述方法还包含在热退火工艺之后移除膜,以及用导电材料填充凹陷。
在一些实施例中,半导体装置的形成方法包含形成介电层,用至少一导电层覆盖介电层,在上述至少一导电层上供应含氟前驱物,以及驱使含氟前驱物的氟进入介电层。
在一些实例中,其中含氟前驱物为含氟气体或含氟等离子体。
在一些实施例中,其中供应含氟前驱物将膜沉积于上述至少一导电层上。
在一些实施例中,其中介电材料包含高介电常数介电材料,且其中驱使含氟前驱物的氟进入介电层包含至少一热驱入工艺(thermal drive-in process)。
以上概述了数个实施例的部件,使得本领域普通技术人员可以更加理解本公开实施例的各方面。本领域普通技术人员应该理解,他们可以容易地使用本公开实施例作为基础,来设计或修改用于实施与在此所介绍实施例具有相同的目的和/或达到相同优点的其他工艺和结构。本领域普通技术人员也应该理解,这些等效的构造并不背离本公开的构思和范围,并且在不背离本公开的构思和范围的情况下,在此可以做出各种改变、取代或其他选择。因此,本公开的保护范围当视后附的权利要求书所界定为准。
Claims (1)
1.一种半导体装置的形成方法,包括:
在一半导体鳍上形成一虚设栅极结构;
在该虚设栅极结构的相对两侧形成一介电层;
移除该虚设栅极结构,以在该介电层中形成一凹陷;
在该凹陷的侧壁和一底部上依序形成一栅极介电层和至少一导电层;以及
用一含氟的化学物质处理该栅极介电层和该至少一导电层。
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CN112563127B (zh) * | 2019-09-26 | 2023-10-31 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
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US10276690B2 (en) | 2019-04-30 |
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US20190259861A1 (en) | 2019-08-22 |
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