US20230387328A1 - Semiconductor device and method - Google Patents
Semiconductor device and method Download PDFInfo
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- US20230387328A1 US20230387328A1 US18/446,918 US202318446918A US2023387328A1 US 20230387328 A1 US20230387328 A1 US 20230387328A1 US 202318446918 A US202318446918 A US 202318446918A US 2023387328 A1 US2023387328 A1 US 2023387328A1
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- nanostructures
- work function
- function tuning
- gate dielectric
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- 238000000034 method Methods 0.000 title description 181
- 239000004065 semiconductor Substances 0.000 title description 81
- 239000002086 nanomaterial Substances 0.000 claims abstract description 220
- 239000003292 glue Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000010410 layer Substances 0.000 claims description 587
- 239000000463 material Substances 0.000 claims description 84
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 239000011241 protective layer Substances 0.000 claims description 25
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 14
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052715 tantalum Inorganic materials 0.000 claims description 10
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 9
- 229910000951 Aluminide Inorganic materials 0.000 claims description 5
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- 230000008569 process Effects 0.000 description 123
- 238000005530 etching Methods 0.000 description 61
- 238000000231 atomic layer deposition Methods 0.000 description 59
- 125000006850 spacer group Chemical group 0.000 description 51
- 238000000151 deposition Methods 0.000 description 30
- 239000003989 dielectric material Substances 0.000 description 29
- 239000012535 impurity Substances 0.000 description 28
- 230000008021 deposition Effects 0.000 description 24
- 238000005229 chemical vapour deposition Methods 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 20
- 229910052710 silicon Inorganic materials 0.000 description 20
- 239000010703 silicon Substances 0.000 description 20
- 239000012774 insulation material Substances 0.000 description 19
- 229910052782 aluminium Inorganic materials 0.000 description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 17
- 239000002243 precursor Substances 0.000 description 17
- 229910052719 titanium Inorganic materials 0.000 description 17
- 239000010936 titanium Substances 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- -1 SixGe1-x Chemical compound 0.000 description 14
- 238000000206 photolithography Methods 0.000 description 12
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- 239000007943 implant Substances 0.000 description 10
- 238000002955 isolation Methods 0.000 description 10
- 238000000059 patterning Methods 0.000 description 10
- 238000009966 trimming Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000004380 ashing Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 6
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 5
- 229910017052 cobalt Inorganic materials 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical group [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910021627 Tin(IV) chloride Inorganic materials 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 239000002135 nanosheet Substances 0.000 description 3
- 239000002070 nanowire Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- HPGGPRDJHPYFRM-UHFFFAOYSA-J tin(iv) chloride Chemical compound Cl[Sn](Cl)(Cl)Cl HPGGPRDJHPYFRM-UHFFFAOYSA-J 0.000 description 3
- WIDQNNDDTXUPAN-UHFFFAOYSA-I tungsten(v) chloride Chemical compound Cl[W](Cl)(Cl)(Cl)Cl WIDQNNDDTXUPAN-UHFFFAOYSA-I 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000000908 ammonium hydroxide Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 229910015900 BF3 Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 229910015218 MoCl4 Inorganic materials 0.000 description 1
- 229910019804 NbCl5 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910020751 SixGe1-x Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- KYCKJHNVZCVOTJ-UHFFFAOYSA-N [GeH3-].[Si+4].[GeH3-].[GeH3-].[GeH3-] Chemical group [GeH3-].[Si+4].[GeH3-].[GeH3-].[GeH3-] KYCKJHNVZCVOTJ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- DDHRUTNUHBNAHW-UHFFFAOYSA-N cobalt germanium Chemical compound [Co].[Ge] DDHRUTNUHBNAHW-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000109 continuous material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- OYMJNIHGVDEDFX-UHFFFAOYSA-J molybdenum tetrachloride Chemical compound Cl[Mo](Cl)(Cl)Cl OYMJNIHGVDEDFX-UHFFFAOYSA-J 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- YHBDIEWMOMLKOO-UHFFFAOYSA-I pentachloroniobium Chemical compound Cl[Nb](Cl)(Cl)(Cl)Cl YHBDIEWMOMLKOO-UHFFFAOYSA-I 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- OEIMLTQPLAGXMX-UHFFFAOYSA-I tantalum(v) chloride Chemical compound Cl[Ta](Cl)(Cl)(Cl)Cl OEIMLTQPLAGXMX-UHFFFAOYSA-I 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Definitions
- Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- FIG. 1 illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments.
- nano-FET nanostructure field-effect transistor
- FIGS. 2 through 27 B are views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.
- FIG. 28 is a flow chart of an example method for forming replacement gates for nano-FETs, in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- replacement gate electrodes for p-type devices and n-type devices are formed.
- the work function tuning layers for the n-type devices are formed before the work function tuning layers for the p-type devices to allow more control of the threshold voltages of the resulting devices.
- the method of forming the work function tuning layers for the n-type devices before the work function tuning layers for the p-type devices includes the formation and patterning of sacrificial layers to prevent the work function tuning layers for the n-type devices from being formed between the nanostructures of the p-type devices. This helps to prevent the work function tuning layers from remaining on the p-type devices which could degrade the performance of the p-type devices.
- a protection layer is formed between the work function tuning layer and a glue layer to inhibit (e.g., substantially prevents or at least reduces) diffusion of the work function tuning layer. The threshold voltages of the resulting devices may thus be more accurately tuned.
- Embodiments are described in a particular context, a die including nano-FETs. Various embodiments may be applied, however, to dies including other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in lieu of or in combination with the nano-FETs.
- FinFETs fin field effect transistors
- planar transistors or the like
- FIG. 1 illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like), in accordance with some embodiments.
- FIG. 1 is a three-dimensional view, where some features of the nano-FETs are omitted for illustration clarity.
- the nano-FETs may be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), or the like.
- the nano-FETs include nanostructures 66 (e.g., nanosheets, nanowires, or the like) over fins 62 on a substrate 50 (e.g., a semiconductor substrate), with the nanostructures 66 acting as channel regions for the nano-FETs.
- the nanostructures 66 may include p-type nanostructures, n-type nanostructures, or a combination thereof.
- Isolation regions 70 such as shallow trench isolation (STI) regions, are disposed between adjacent fins 62 , which may protrude above and from between adjacent isolation regions 70 .
- STI shallow trench isolation
- the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fins 62 are illustrated as being single, continuous materials with the substrate 50 , the bottom portion of the fins 62 and/or the substrate 50 may include a single material or a plurality of materials. In this context, the fins 62 refer to the portion extending above and from between the adjacent isolation regions 70 .
- Gate dielectrics 122 are over top surfaces of the fins 62 and along top surfaces, sidewalls, and bottom surfaces of the nanostructures 66 .
- Gate electrodes 124 are over the gate dielectrics 122 .
- Epitaxial source/drain regions 98 are disposed on the fins 62 at opposing sides of the gate dielectrics 122 and the gate electrodes 124 .
- the epitaxial source/drain regions 98 may be shared between various fins 62 .
- adjacent epitaxial source/drain regions 98 may be electrically connected, such as through coalescing the epitaxial source/drain regions 98 by epitaxial growth, or through coupling the epitaxial source/drain regions 98 with a same source/drain contact.
- FIG. 1 further illustrates reference cross-sections that are used in later figures.
- Cross-section A-A′ is along a longitudinal axis of a gate electrode 124 and in a direction, for example, perpendicular to a direction of current flow between the epitaxial source/drain regions 98 of a nano-FET.
- Cross-section B-B′ is along a longitudinal axis of a fin 62 and in a direction of, for example, a current flow between the epitaxial source/drain regions 98 of the nano-FET.
- Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions 98 of the nano-FETs. Subsequent figures refer to these reference cross-sections for clarity.
- FinFETs may include fins on a substrate, with the fins acting as channel regions for the FinFETs.
- planar FETs may include a substrate, with portions of the substrate acting as channel regions for the planar FETs.
- FIGS. 2 through 27 B are views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.
- FIGS. 2 , 3 , 4 , 5 , and 6 are three-dimensional views showing a similar three-dimensional view as FIG. 1 .
- FIGS. 7 A, 8 A, 9 A, 10 A, 11 A, 12 A, 13 A, 14 A, 14 B, 15 A, 15 B, 16 A, 16 B, 17 A, 17 B, 18 A, 18 B, 19 A, 19 B, 20 A, 20 B , 21 A, 21 B, 22 A, 22 B, 23 A, 23 B, 24 A, 24 B, 25 A, 26 A, and 27 A illustrate reference cross-section A-A′ illustrated in FIG. 1 , except two fins are shown.
- FIGS. 9 C and 9 D illustrate reference cross-section C-C′ illustrated in FIG. 1 , except two fins are shown.
- a substrate 50 is provided for forming nano-FETs.
- the substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or a n-type impurity) or undoped.
- the substrate 50 may be a wafer, such as a silicon wafer.
- SOI substrate is a layer of a semiconductor material formed on an insulator layer.
- the insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like.
- the insulator layer is provided on a substrate, typically a silicon or glass substrate.
- the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; combinations thereof; or the like.
- the substrate 50 has an n-type region 50 N and a p-type region 50 P.
- the n-type region 50 N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs
- the p-type region 50 P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs.
- the n-type region 50 N may be physically separated from the p-type region 50 P (not separately illustrated), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50 N and the p-type region 50 P.
- any number of n-type regions 50 N and p-type regions 50 P may be provided.
- the substrate 50 may be lightly doped with a p-type or an n-type impurity.
- An anti-punch-through (APT) implantation may be performed on an upper portion of the substrate 50 to form an APT region.
- impurities may be implanted in the substrate 50 .
- the impurities may have a conductivity type opposite from a conductivity type of source/drain regions that will be subsequently formed in each of the n-type region 50 N and the p-type region 50 P.
- the APT region may extend under the source/drain regions in the nano-FETs.
- the APT region may be used to reduce the leakage from the source/drain regions to the substrate 50 .
- the doping concentration in the APT region may be in the range of 10 18 cm ⁇ 3 to 10 19 cm ⁇ 3 .
- a multi-layer stack 52 is formed over the substrate 50 .
- the multi-layer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56 .
- the first semiconductor layers 54 are formed of a first semiconductor material
- the second semiconductor layers 56 are formed of a second semiconductor material.
- the semiconductor materials may each be selected from the candidate semiconductor materials of the substrate 50 .
- the multi-layer stack 52 includes three layers of each of the first semiconductor layers 54 and the second semiconductor layers 56 . It should be appreciated that the multi-layer stack 52 may include any number of the first semiconductor layers 54 and the second semiconductor layers 56 .
- the first semiconductor layers 54 will be removed and the second semiconductor layers 56 will patterned to form channel regions for the nano-FETs in both the n-type region 50 N and the p-type region 50 P.
- the first semiconductor layers 54 are sacrificial layers (or dummy layers), which will be removed in subsequent processing to expose the top surfaces and the bottom surfaces of the second semiconductor layers 56 .
- the first semiconductor material of the first semiconductor layers 54 is a material that has a high etching selectivity from the etching of the second semiconductor layers 56 , such as silicon germanium.
- the second semiconductor material of the second semiconductor layers 56 is a material suitable for both n-type and p-type devices, such as silicon.
- the first semiconductor layers 54 will be patterned to form channel regions for nano-FETs in one region (e.g., the p-type region 50 P), and the second semiconductor layers 56 will be patterned to form channel regions for nano-FETs in another region (e.g., the n-type region 50 N).
- the first semiconductor material of the first semiconductor layers 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si x Ge 1-x , where x can be in the range of 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like.
- the second semiconductor material of the second semiconductor layers 56 may be a material suitable for n-type devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like.
- the first semiconductor material and the second semiconductor material may have a high etching selectivity from the etching of one another, so that the first semiconductor layers 54 may be removed without removing the second semiconductor layers 56 in the n-type region 50 N, and the second semiconductor layers 56 may be removed without removing the first semiconductor layers 54 in the p-type region 50 P.
- Each of the layers of the multi-layer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like.
- VPE vapor phase epitaxy
- MBE molecular beam epitaxy
- CVD chemical vapor deposition
- ALD atomic layer deposition
- Each of the layers may have a small thickness, such as a thickness in a range from 5 nm to 30 nm.
- some layers e.g., the second semiconductor layers 56
- the first semiconductor layers 54 are sacrificial layers (or dummy layers) and the second semiconductor layers 56 are patterned to form channel regions for the nano-FETs in both the n-type region 50 N and the p-type region 50 P
- the first semiconductor layers 54 can have a first thickness T 1 and the second semiconductor layers 56 can have a second thickness T 2 , with the second thickness T 2 being from 30% to 60% less than the first thickness T 1 . Forming the second semiconductor layers 56 to a smaller thickness allows the channel regions to be formed at a greater density.
- trenches are patterned in the substrate 50 and the multi-layer stack 52 to form fins 62 , first nanostructures 64 , and second nanostructures 66 .
- the fins 62 are semiconductor strips patterned in the substrate 50 .
- the first nanostructures 64 and the second nanostructures 66 include the remaining portions of the first semiconductor layers 54 and the second semiconductor layers 56 , respectively.
- the trenches may be patterned by any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof.
- the etching may be anisotropic.
- the fins 62 and the nanostructures 64 , 66 may be patterned by any suitable method.
- the fins 62 and the nanostructures 64 , 66 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process.
- the sacrificial layer is then removed, and the remaining spacers may then be used as masks to pattern the fins 62 and the nanostructures 64 , 66 .
- the mask (or other layer) may remain on the nanostructures 64 , 66 .
- the fins 62 and the nanostructures 64 , 66 may each have widths in a range from 8 nm to 40 nm. In the illustrated embodiment, the fins 62 and the nanostructures 64 , 66 have substantially equal widths in the n-type region 50 N and the p-type region 50 P. In another embodiment, the fins 62 and the nanostructures 64 , 66 in one region (e.g., the n-type region 50 N) are wider or narrower than the fins 62 and the nanostructures 64 , 66 in another region (e.g., the p-type region 50 P).
- STI regions 70 are formed over the substrate 50 and between adjacent fins 62 .
- the STI regions 70 are disposed around at least a portion of the fins 62 such that at least a portion of the nanostructures 64 , 66 protrude from between adjacent STI regions 70 .
- the top surfaces of the STI regions 70 are coplanar (within process variations) with the top surfaces of the fins 62 .
- the top surfaces of the STI regions 70 are above or below the top surfaces of the fins 62 .
- the STI regions 70 separate the features of adjacent devices.
- the STI regions 70 may be formed by any suitable method.
- an insulation material can be formed over the substrate 50 and the nanostructures 64 , 66 , and between adjacent fins 62 .
- the insulation material may be an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, which may be formed by a chemical vapor deposition (CVD) process, such as high density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof.
- CVD chemical vapor deposition
- HDP-CVD high density plasma CVD
- FCVD flowable CVD
- Other insulation materials formed by any acceptable process may be used.
- the insulation material is silicon oxide formed by FCVD.
- An anneal process may be performed once the insulation material is formed.
- the insulation material is formed such that excess insulation material covers the nanostructures 64 , 66 .
- the STI regions 70 are each illustrated as a single layer, some embodiments may utilize multiple layers.
- a liner (not separately illustrated) may first be formed along surfaces of the substrate 50 , the fins 62 , and the nanostructures 64 , 66 . Thereafter, a fill material, such as those previously described may be formed over the liner.
- a removal process is then applied to the insulation material to remove excess insulation material over the nanostructures 64 , 66 .
- a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized.
- CMP chemical mechanical polish
- the planarization process exposes the nanostructures 64 , 66 such that top surfaces of the nanostructures 64 , 66 and the insulation material are coplanar (within process variations) after the planarization process is complete.
- the planarization process may expose the mask or remove the mask such that top surfaces of the mask or the nanostructures 64 , 66 , respectively, and the insulation material are coplanar (within process variations) after the planarization process is complete.
- the insulation material is then recessed to form the STI regions 70 .
- the insulation material is recessed such that at least a portion of the nanostructures 64 , 66 protrude from between adjacent portions of the insulation material.
- the top surfaces of the STI regions 70 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof.
- the top surfaces of the STI regions 70 may be formed flat, convex, and/or concave by an appropriate etch.
- the insulation material may be recessed using any acceptable etching process, such as one that is selective to the material of the insulation material (e.g., selectively etches the insulation material of the STI regions 70 at a faster rate than the materials of the fins 62 and the nanostructures 64 , 66 ).
- an oxide removal may be performed using dilute hydrofluoric (dHF) acid.
- the fins 62 and the nanostructures 64 , 66 may be formed using a mask and an epitaxial growth process.
- a dielectric layer can be formed over a top surface of the substrate 50 , and trenches can be etched through the dielectric layer to expose the underlying substrate 50 .
- Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 62 and/or the nanostructures 64 , 66 .
- the epitaxial structures may include the alternating semiconductor materials previously described, such as the first semiconductor material and the second semiconductor material.
- the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together.
- appropriate wells may be formed in the substrate 50 , the fins 62 , and/or the nanostructures 64 , 66 .
- the wells may have a conductivity type opposite from a conductivity type of source/drain regions that will be subsequently formed in each of the n-type region 50 N and the p-type region 50 P.
- a p-type well is formed in the n-type region 50 N
- an n-type well is formed in the p-type region 50 P.
- a p-type well or an n-type well is formed in both the n-type region 50 N and the p-type region 50 P.
- different implant steps for the n-type region 50 N and the p-type region 50 P may be achieved using mask (not separately illustrated) such as a photoresist.
- a photoresist may be formed over the fins 62 , the nanostructures 64 , 66 , and the STI regions 70 in the n-type region 50 N.
- the photoresist is patterned to expose the p-type region 50 P.
- the photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques.
- an n-type impurity implant is performed in the p-type region 50 P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50 N.
- the n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in the range of 10 13 cm ⁇ 3 to 10 14 cm ⁇ 3 .
- the photoresist may be removed, such as by any acceptable ashing process.
- a mask such as a photoresist is formed over the fins 62 , the nanostructures 64 , 66 , and the STI regions 70 in the p-type region 50 P.
- the photoresist is patterned to expose the n-type region 50 N.
- the photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques.
- a p-type impurity implant may be performed in the n-type region 50 N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50 P.
- the p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in the range of 10 13 cm ⁇ 3 to 10 14 cm ⁇ 3 .
- the photoresist may be removed, such as by any acceptable ashing process.
- an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted.
- the grown materials may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.
- a dummy dielectric layer 72 is formed on the fins 62 and the nanostructures 64 , 66 .
- the dummy dielectric layer 72 may be formed of a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, which may be deposited or thermally grown according to acceptable techniques.
- a dummy gate layer 74 is formed over the dummy dielectric layer 72 , and a mask layer 76 is formed over the dummy gate layer 74 .
- the dummy gate layer 74 may be deposited over the dummy dielectric layer 72 and then planarized, such as by a CMP.
- the mask layer 76 may be deposited over the dummy gate layer 74 .
- the dummy gate layer 74 may be formed of a conductive or non-conductive material, such as amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), a metal, a metallic nitride, a metallic silicide, a metallic oxide, or the like, which may be deposited by physical vapor deposition (PVD), CVD, or the like.
- the dummy gate layer 74 may be formed of material(s) that have a high etching selectivity from the etching of insulation materials, e.g., the STI regions 70 and/or the dummy dielectric layer 72 .
- the mask layer 76 may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like.
- a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50 N and the p-type region 50 P.
- the dummy dielectric layer 72 covers the fins 62 , the nanostructures 64 , 66 , and the STI regions 70 , such that the dummy dielectric layer 72 extends over the STI regions 70 and between the dummy gate layer 74 and the STI regions 70 .
- the dummy dielectric layer 72 covers only the fins 62 and the nanostructures 64 , 66 .
- the mask layer 76 is patterned using acceptable photolithography and etching techniques to form masks 86 .
- the pattern of the masks 86 is then transferred to the dummy gate layer 74 by any acceptable etching technique to form dummy gates 84 .
- the pattern of the masks 86 may optionally be further transferred to the dummy dielectric layer 72 by any acceptable etching technique to form dummy dielectrics 82 .
- the dummy gates 84 cover portions of the nanostructures 64 , 66 that will be exposed in subsequent processing to form channel regions. Specifically, the dummy gates 84 extend along the portions of the nanostructures 66 that will be patterned to form channel regions 68 .
- the pattern of the masks 86 may be used to physically separate adjacent dummy gates 84 .
- the dummy gates 84 may also have lengthwise directions substantially perpendicular (within process variations) to the lengthwise directions of the fins 62 .
- the masks 86 can optionally be removed after patterning, such as by any acceptable etching technique.
- FIGS. 7 A through 22 B illustrate various additional steps in the manufacturing of embodiment devices.
- FIGS. 7 A through 13 B and FIGS. 21 A through 22 B illustrate features in either of the n-type region 50 N and the p-type region 50 P.
- the structures illustrated may be applicable to both the n-type region 50 N and the p-type region 50 P. Differences (if any) in the structures of the n-type region 50 N and the p-type region 50 P are described in the text accompanying each figure.
- FIGS. 14 A, 15 A, 16 A, 17 A, 18 A, 19 A, and 20 A illustrate features in the n-type region 50 N.
- FIGS. 14 B, 15 B, 16 B, 17 B, 18 B, 19 B, and 20 B illustrate features in the p-type region 50 P.
- gate spacers 90 are formed over the nanostructures 64 , 66 , on exposed sidewalls of the masks 86 (if present), the dummy gates 84 , and the dummy dielectrics 82 .
- the gate spacers 90 may be formed by conformally depositing one or more dielectric material(s) and subsequently etching the dielectric material(s).
- Acceptable dielectric materials include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or the like; multilayers thereof; or the like.
- the dielectric materials may be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like.
- the gate spacers 90 each include multiple layers, e.g., a first spacer layer 90 A and a second spacer layer 90 B.
- the first spacer layers 90 A and the second spacer layers 90 B are formed of silicon oxycarbonitride (e.g., SiO x N y C 1-x-y , where x and y are in the range of 0 to 1).
- the first spacer layers 90 A can be formed of a similar or a different composition of silicon oxycarbonitride than the second spacer layers 90 B.
- An acceptable etch process such as a dry etch, a wet etch, the like, or a combination thereof, may be performed to pattern the dielectric material(s). The etching may be anisotropic.
- the dielectric material(s), when etched, have portions left on the sidewalls of the dummy gates 84 (thus forming the gate spacers 90 ).
- the gate spacers 90 can have straight sidewalls (as illustrated) or can have curved sidewalls (not illustrated).
- the dielectric material(s), when etched may have portions left on the sidewalls of the fins 62 and/or the nanostructures 64 , 66 (thus forming fin spacers).
- lightly doped source/drain regions may be formed using lightly doped source/drain (LDD) regions (not separately illustrated).
- a mask such as a photoresist may be formed over the n-type region 50 N, while exposing the p-type region 50 P, and appropriate type (e.g., p-type) impurities may be implanted into the fins 62 and/or the nanostructures 64 , 66 exposed in the p-type region 50 P. The mask may then be removed.
- a mask such as a photoresist may be formed over the p-type region 50 P while exposing the n-type region 50 N, and appropriate type impurities (e.g., n-type) may be implanted into the fins 62 and/or the nanostructures 64 , 66 exposed in the n-type region 50 N.
- the mask may then be removed.
- the n-type impurities may be any of the n-type impurities previously described, and the p-type impurities may be any of the p-type impurities previously described.
- the LDD regions may have a concentration of impurities in the range of 10 15 cm ⁇ 3 to 10 19 cm ⁇ 3 .
- An anneal may be used to repair implant damage and to activate the implanted impurities.
- spacers and LDD regions generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized, additional spacers may be formed and removed, and/or the like. Furthermore, the n-type devices and the p-type devices may be formed using different structures and steps.
- source/drain recesses 94 are formed in the nanostructures 64 , 66 .
- the source/drain recesses 94 extend through the nanostructures 64 , 66 and into the fins 62 .
- the source/drain recesses 94 may also extend into the substrate 50 .
- the source/drain recesses 94 may extend to a top surface of the substrate 50 without etching the substrate 50 ; the fins 62 may be etched such that bottom surfaces of the source/drain recesses 94 are disposed below the top surfaces of the STI regions 70 ; or the like.
- the source/drain recesses 94 may be formed by etching the nanostructures 64 , 66 using an anisotropic etching process, such as a RIE, a NBE, or the like.
- the gate spacers 90 and the dummy gates 84 collectively mask portions of the fins 62 and/or the nanostructures 64 , 66 during the etching processes used to form the source/drain recesses 94 .
- a single etch process may be used to etch each of the nanostructures 64 , 66 , or multiple etch processes may be used to etch the nanostructures 64 , 66 .
- Timed etch processes may be used to stop the etching of the source/drain recesses 94 after the source/drain recesses 94 reach a desired depth.
- inner spacers 96 are formed on the sidewalls of the remaining portions of the first nanostructures 64 , e.g., those sidewalls exposed by the source/drain recesses 94 .
- source/drain regions will be subsequently formed in the source/drain recesses 94
- the first nanostructures 64 will be subsequently replaced with corresponding gate structures.
- the inner spacers 96 act as isolation features between the subsequently formed source/drain regions and the subsequently formed gate structures. Further, the inner spacers 96 may be used to substantially prevent damage to the subsequently formed source/drain regions by subsequent etching processes, such as etching processes used to subsequently remove the first nanostructures 64 .
- the source/drain recesses 94 can be laterally expanded. Specifically, portions of the sidewalls of the first nanostructures 64 exposed by the source/drain recesses 94 may be recessed. Although sidewalls of the first nanostructures 64 are illustrated as being straight, the sidewalls may be concave or convex. The sidewalls may be recessed by any acceptable etching process, such as one that is selective to the material of the first nanostructures 64 (e.g., selectively etches the material of the first nanostructures 64 at a faster rate than the material of the second nanostructures 66 ). The etching may be isotropic.
- the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like.
- the etching process may be a dry etch using a fluorine-based gas such as hydrogen fluoride (HF) gas.
- HF hydrogen fluoride
- the same etching process may be continually performed to both form the source/drain recesses 94 and recess the sidewalls of the first nanostructures 64 .
- the inner spacers 96 can then be formed by conformally forming an insulating material and subsequently etching the insulating material.
- the insulating material may be silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than 3.5, may be utilized.
- the insulating material may be deposited by a conformal deposition process, such as ALD, CVD, or the like.
- the etching of the insulating material may be anisotropic.
- the etching process may be a dry etch such as a RIE, a NBE, or the like.
- outer sidewalls of the inner spacers 96 are illustrated as being flush with respect to the sidewalls of the gate spacers 90 , the outer sidewalls of the inner spacers 96 may extend beyond or be recessed from the sidewalls of the gate spacers 90 . In other words, the inner spacers 96 may partially fill, completely fill, or overfill the sidewall recesses. Moreover, although the sidewalls of the inner spacers 96 are illustrated as being straight, the sidewalls of the inner spacers 96 may be concave or convex.
- epitaxial source/drain regions 98 are formed in the source/drain recesses 94 .
- the epitaxial source/drain regions 98 are formed in the source/drain recesses 94 such that each dummy gate 84 (and corresponding channel regions 68 ) is disposed between respective adjacent pairs of the epitaxial source/drain regions 98 .
- the gate spacers 90 and the inner spacers 96 are used to separate the epitaxial source/drain regions 98 from, respectively, the dummy gates 84 and the first nanostructures 64 by an appropriate lateral distance so that the epitaxial source/drain regions 98 do not short out with subsequently formed gates of the resulting nano-FETs.
- a material of the epitaxial source/drain regions 98 may be selected to exert stress in the respective channel regions 68 , thereby improving performance.
- the epitaxial source/drain regions 98 in the n-type region 50 N may be formed by masking the p-type region 50 P. Then, the epitaxial source/drain regions 98 in the n-type region 50 N are epitaxially grown in the source/drain recesses 94 in the n-type region 50 N.
- the epitaxial source/drain regions 98 may include any acceptable material appropriate for n-type devices.
- the epitaxial source/drain regions 98 in the n-type region 50 N may include materials exerting a tensile strain on the channel regions 68 , such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like.
- the epitaxial source/drain regions 98 in the n-type region 50 N may have surfaces raised from respective surfaces of the fins 62 and the nanostructures 64 , 66 , and may have facets.
- the epitaxial source/drain regions 98 in the p-type region 50 P may be formed by masking the n-type region 50 N. Then, the epitaxial source/drain regions 98 in the p-type region 50 P are epitaxially grown in the source/drain recesses 94 in the p-type region 50 P.
- the epitaxial source/drain regions 98 may include any acceptable material appropriate for p-type devices.
- the epitaxial source/drain regions 98 in the p-type region 50 P may include materials exerting a compressive strain on the channel regions 68 , such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like.
- the epitaxial source/drain regions 98 in the p-type region 50 P may have surfaces raised from respective surfaces of the fins 62 and the nanostructures 64 , 66 , and may have facets.
- the epitaxial source/drain regions 98 , the nanostructures 64 , 66 , and/or the fins 62 may be implanted with impurities to form source/drain regions, similar to the process previously described for forming LDD regions, followed by an anneal.
- the source/drain regions may have an impurity concentration in the range of 10 19 cm ⁇ 3 to 10 21 cm ⁇ 3 .
- the n-type and/or p-type impurities for source/drain regions may be any of the impurities previously described.
- the epitaxial source/drain regions 98 may be in situ doped during growth.
- upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins 62 and the nanostructures 64 , 66 .
- these facets cause adjacent epitaxial source/drain regions 98 to merge as illustrated by FIG. 9 C .
- adjacent epitaxial source/drain regions 98 remain separated after the epitaxy process is completed as illustrated by FIG. 9 D .
- the spacer etch used to form the gate spacers 90 is adjusted to also form fin spacers 92 on sidewalls of the fins 62 and/or the nanostructures 64 , 66 .
- the fin spacers 92 are formed to cover a portion of the sidewalls of the fins 62 and/or the nanostructures 64 , 66 that extend above the STI regions 70 , thereby blocking the epitaxial growth.
- the spacer etch used to form the gate spacers 90 is adjusted to not form fin spacers, so as to allow the epitaxial source/drain regions 98 to extend to the surface of the STI regions 70 .
- the epitaxial source/drain regions 98 may include one or more semiconductor material layers.
- the epitaxial source/drain regions 98 may each include a liner layer 98 A, a main layer 98 B, and a finishing layer 98 C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source/drain regions 98 .
- Each of the liner layer 98 A, the main layer 98 B, and the finishing layer 98 C may be formed of different semiconductor materials and may be doped to different impurity concentrations.
- the liner layer 98 A may have a lesser concentration of impurities than the main layer 98 B, and the finishing layer 98 C may have a greater concentration of impurities than the liner layer 98 A and a lesser concentration of impurities than the main layer 98 B.
- the liner layers 98 A may be grown in the source/drain recesses 94
- the main layers 98 B may be grown on the liner layers 98 A
- the finishing layers 98 C may be grown on the main layers 98 B.
- a first inter-layer dielectric (ILD) 104 is deposited over the epitaxial source/drain regions 98 , the gate spacers 90 , the masks 86 (if present) or the dummy gates 84 .
- the first ILD 104 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Acceptable dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used.
- a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source/drain regions 98 , the gate spacers 90 , and the masks 86 (if present) or the dummy gates 84 .
- the CESL 102 may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etching selectivity from the etching of the first ILD 104 .
- the CESL 102 may be formed by any suitable method, such as CVD, ALD, or the like.
- a removal process is performed to level the top surfaces of the first ILD 104 with the top surfaces of the masks 86 (if present) or the dummy gates 84 .
- a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized.
- CMP chemical mechanical polish
- the planarization process may also remove the masks 86 on the dummy gates 84 , and portions of the gate spacers 90 along sidewalls of the masks 86 .
- the top surfaces of the gate spacers 90 , the first ILD 104 , the CESL 102 , and the masks 86 (if present) or the dummy gates 84 are coplanar (within process variations). Accordingly, the top surfaces of the masks 86 (if present) or the dummy gates 84 are exposed through the first ILD 104 . In the illustrated embodiment, the masks 86 remain, and the planarization process levels the top surfaces of the first ILD 104 with the top surfaces of the masks 86 .
- the masks 86 (if present) and the dummy gates 84 are removed in an etching process, so that recesses 110 are formed. Portions of the dummy dielectrics 82 in the recesses 110 are also removed.
- the dummy gates 84 are removed by an anisotropic dry etch process.
- the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates 84 at a faster rate than the first ILD 104 or the gate spacers 90 .
- the dummy dielectrics 82 may be used as etch stop layers when the dummy gates 84 are etched.
- Each recess 110 exposes and/or overlies portions of the channel regions 68 . Portions of the second nanostructures 66 which act as the channel regions 68 are disposed between adjacent pairs of the epitaxial source/drain regions 98 .
- the remaining portions of the first nanostructures 64 are then removed to expand the recesses 110 .
- the remaining portions of the first nanostructures 64 can be removed by any acceptable etching process that selectively etches the material of the first nanostructures 64 at a faster rate than the material of the second nanostructures 66 .
- the etching may be isotropic.
- the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), NH 4 OH, H 2 O 2 , H 2 O, HF, C 3 H 8 O 2 , C 2 H 4 C 3 , the like, or combinations thereof.
- TMAH tetramethylammonium hydroxide
- a trim process (not separately illustrated) is performed to decrease the thicknesses of the exposed portions of the second nanostructures 66 . As illustrated more clearly in FIGS. 14 A through 20 B (subsequently described in greater detail), the remaining portions of the second nanostructures 66 can have rounded corners.
- a gate dielectric layer 112 is formed in the recesses 110 .
- a gate electrode layer 114 is formed on the gate dielectric layer 112 .
- the gate dielectric layer 112 and the gate electrode layer 114 are layers for replacement gates, and each wrap around all (e.g., four) sides of the second nanostructures 66 .
- the gate dielectric layer 112 is disposed on the sidewalls and/or the top surfaces of the fins 62 ; on the top surfaces, the sidewalls, and the bottom surfaces of the second nanostructures 66 ; and on the sidewalls of the gate spacers 90 .
- the gate dielectric layer 112 may also be formed on the top surfaces of the first ILD 104 and the gate spacers 90 .
- the gate dielectric layer 112 may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, combinations thereof, multi-layers thereof, or the like.
- the gate dielectric layer 112 may include a dielectric material having a k-value greater than 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although a single layered gate dielectric layer 112 is illustrated in FIGS. 13 A and 13 B , as will be subsequently described in greater detail, the gate dielectric layer 112 may include an interfacial layer and a main layer.
- the gate electrode layer 114 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, multi-layers thereof, or the like. Although a single-layered gate electrode layer 114 is illustrated in FIGS. 13 A and 13 B , as will be subsequently described in greater detail, the gate electrode layer 114 may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and a fill material.
- FIGS. 14 A through 24 B illustrate a process in which layers for replacement gates are formed in the recesses 110 .
- FIG. 28 is a flow chart of an example method 200 for forming the replacement gate layers, in accordance with some embodiments.
- FIGS. 14 A through 24 B are described in conjunction with FIG. 28 .
- the gate dielectric layer 112 is deposited in the recesses 110 in both the first region (e.g., the n-type region 50 N) and the second region (e.g., the p-type region 50 P).
- the gate dielectric layer 112 may also be deposited on the top surfaces of the first ILD 104 and the gate spacers 90 (see FIG. 13 B ).
- the gate dielectric layer 112 is multilayered, including an interfacial layer 112 A (or more generally, a first gate dielectric layer) and an overlying high-k dielectric layer 112 B (or more generally, a second gate dielectric layer).
- the interfacial layer 112 A may be formed of silicon oxide or the like and the high-k dielectric layer 112 B may be formed of hafnium oxide, lanthanum oxide, or the like.
- the formation methods of the gate dielectric layer 112 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.
- MBD molecular-beam deposition
- ALD ALD
- PECVD PECVD
- the gate dielectric layer 112 wraps around all (e.g., four) sides of the second nanostructures 66 .
- the second nanostructures 66 have a width W 1 in a range from 1 nm to 50 nm, such as a range from 15 nm to 25 nm.
- adjacent second nanostructures 66 are spaced apart by a spacing S 1 in a range from 0.1 nm to 40 nm, such as a range from 3 nm to 8 nm. If the spacing S 1 is higher than 40 nm, a seam or void may be formed between adjacent second nanostructures 66 after the subsequent formation of the gate structures. If the spacing S 1 is lower than 0.1 nm, the adjacent second nanostructures 66 could easily short to each other.
- a first sacrificial layer 116 A is deposited on the gate dielectric layer 112 in the first region (e.g., the n-type region 50 N) and the second region (e.g., the p-type region 50 P).
- the first sacrificial layer 116 A will be patterned to remove portions of the first sacrificial layer 116 A in the first region (e.g., the n-type region 50 N) while leaving portions of the first sacrificial layer 116 A in the second region (e.g., the p-type region 50 P).
- the first sacrificial layer 116 A is used to ease the removal of work function layers from the second region (e.g., the p-type region 50 P) by not allowing those work function layers to get between the second nanostructures 66 .
- the first sacrificial layer 116 A includes any acceptable material that can be formed on and removed from between second nanostructures 66 , and may be deposited using any acceptable deposition process.
- the first sacrificial layer 116 A is formed of TiN, WCN, WCl 5 , TaCl 5 , SnCl 4 , combinations thereof, or the like, which may be deposited by ALD, CVD, PVD, or the like.
- first sacrificial layer 116 A is shown as being single layered, the first sacrificial layer 116 A can be multilayered.
- the first sacrificial layer 116 A may fill portions of the second recesses 110 extending between vertically adjacent ones of the nanostructures 66 and extending between the nanostructures 66 and the fins 62 .
- portions of the first sacrificial layer 116 A are removed from the first region (e.g., the n-type region 50 N) and the second region (e.g., the p-type region 50 P). Removing the portions of the first sacrificial layer 116 A allows for the subsequent formation of a second sacrificial layer 116 B to protect the gate dielectric layer 112 while potentially providing etch selectivity to the first sacrificial layer 116 A.
- the removal may be by acceptable photolithography and etching techniques.
- the etching may include any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof.
- the etching may be anisotropic.
- the removal of portions of first sacrificial layer 116 A removes outer portions of the first sacrificial layer 116 A to expose the gate dielectric layer 112 but leaves the first sacrificial layer 116 A between vertically adjacent ones of the nanostructures 66 and extending between the nanostructures 66 and the fins 62 in both the first and second regions 50 N and 50 P.
- This removal of outer portions of the first sacrificial layer 116 A while leaving inner portions may be referred to as a trimming process.
- the gate dielectric layer 112 After the removal of portions of the first sacrificial layer 116 A, the gate dielectric layer 112 remains over and covers isolations regions 70 (see, e.g., FIG. 13 A ). These portions of gate dielectric layer 112 can help to protect the isolation regions 70 from damage from subsequent deposition and removal processes.
- a single etch is performed to remove the portions of the first sacrificial layer 116 A.
- the single etch may be selective to the materials of the first sacrificial layer 116 A (e.g., selectively etches the material of the first sacrificial layer 116 A at a faster rate than the material(s) of the gate dielectric layer 112 ).
- multiple etch steps/processes are performed to remove the portions of the first sacrificial layer 116 A.
- a second sacrificial layer 116 A is deposited on the gate dielectric layer 112 and the remaining first sacrificial layer 116 A in the first region (e.g., the n-type region 50 N) and the second region (e.g., the p-type region 50 P).
- the second sacrificial layer 116 B will be patterned to remove it and the first sacrificial layer 116 A from in the first region (e.g., the n-type region 50 N) while leaving the second sacrificial layer 116 B and the first sacrificial layer 116 A in the second region (e.g., the p-type region 50 P).
- the second sacrificial layer 116 B is used to protect the gate dielectric layer 112 from first mask layer 118 A formed in the first and second regions by not allowing the first mask layer 118 A to be formed directly on the gate dielectric layer 112 .
- the second sacrificial layer 116 B includes any acceptable material that can be formed on and removed from the gate dielectric layer 112 without damaging the gate dielectric layer 112 , and may be deposited using any acceptable deposition process.
- the second sacrificial layer 116 B is formed of TiN, WCN, WCl 5 , TaCl 5 , SnCl 4 , combinations thereof, or the like, which may be deposited by ALD, CVD, PVD, or the like.
- the second sacrificial layer 116 B is formed of a different material than the first sacrificial layer 116 A.
- the second sacrificial layer 116 B is shown as being single layered, the second sacrificial layer 116 B can be multilayered.
- the second sacrificial layer 116 B is formed of a same material as the first sacrificial layer 116 A and there is no visible interface between the layers 116 A and 116 B. In some embodiments, the second sacrificial layer 116 B is omitted and the first sacrificial layer 116 A is not patterned as illustrated in FIGS. 16 A and 16 B such that the first sacrificial layer 116 A protects the dielectric layer 112 from the first mask layer 118 A.
- the first mask layer 118 A is formed in the second recesses 110 over the second sacrificial layer 116 B in the first and second regions 50 N and 50 P.
- the first mask layer 118 A may be deposited by spin-on-coating or the like.
- the first mask layer 118 A may include a polymer material, such as poly(methyl)acrylate, poly(maleimide), novolacs, poly(ether)s, combinations thereof, or the like.
- the first mask layer 118 A may be a bottom anti-reflective coating (BARC) material.
- the first mask layer 118 A is patterned to remove the first mask layer 118 A from the recesses 110 in the first region 50 N.
- the first mask layer 118 A may be removed by plasma ashing, an etching process such as an isotropic or an anisotropic etching process, or the like.
- the first and second sacrificial layers 116 A and 116 B are removed from the first region 50 N using the first mask layer 118 A as a mask.
- the removal may be by acceptable photolithography and etching techniques.
- the etching may include any acceptable etch process, such as a RIE, NBE, a wet etch, the like, or a combination thereof.
- the etching may be anisotropic.
- a single etch is performed to remove the portions of the first and second sacrificial layers 116 A and 116 B.
- the single etch may be selective to the materials of the first and second sacrificial layers 116 A and 116 B (e.g., selectively etches the materials of the first and second sacrificial layers 116 A and 116 B at a faster rate than the material(s) of the gate dielectric layer 112 ).
- the first and second sacrificial layers 116 A and 116 B are formed of titanium nitride, it may be removed by an inductively coupled plasma etching process using Ar/CHF 3 , Ar/Cl 2 , Ar/BCl 3 , the like, or a combination thereof.
- multiple etch steps/processes are performed to remove the first and second sacrificial layers 116 A and 116 B.
- the first mask layer 118 A is patterned to remove the first mask layer 118 A from the recesses 110 in the second region 50 P.
- the first mask layer 118 A may be removed by plasma ashing, an etching process such as an isotropic or an anisotropic etching process, or the like.
- the second sacrificial layer 116 B is removed from the second region 50 P.
- the removal may be by acceptable photolithography and etching techniques.
- the etching may include any acceptable etch process, such as a RIE, NBE, the like, or a combination thereof.
- the etching may be anisotropic.
- a single etch is performed to remove the second sacrificial layers 116 B.
- the single etch may be selective to the materials of the second sacrificial layer 116 B (e.g., selectively etches the materials of the second sacrificial layer 116 B at a faster rate than the material(s) of the gate dielectric layer 112 and/or the first sacrificial layer 116 A).
- multiple etch steps/processes are performed to remove the second sacrificial layer 116 B.
- the removal the second sacrificial layer 116 B removes outer portions of the second sacrificial layer 116 B to expose portions of the gate dielectric layer 112 but leaves the first sacrificial layer 116 A between vertically adjacent ones of the nanostructures 66 and extending between the nanostructures 66 and the fins 62 in both the second region 50 P.
- This removal of outer portions of the second sacrificial layer 116 B while leaving inner portions may be referred to as a trimming process.
- a first work function tuning layer 114 A is deposited on the gate dielectric layer 112 in the first region (e.g., the n-type region 50 N) and on the gate dielectric layer 112 and the first sacrificial layer 116 A in the second region (e.g., the p-type region 50 P).
- the first work function tuning layer 114 A will be patterned to remove portions of the first work function tuning layer 114 A in the second region (e.g., the p-type region 50 P) while leaving portions of the first work function tuning layer 114 A in the first region (e.g., the n-type region 50 N).
- the first work function tuning layer 114 A may be referred to as an “n-type work function tuning layer” when it is removed from the second region (e.g., the p-type region 50 P).
- the first work function tuning layer 114 A includes any acceptable material to tune a work function of a device to a desired amount given the application of the device to be formed, and may be deposited using any acceptable deposition process.
- the first work function tuning layer 114 A when it is a n-type work function tuning layer, it may be formed of a n-type work function metal (NWFM) such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), TiAlC:N, titanium aluminum nitride (TiAlN), tantalum silicon aluminum (TaSiAl), WCl 5 , SnCl 4 , NbCl 5 , MoCl 4 , combinations thereof, or the like, which may be deposited by ALD, CVD, PVD, or the like.
- NWFM n-type work function metal
- TiAl titanium aluminum
- TiAlC titanium aluminum carbide
- TiAlC:N titanium aluminum nitride
- TaSiAl tantalum silicon aluminum
- WCl 5 , SnCl 4 , NbCl 5 , MoCl 4 combinations thereof, or the like, which may be deposited by ALD, CVD, PVD, or
- the first work function tuning layer 114 A is formed to a thickness that does not cause merging of the portions of the first work function tuning layer 114 A between the second nanostructures 66 in the first region (e.g., the n-type region 50 N). As described in more detail below, the ALD process used to form the first work function tuning layer 114 A allows for a thinner first work function tuning layer 114 A (that does not merge between second nanostructures 66 in the illustrated cross-section in the first region 50 N) while also having the desired effective work function value.
- the first work function tuning layer 114 A cannot merge between the second nanostructures 66 in the second region (e.g., the p-type region 50 P) in the illustrated cross-section due to the remaining portions of the first sacrificial layer 116 A in the second region.
- the first work function tuning layer 114 A is formed to a thickness in a range from 5 ⁇ to 120 ⁇ , such as in a range from 20 ⁇ to 80 ⁇ .
- the first work function tuning layer 114 A is formed of titanium aluminum carbide, which is deposited by an ALD process.
- the first work function tuning layer 114 A may be formed by placing the substrate 50 in a deposition chamber and cyclically dispensing multiple source precursors into the deposition chamber.
- a first pulse of an ALD cycle is performed by dispensing a titanium source precursor into the deposition chamber.
- Acceptable titanium source precursors include titanium chloride (TiCl 4 ) or the like.
- the first pulse can be performed at a temperature in the range of 100° C. to 600° C. and at a pressure in the range of 1 torr to 100 torr, e.g., by maintaining the deposition chamber at such a temperature and pressure.
- the first pulse can be performed for a duration in the range of 0.5 seconds to 20 seconds, e.g., by keeping the titanium source precursor in the deposition chamber for such a duration.
- the titanium source precursor is then purged from the deposition chamber, such as by an acceptable vacuuming process and/or by flowing an inert gas (sometimes called a carrier gas) into the deposition chamber.
- a second pulse of the ALD cycle is performed by dispensing an aluminum source precursor into the deposition chamber.
- Acceptable aluminum source precursors include triethylaluminium (TEA) (Al 2 (C 2 H 5 ) 6 ) and the like.
- the second pulse can be performed at a temperature in the range of 100° C. to 600° C.
- the second pulse can be performed for a duration in the range of 0.5 seconds to 20 seconds, e.g., by keeping the aluminum source precursor in the deposition chamber for such a duration.
- the aluminum source precursor is then purged from the deposition chamber, such as by an acceptable vacuuming process and/or by flowing an inert gas into the deposition chamber.
- Performing either of the ALD pulses at a temperature higher than 600° C. may negatively impact the uniformity of the deposition and have inconsistent concentration of materials in the deposited layer.
- Each ALD cycle results in the deposition of an atomic layer (sometimes called a monolayer) of titanium aluminum carbide.
- the ALD cycles are repeated until the first work function tuning layer 114 A has a desired thickness (previously described).
- the ALD cycles can be repeated from 1 to 10 times. Performing the ALD process with parameters in these ranges allows the first work function tuning layer 114 A to be formed to a desired thickness (previously described), quality, and composition. Performing the ALD process with parameters outside of these ranges may not allow the first work function tuning layer 114 A to be formed to the desired thickness, quality, or composition.
- the above-described ALD process for forming the first work function tuning layer 114 A has the same number of titanium pulses as aluminum pulses in each ALD cycle. In some embodiments, there are more aluminum pulses than titanium pulses per ALD cycle. For example, each ALD cycle could include one titanium pulse and two aluminum pulses. As another example, each ALD cycle could include two titanium pulse and three aluminum pulses. By ensuring that there are at least as many aluminum pulses as titanium pulses in each ALD cycle, the first work function layer has a higher aluminum concentration. In some embodiments, the atomic percentage (at %) of aluminum in the first work function tuning layer 114 A is in a range from 3% to 80%, such as in a range from 20% to 40%.
- the first work function tuning layer 114 A has a gradient metal concentration with a higher concentration of aluminum at an inner portion near the second nanostructures 66 and a lower concentration at an outer portion away from the second nanostructures 66 . In some embodiments, the disclosed method of forming the first work function tuning layer 114 A has improved the effective work function by 10% to 15%.
- the ALD process for forming the first work function tuning layer 114 A includes flowing a carrier gas from a port on the bottom of the deposition chamber (e.g., below or on the back side of the substrate 50 ) whereas the titanium and aluminum precursors described above are flowed into one or more ports on the top of the deposition chamber (e.g., above or on the front side of the substrate 50 ).
- the carrier gas flowed into the bottom of the deposition chamber is N 2 or the like and at a flow rate in a range from 2 sccm to 100 sccm.
- the carrier flow is a pulse performed at the end of each ALD cycle.
- the carrier flow is a pulse performed after each titanium or aluminum precursor pulse in each ALD cycle.
- a glue layer 114 B is formed on the first work function tuning layer 114 A in the first region (e.g., the n-type region 50 N) and the second region (e.g., the p-type region 50 P). As illustrated in FIG. 20 A , the glue layer 114 B merges between adjacent second nanostructures 66 in the first region 50 N in the illustrated cross-section. In some embodiments, the glue layer 114 B is formed to a thickness in a range from 10 nm to 50 nm.
- the glue layer 114 B includes any acceptable material to promote adhesion and prevent diffusion.
- the glue layer 114 B may be formed of a metal or metal nitride such as titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, silicon-doped tantalum aluminide, or the like, which may be deposited by ALD, CVD, PVD, or the like.
- a metal or metal nitride such as titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, silicon-doped tantalum aluminide, or the like, which may be deposited by ALD, CVD, PVD, or the like.
- the glue layer 114 B is formed by a similar ALD process with titanium precursors, such as TiCl 4 or the like, tantalum precursors, such as pentakis(dimethylamido)tantalum (PDMAT) (C 10 H 30 N 5 Ta), tantalum chloride (TaCl 5 ), or the like, and/or nitrogen precursors such as NH 3 , or the like.
- titanium precursors such as TiCl 4 or the like
- tantalum precursors such as pentakis(dimethylamido)tantalum (PDMAT) (C 10 H 30 N 5 Ta), tantalum chloride (TaCl 5 ), or the like
- nitrogen precursors such as NH 3 , or the like.
- the titanium or tantalum precursors may be flowed into the deposition chamber at flow rates in a range from 50 sccm to 100 sccm.
- the nitrogen precursors may be flowed into the deposition chamber at flow rates in a range from 50 scc
- the ALD process can be performed at a temperature in the range of 100° C. to 600° C. and at a pressure in a range from 0.0001 torr to 1 torr. Performing the ALD process at a temperature higher than 600° C. may negatively impact the uniformity of the deposition and have inconsistent concentration of materials in the deposited layer. Performing the ALD process at a temperature less than 100° C. may negatively impact throughput and/or productivity of the manufacturing process and may lead to a higher cost of manufacturing.
- a second mask layer 118 B is formed in the second recesses 110 over the glue layer 114 B in the first and second regions 50 N and 50 P.
- the second mask layer 118 B may be similar to the first mask layer 118 A described above and the description is not repeated herein.
- the second mask layer 118 B is patterned to remove the second mask layer 118 B from the recesses 110 in the second region 50 P.
- the second mask layer 118 B may be removed by plasma ashing, an etching process such as an isotropic or an anisotropic etching process, or the like.
- the first work function tuning layer 114 A, the glue layer 114 B, and remaining portions of the first sacrificial layer 116 A are removed from the second region 50 P using the second mask layer 118 B as a mask.
- the removal may be by acceptable photolithography and etching techniques.
- the etching may include any acceptable etch process, such as a RIE, NBE, the like, a wet etch using for example, ammonium hydroxide (NH 4 OH), dilute hydrofluoric (dHF) acid, the like, or a combination thereof.
- the etching may be isotropic.
- a single etch is performed to remove the first work function tuning layer 114 A, the glue layer 114 B, and remaining portions of the first sacrificial layer 116 A.
- the single etch may be selective to the materials of the first work function tuning layer 114 A, the glue layer 114 B, and remaining portions of the first sacrificial layer 116 A (e.g., selectively etches the materials of the first work function tuning layer 114 A, the glue layer 114 B, and remaining portions of the first sacrificial layer 116 A at a faster rate than the material(s) of the gate dielectric layer 112 ).
- multiple etch steps/processes are performed to remove the first work function tuning layer 114 A, the glue layer 114 B, and remaining portions of the first sacrificial layer 116 A.
- the remaining portions of the first sacrificial layer 116 A are easier to remove from between the second nanostructures 66 than the work function tuning layers, and thus, the disclosed method provides better control for tuning the threshold voltage of the devices.
- the second mask layer 118 B is patterned to remove the second mask layer 118 B from the recesses 110 in the first region 50 N.
- the second mask layer 118 B may be removed by plasma ashing, an etching process such as an isotropic or an anisotropic etching process, or the like.
- a second work function tuning layers 114 C and 114 D are deposited on the glue layer 114 B in the first region (e.g., the n-type region 50 N) and on the gate dielectric layer 112 in the second region (e.g., the p-type region 50 P).
- p-type devices will be formed having the second work function tuning layers 114 C and 114 D in the second region (e.g., the p-type region 50 P), and n-type devices will be formed having the first work function tuning layer 114 A, the glue layer 114 B, and the second work function tuning layers 114 C and 114 D in the first region (e.g., the n-type region 50 N).
- the second work function tuning layers 114 C and 114 D may be referred to as a “p-type work function tuning layers” when it is the only work function tuning layer in the second region (e.g., the p-type region 50 P).
- the second work function tuning layers 114 C and 114 D includes any acceptable material to tune a work function of a device to a desired amount given the application of the device to be formed, and may be deposited using any acceptable deposition process.
- the second work function tuning layers 114 C and 114 D are p-type work function tuning layers, it may be formed of a p-type work function metals (PWFM) such as titanium nitride (TiN), tantalum nitride (TaN), combinations thereof, or the like, which may be deposited by ALD, CVD, PVD, or the like.
- PWFM p-type work function metals
- the second work function tuning layers 114 C and 114 D may be formed by an ALD process using parameters as described above for the glue layer 114 B and the description is not repeated herein. Although the second work function tuning layers 114 C and 114 D are shown as being two layers, the second work function tuning layer can be single-layered or have more than two layers. In some embodiments, the second work function tuning layers 114 C and 114 D include a layer of titanium nitride (TiN) and a layer of tantalum nitride (TaN).
- the second work function tuning layers 114 C and 114 D are formed to a thickness that is sufficient to cause merging of the portions of the second work function tuning layer 114 C or 114 D between the second nanostructures 66 in the second region (e.g., the p-type region 50 P).
- the second work function tuning layers 114 C and 114 D are formed to a thickness in a range from 10 ⁇ to 200 ⁇ , such as in a range from 20 ⁇ to 25 ⁇ . Forming the second work function tuning layer 114 C to a thickness of less than 20 ⁇ may not result in merging of portions of the second work function tuning layers 114 C and 114 D. Forming the second work function tuning layer 114 C and 114 D to a thickness of greater than 25 ⁇ may negatively impact the threshold voltages of the resulting devices.
- the material of the first work function tuning layer 114 A is different from the material of the second work function tuning layers 114 C and 114 D.
- the first work function tuning layer 114 A can be formed of a n-type work function metal (NWFM) and the second work function tuning layers 114 C and 114 D can be formed of p-type work function metal (PWFM).
- NWFM is different from the PWFM.
- a fill layer 114 E is deposited on the second work function tuning layer 114 D.
- the gate electrode layer 114 includes the first work function tuning layer 114 A, the glue layer 114 B, the second work function tuning layers 114 C and 114 D, and the fill layer 114 E.
- the fill layer 114 E includes any acceptable material of a low resistance.
- the fill layer 114 E may be formed of a metal such as tungsten, aluminum, cobalt, ruthenium, combinations thereof or the like, which may be deposited by ALD, CVD, PVD, or the like.
- the fill layer 114 E fills the remaining portions of the recesses 110 .
- the fill layer 114 E does not extend between adjacent second nanostructures 66 in either the first region 50 N or the second region 50 P as the area between adjacent second nanostructures 66 in both regions has already been filled by other layers.
- the glue layer 114 B is used promote adhesion and prevent diffusion of the first work function tuning layer 114 A during processing, it may not significantly affect the electrical characteristics of the resulting devices, and may be left in the portions of the gate electrode layer 114 in the first region (e.g., the n-type region 50 N).
- the glue layer 114 B is disposed between and physically separates the portions of the first work function tuning layer 114 A and the second work function tuning layer 114 C in the first region (e.g., the n-type region 50 N).
- the second region (e.g., the p-type region 50 P) is free of the first work function tuning layer 114 A and the glue layer 114 B, such that the second work function tuning layer 114 C and the gate dielectric layer 112 in the second region (e.g., the p-type region 50 P) are not separated by a glue layer, and may be in physical contact.
- FIGS. 24 A and 24 B illustrate an embodiment that includes a protective layer 114 F between the first work function tuning layer 114 A and the glue layer 114 B.
- the protective layer 114 F is formed of a material that is resistant to oxidation and prevents diffusion of the first work function tuning layer 114 A, and thus, inhibits the modification of the first work function tuning layer 114 A by subsequent processing.
- the protective layer 114 F is formed of amorphous silicon, tantalum nitride, titanium nitride, the like, or a combination thereof which may be deposited by CVD, ALD, or the like. Although the protective layer 114 F is shown as being single layered, the protective layer 114 F can be multilayered. For example, the protective layer 114 F can include a layer of amorphous silicon and a layer of titanium nitride. In some embodiments, the protective layer 114 F is formed to a thickness in a range from 0.1 nm to 10 nm.
- a removal process is performed to remove the excess portions of the materials of the gate dielectric layer 112 and the gate electrode layer 114 , which excess portions are over the top surfaces of the first ILD 104 and the gate spacers 90 , thereby forming gate dielectrics 122 and gate electrodes 124 .
- a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized.
- CMP chemical mechanical polish
- the gate dielectric layer 112 when planarized, has portions left in the recesses 110 (thus forming the gate dielectrics 122 ).
- the gate electrode layer 114 when planarized, has portions left in the recesses 110 (thus forming the gate electrodes 124 ).
- the top surfaces of the gate spacers 90 ; the CESL 102 ; the first ILD 104 ; the gate dielectrics 122 (e.g., the interfacial layers 112 A and the high-k dielectric layers 112 B, see FIGS. 23 A- 24 B ); and the gate electrodes 124 e.g., the first work function tuning layer 114 A, the glue layer 114 B, the second work function tuning layers 114 C and 114 D, optionally the protective layer 114 F, and the fill layer 114 E, see FIGS. 23 A- 24 B ) are coplanar (within process variations).
- the gate dielectrics 122 and the gate electrodes 124 form replacement gates of the resulting nano-FETs.
- Each respective pair of a gate dielectric 122 and a gate electrode 124 may be collectively referred to as a “gate structure.”
- the gate structures each extend along top surfaces, sidewalls, and bottom surfaces of a channel region 68 of the second nanostructures 66 .
- a second ILD 134 is deposited over the gate spacers 90 , the CESL 102 , the first ILD 104 , the gate dielectrics 122 , and the gate electrodes 124 .
- the second ILD 134 is a flowable film formed by a flowable CVD method.
- the second ILD 134 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, which may be deposited by any suitable method, such as CVD, PECVD, or the like.
- an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacers 90 , the CESL 102 , the first ILD 104 , the gate dielectrics 122 , and the gate electrodes 124 .
- the ESL 132 may include a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etching selectivity from the etching of the second ILD 134 .
- gate contacts 142 and source/drain contacts 144 are formed to contact, respectively, the gate electrodes 124 and the epitaxial source/drain regions 98 .
- the gate contacts 142 are physically and electrically coupled to the gate electrodes 124 .
- the source/drain contacts 144 are physically and electrically coupled to the epitaxial source/drain regions 98 .
- openings for the gate contacts 142 are formed through the second ILD 134 and the ESL 132
- openings for the source/drain contacts 144 are formed through the second ILD 134 , the ESL 132 , the first ILD 104 , and the CESL 102 .
- the openings may be formed using acceptable photolithography and etching techniques.
- a liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings.
- the liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.
- the conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like.
- a planarization process such as a CMP, may be performed to remove excess material from a surface of the second ILD 134 .
- the remaining liner and conductive material form the gate contacts 142 and the source/drain contacts 144 in the openings.
- the gate contacts 142 and the source/drain contacts 144 may be formed in distinct processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the gate contacts 142 and the source/drain contacts 144 may be formed in different cross-sections, which may avoid shorting of the contacts.
- metal-semiconductor alloy regions 146 are formed at the interfaces between the epitaxial source/drain regions 98 and the source/drain contacts 144 .
- the metal-semiconductor alloy regions 146 can be silicide regions formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed of a metal germanide (e.g. titanium germanide, cobalt germanide, nickel germanide, etc.), silicon-germanide regions formed of both a metal silicide and a metal germanide, or the like.
- the metal-semiconductor alloy regions 146 can be formed before the material(s) of the source/drain contacts 144 by depositing a metal in the openings for the source/drain contacts 144 and then performing a thermal anneal process.
- the metal can be any metal capable of reacting with the semiconductor materials (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source/drain regions 98 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys.
- the metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like.
- a cleaning process such as a wet clean, may be performed to remove any residual metal from the openings for the source/drain contacts 144 , such as from surfaces of the metal-semiconductor alloy regions 146 .
- the material(s) of the source/drain contacts 144 can then be formed on the metal-semiconductor alloy regions 146 .
- the work function tuning layers for the n-type devices are formed before the work function tuning layers for the p-type devices to allow more control of the threshold voltages of the resulting devices.
- the method of forming the work function tuning layers for the n-type devices before the work function tuning layers for the p-type devices includes the formation and patterning of sacrificial layers to prevent the work function tuning layers for the n-type devices from being formed between the nanostructures of the p-type devices. This helps to prevent the work function tuning layers from remaining on the p-type devices which could degrade the performance of the p-type devices.
- a protection layer is formed between the work function tuning layer and a glue layer to inhibit (e.g., substantially prevents or at least reduces) diffusion of the work function tuning layer. The threshold voltages of the resulting devices may thus be more accurately tuned.
- An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region.
- the device also includes a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region.
- the device also includes a gate dielectric layer wrapping around each of the first and second sets of nanostructures.
- the device also includes a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, the first work function tuning layer including an n-type work function metal.
- the device also includes a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures.
- the device also includes a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal.
- the device also includes a fill layer on the second work function tuning layer.
- Embodiments may include one or more of the following features.
- the device where the glue layer includes titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, silicon-doped tantalum aluminide.
- the device further including a protective layer between the first work function tuning layer and the glue layer on the first set of nanostructures, the protective layer wrapping around each of the first set of nanostructures.
- the protective layer includes amorphous silicon.
- the glue layer separates and fills an area between respective portions of the protective layer on adjacent nanostructures of the first set of nanostructures.
- the glue layer separates and fills an area between respective portions of the first work function tuning layer on adjacent nanostructures of the first set of nanostructures.
- the second work function tuning layer separates and fills an area between respective portions of the gate dielectric layer on adjacent nanostructures of the second set of nanostructures.
- the fill layer does not extend between adjacent nanostructures of the second set of nanostructures.
- An embodiment includes a method including forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region.
- the method also includes forming a gate dielectric layer having a first portion and a second portion, the first portion deposited on the first channel region, the second portion deposited on the second channel region.
- the method also includes forming a first work function tuning layer on the first portion of the gate dielectric layer and the second portion of the gate dielectric layer.
- the method also includes forming a glue layer on the first work function tuning layer.
- the method also includes removing the glue layer and the first work function tuning layer from the second portion of the gate dielectric layer.
- the method also includes forming a second work function tuning layer on the remaining glue layer and the second portion of the gate dielectric layer.
- the method also includes forming a fill layer on the second work function tuning layer.
- Embodiments may include one or more of the following features.
- the method where the first work function tuning layer includes an n-type work function metal, and where the second work function tuning layer including an p-type work function metal.
- the method further including before forming the first work function tuning layer, forming a sacrificial layer on the second portion of the gate dielectric layer between adjacent nanostructures of the second set of nanostructures, the first work function layer being formed on the sacrificial layer and the second portion of the gate dielectric layer.
- Forming the sacrificial layer on the second portion of the gate dielectric layer between adjacent nanostructures of the second set of nanostructures further includes forming a first sacrificial layer on the first portion and the second portion of the gate dielectric layer, trimming the first sacrificial layer to expose portions of the first portion and the second portion of the gate dielectric layer, where after the trimming, portions of the first sacrificial layer remain between adjacent nanostructures of both the first and second sets of nanostructures, forming a second sacrificial layer on the exposed portions of the first portion and the second portion of the gate dielectric layer and the remaining portions of the first sacrificial layer, removing the first and second sacrificial layers from the first set of nanostructures to expose the first portion of the gate dielectric layer, and trimming the second sacrificial layer to expose portions of the second portion of the gate dielectric layer, where after the trimming, portions of the first sacrificial layer remain between adjacent nanostructures of the second set of nanostructures.
- Forming the first work function tuning layer includes depositing titanium aluminum carbide by an ALD process, the ALD process performed with titanium chloride and triethylaluminium, the ALD process performed at a temperature in a range of 100° C. to 600° C., the ALD process performed at a pressure in a range of 1 torr to 100 torr.
- the ALD process includes the same number of pulses of titanium chloride and triethylaluminium in each ALD cycle.
- the ALD process includes more pulses of triethylaluminium than titanium chloride in each ALD cycle.
- the method further including forming a protective layer on the first work function tuning layer on the first set of nanostructures, the glue layer being formed on the protective layer on the first set of nanostructures.
- the protective layer includes amorphous silicon.
- An embodiment includes a method including forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region.
- the method also includes forming a gate dielectric layer on the first channel region.
- the method also includes forming a second gate dielectric layer on the second channel region.
- the method also includes forming a sacrificial layer between the second set of nanostructures.
- the method also includes forming a n-type work function tuning layer on the first gate dielectric layer, the second gate dielectric layer, and the sacrificial layer, the n-type work function tuning layer wrapping around each of the first set of nanostructures.
- the method also includes forming a glue layer on the n-type work function tuning layer, the glue layer wrapping around each of the first set of nanostructures.
- the method also includes removing the glue layer, the n-type work function tuning layer, and the sacrificial layer from the second gate dielectric layer.
- the method also includes forming a p-type work function tuning layer on the glue layer on the first set of nanostructures and the second gate dielectric layer.
- the method also includes forming a fill layer on the p-type work function tuning layer.
- Embodiments may include one or more of the following features.
- the method where forming a sacrificial layer between the second set of nanostructures further includes forming a first sacrificial layer on the first and second gate dielectric layers, trimming the first sacrificial layer to expose portions of the first and second gate dielectric layers, where after the trimming, portions of the first sacrificial layer remain between adjacent nanostructures of both the first and second sets of nanostructures, forming a second sacrificial layer on the exposed portions of the first and second gate dielectric layers and the remaining portions of the first sacrificial layer, removing the first and second sacrificial layers from the first set of nanostructures to expose the first gate dielectric layer, and trimming the second sacrificial layer to expose portions of the second gate dielectric layer, where after the trimming, portions of the first sacrificial layer remain between adjacent nanostructures of the second set of nanostructures.
- Forming the n-type work function tuning layer includes depositing titanium aluminum carbide by an ALD process, the ALD process includes performing multiple ALD cycles, where each ALD cycle includes pulses of titanium chloride and triethylaluminium, the ALD process performed at a temperature in a range of 100° C. to 600° C., the ALD process performed at a pressure in a range of 1 torr to 100 torr, where the ALD process includes more pulses of triethylaluminium than titanium chloride in each ALD cycle.
Abstract
An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region, a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region, a gate dielectric layer wrapping around each of the first and second sets of nanostructures, a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures, a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, and a fill layer on the second work function tuning layer.
Description
- This application is a divisional of U.S. patent application Ser. No. 17/314,752, filed May 7, 2021, entitled “SEMICONDUCTOR DEVICE AND METHOD,” which claims the benefit claims the benefit of U.S. Provisional Application No. 63/153,995, filed on Feb. 26, 2021, which application is hereby incorporated herein by reference.
- Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments. -
FIGS. 2 through 27B are views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments. -
FIG. 28 is a flow chart of an example method for forming replacement gates for nano-FETs, in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- According to various embodiments, replacement gate electrodes for p-type devices and n-type devices are formed. In some embodiments, the work function tuning layers for the n-type devices are formed before the work function tuning layers for the p-type devices to allow more control of the threshold voltages of the resulting devices. The method of forming the work function tuning layers for the n-type devices before the work function tuning layers for the p-type devices includes the formation and patterning of sacrificial layers to prevent the work function tuning layers for the n-type devices from being formed between the nanostructures of the p-type devices. This helps to prevent the work function tuning layers from remaining on the p-type devices which could degrade the performance of the p-type devices. In some embodiments, a protection layer is formed between the work function tuning layer and a glue layer to inhibit (e.g., substantially prevents or at least reduces) diffusion of the work function tuning layer. The threshold voltages of the resulting devices may thus be more accurately tuned.
- Embodiments are described in a particular context, a die including nano-FETs. Various embodiments may be applied, however, to dies including other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in lieu of or in combination with the nano-FETs.
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FIG. 1 illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like), in accordance with some embodiments.FIG. 1 is a three-dimensional view, where some features of the nano-FETs are omitted for illustration clarity. The nano-FETs may be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), or the like. - The nano-FETs include nanostructures 66 (e.g., nanosheets, nanowires, or the like) over
fins 62 on a substrate 50 (e.g., a semiconductor substrate), with thenanostructures 66 acting as channel regions for the nano-FETs. Thenanostructures 66 may include p-type nanostructures, n-type nanostructures, or a combination thereof.Isolation regions 70, such as shallow trench isolation (STI) regions, are disposed betweenadjacent fins 62, which may protrude above and from betweenadjacent isolation regions 70. Although theisolation regions 70 are described/illustrated as being separate from thesubstrate 50, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of thefins 62 are illustrated as being single, continuous materials with thesubstrate 50, the bottom portion of thefins 62 and/or thesubstrate 50 may include a single material or a plurality of materials. In this context, thefins 62 refer to the portion extending above and from between theadjacent isolation regions 70. -
Gate dielectrics 122 are over top surfaces of thefins 62 and along top surfaces, sidewalls, and bottom surfaces of thenanostructures 66.Gate electrodes 124 are over thegate dielectrics 122. Epitaxial source/drain regions 98 are disposed on thefins 62 at opposing sides of thegate dielectrics 122 and thegate electrodes 124. The epitaxial source/drain regions 98 may be shared betweenvarious fins 62. For example, adjacent epitaxial source/drain regions 98 may be electrically connected, such as through coalescing the epitaxial source/drain regions 98 by epitaxial growth, or through coupling the epitaxial source/drain regions 98 with a same source/drain contact. -
FIG. 1 further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of agate electrode 124 and in a direction, for example, perpendicular to a direction of current flow between the epitaxial source/drain regions 98 of a nano-FET. Cross-section B-B′ is along a longitudinal axis of afin 62 and in a direction of, for example, a current flow between the epitaxial source/drain regions 98 of the nano-FET. Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions 98 of the nano-FETs. Subsequent figures refer to these reference cross-sections for clarity. - Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs). For example, FinFETs may include fins on a substrate, with the fins acting as channel regions for the FinFETs. Similarly, planar FETs may include a substrate, with portions of the substrate acting as channel regions for the planar FETs.
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FIGS. 2 through 27B are views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.FIGS. 2, 3, 4, 5 , and 6 are three-dimensional views showing a similar three-dimensional view asFIG. 1 .FIGS. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B , 21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B, 25A, 26A, and 27A illustrate reference cross-section A-A′ illustrated inFIG. 1 , except two fins are shown.FIGS. 7B, 8B, 9B, 10B, 11B, 12B, 13B, 25B, 26B, 27B illustrate reference cross-section B-B′ illustrated inFIG. 1 .FIGS. 9C and 9D illustrate reference cross-section C-C′ illustrated inFIG. 1 , except two fins are shown. - In
FIG. 2 , asubstrate 50 is provided for forming nano-FETs. Thesubstrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or a n-type impurity) or undoped. Thesubstrate 50 may be a wafer, such as a silicon wafer. Generally, a SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of thesubstrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; combinations thereof; or the like. - The
substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region 50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region 50N may be physically separated from the p-type region 50P (not separately illustrated), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P may be provided. - The
substrate 50 may be lightly doped with a p-type or an n-type impurity. An anti-punch-through (APT) implantation may be performed on an upper portion of thesubstrate 50 to form an APT region. During the APT implantation, impurities may be implanted in thesubstrate 50. The impurities may have a conductivity type opposite from a conductivity type of source/drain regions that will be subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend under the source/drain regions in the nano-FETs. The APT region may be used to reduce the leakage from the source/drain regions to thesubstrate 50. In some embodiments, the doping concentration in the APT region may be in the range of 1018 cm−3 to 1019 cm−3. - A
multi-layer stack 52 is formed over thesubstrate 50. Themulti-layer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. The semiconductor materials may each be selected from the candidate semiconductor materials of thesubstrate 50. In the illustrated embodiment, themulti-layer stack 52 includes three layers of each of the first semiconductor layers 54 and the second semiconductor layers 56. It should be appreciated that themulti-layer stack 52 may include any number of the first semiconductor layers 54 and the second semiconductor layers 56. - In the illustrated embodiment, and as will be subsequently described in greater detail, the first semiconductor layers 54 will be removed and the second semiconductor layers 56 will patterned to form channel regions for the nano-FETs in both the n-
type region 50N and the p-type region 50P. The first semiconductor layers 54 are sacrificial layers (or dummy layers), which will be removed in subsequent processing to expose the top surfaces and the bottom surfaces of the second semiconductor layers 56. The first semiconductor material of the first semiconductor layers 54 is a material that has a high etching selectivity from the etching of the second semiconductor layers 56, such as silicon germanium. The second semiconductor material of the second semiconductor layers 56 is a material suitable for both n-type and p-type devices, such as silicon. - In another embodiment (not separately illustrated), the first semiconductor layers 54 will be patterned to form channel regions for nano-FETs in one region (e.g., the p-
type region 50P), and the second semiconductor layers 56 will be patterned to form channel regions for nano-FETs in another region (e.g., the n-type region 50N). The first semiconductor material of the first semiconductor layers 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., SixGe1-x, where x can be in the range of 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material of the second semiconductor layers 56 may be a material suitable for n-type devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material may have a high etching selectivity from the etching of one another, so that the first semiconductor layers 54 may be removed without removing the second semiconductor layers 56 in the n-type region 50N, and the second semiconductor layers 56 may be removed without removing the first semiconductor layers 54 in the p-type region 50P. - Each of the layers of the
multi-layer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. Each of the layers may have a small thickness, such as a thickness in a range from 5 nm to 30 nm. In some embodiments, some layers (e.g., the second semiconductor layers 56) are formed to be thinner than other layers (e.g., the first semiconductor layers 54). For example, in embodiments in which the first semiconductor layers 54 are sacrificial layers (or dummy layers) and the second semiconductor layers 56 are patterned to form channel regions for the nano-FETs in both the n-type region 50N and the p-type region 50P, the first semiconductor layers 54 can have a first thickness T1 and the second semiconductor layers 56 can have a second thickness T2, with the second thickness T2 being from 30% to 60% less than the first thickness T1. Forming the second semiconductor layers 56 to a smaller thickness allows the channel regions to be formed at a greater density. - In
FIG. 3 , trenches are patterned in thesubstrate 50 and themulti-layer stack 52 to formfins 62,first nanostructures 64, andsecond nanostructures 66. Thefins 62 are semiconductor strips patterned in thesubstrate 50. Thefirst nanostructures 64 and thesecond nanostructures 66 include the remaining portions of the first semiconductor layers 54 and the second semiconductor layers 56, respectively. The trenches may be patterned by any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. - The
fins 62 and thenanostructures fins 62 and thenanostructures fins 62 and thenanostructures nanostructures - The
fins 62 and thenanostructures fins 62 and thenanostructures type region 50N and the p-type region 50P. In another embodiment, thefins 62 and thenanostructures type region 50N) are wider or narrower than thefins 62 and thenanostructures type region 50P). - In
FIG. 4 ,STI regions 70 are formed over thesubstrate 50 and betweenadjacent fins 62. TheSTI regions 70 are disposed around at least a portion of thefins 62 such that at least a portion of thenanostructures adjacent STI regions 70. In the illustrated embodiment, the top surfaces of theSTI regions 70 are coplanar (within process variations) with the top surfaces of thefins 62. In some embodiments, the top surfaces of theSTI regions 70 are above or below the top surfaces of thefins 62. TheSTI regions 70 separate the features of adjacent devices. - The
STI regions 70 may be formed by any suitable method. For example, an insulation material can be formed over thesubstrate 50 and thenanostructures adjacent fins 62. The insulation material may be an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, which may be formed by a chemical vapor deposition (CVD) process, such as high density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In some embodiments, the insulation material is silicon oxide formed by FCVD. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers thenanostructures STI regions 70 are each illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along surfaces of thesubstrate 50, thefins 62, and thenanostructures - A removal process is then applied to the insulation material to remove excess insulation material over the
nanostructures nanostructures nanostructures nanostructures nanostructures STI regions 70. The insulation material is recessed such that at least a portion of thenanostructures STI regions 70 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of theSTI regions 70 may be formed flat, convex, and/or concave by an appropriate etch. The insulation material may be recessed using any acceptable etching process, such as one that is selective to the material of the insulation material (e.g., selectively etches the insulation material of theSTI regions 70 at a faster rate than the materials of thefins 62 and thenanostructures 64, 66). For example, an oxide removal may be performed using dilute hydrofluoric (dHF) acid. - The process previously described is just one example of how the
fins 62 and thenanostructures fins 62 and/or thenanostructures substrate 50, and trenches can be etched through the dielectric layer to expose theunderlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form thefins 62 and/or thenanostructures - Further, appropriate wells (not separately illustrated) may be formed in the
substrate 50, thefins 62, and/or thenanostructures type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N, and an n-type well is formed in the p-type region 50P. In some embodiments, a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P. - In embodiments with different well types, different implant steps for the n-
type region 50N and the p-type region 50P may be achieved using mask (not separately illustrated) such as a photoresist. For example, a photoresist may be formed over thefins 62, thenanostructures STI regions 70 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in the range of 1013 cm−3 to 1014 cm−3. After the implant, the photoresist may be removed, such as by any acceptable ashing process. - Following or prior to the implanting of the p-
type region 50P, a mask (not separately illustrated) such as a photoresist is formed over thefins 62, thenanostructures STI regions 70 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region 50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in the range of 1013 cm−3 to 1014 cm−3. After the implant, the photoresist may be removed, such as by any acceptable ashing process. - After the implants of the n-
type region 50N and the p-type region 50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments where epitaxial structures are epitaxially grown for thefins 62 and/or thenanostructures - In
FIG. 5 , adummy dielectric layer 72 is formed on thefins 62 and thenanostructures dummy dielectric layer 72 may be formed of a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, which may be deposited or thermally grown according to acceptable techniques. Adummy gate layer 74 is formed over thedummy dielectric layer 72, and amask layer 76 is formed over thedummy gate layer 74. Thedummy gate layer 74 may be deposited over thedummy dielectric layer 72 and then planarized, such as by a CMP. Themask layer 76 may be deposited over thedummy gate layer 74. Thedummy gate layer 74 may be formed of a conductive or non-conductive material, such as amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), a metal, a metallic nitride, a metallic silicide, a metallic oxide, or the like, which may be deposited by physical vapor deposition (PVD), CVD, or the like. Thedummy gate layer 74 may be formed of material(s) that have a high etching selectivity from the etching of insulation materials, e.g., theSTI regions 70 and/or thedummy dielectric layer 72. Themask layer 76 may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a singledummy gate layer 74 and asingle mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, thedummy dielectric layer 72 covers thefins 62, thenanostructures STI regions 70, such that thedummy dielectric layer 72 extends over theSTI regions 70 and between thedummy gate layer 74 and theSTI regions 70. In another embodiment, thedummy dielectric layer 72 covers only thefins 62 and thenanostructures - In
FIG. 6 , themask layer 76 is patterned using acceptable photolithography and etching techniques to form masks 86. The pattern of themasks 86 is then transferred to thedummy gate layer 74 by any acceptable etching technique to formdummy gates 84. The pattern of themasks 86 may optionally be further transferred to thedummy dielectric layer 72 by any acceptable etching technique to form dummy dielectrics 82. Thedummy gates 84 cover portions of thenanostructures dummy gates 84 extend along the portions of thenanostructures 66 that will be patterned to formchannel regions 68. The pattern of themasks 86 may be used to physically separateadjacent dummy gates 84. Thedummy gates 84 may also have lengthwise directions substantially perpendicular (within process variations) to the lengthwise directions of thefins 62. Themasks 86 can optionally be removed after patterning, such as by any acceptable etching technique. -
FIGS. 7A through 22B illustrate various additional steps in the manufacturing of embodiment devices.FIGS. 7A through 13B andFIGS. 21A through 22B illustrate features in either of the n-type region 50N and the p-type region 50P. For example, the structures illustrated may be applicable to both the n-type region 50N and the p-type region 50P. Differences (if any) in the structures of the n-type region 50N and the p-type region 50P are described in the text accompanying each figure.FIGS. 14A, 15A, 16A, 17A, 18A, 19A, and 20A illustrate features in the n-type region 50N.FIGS. 14B, 15B, 16B, 17B, 18B, 19B, and 20B illustrate features in the p-type region 50P. - In
FIGS. 7A and 7B ,gate spacers 90 are formed over thenanostructures dummy gates 84, and the dummy dielectrics 82. The gate spacers 90 may be formed by conformally depositing one or more dielectric material(s) and subsequently etching the dielectric material(s). Acceptable dielectric materials include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or the like; multilayers thereof; or the like. The dielectric materials may be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. In the illustrated embodiment, thegate spacers 90 each include multiple layers, e.g., afirst spacer layer 90A and asecond spacer layer 90B. In some embodiments, thefirst spacer layers 90A and the second spacer layers 90B are formed of silicon oxycarbonitride (e.g., SiOxNyC1-x-y, where x and y are in the range of 0 to 1). For example, the first spacer layers 90A can be formed of a similar or a different composition of silicon oxycarbonitride than the second spacer layers 90B. An acceptable etch process, such as a dry etch, a wet etch, the like, or a combination thereof, may be performed to pattern the dielectric material(s). The etching may be anisotropic. The dielectric material(s), when etched, have portions left on the sidewalls of the dummy gates 84 (thus forming the gate spacers 90). After etching, thegate spacers 90 can have straight sidewalls (as illustrated) or can have curved sidewalls (not illustrated). As will be subsequently described in greater detail, the dielectric material(s), when etched, may have portions left on the sidewalls of thefins 62 and/or thenanostructures 64, 66 (thus forming fin spacers). - Further, implants may be performed to form lightly doped source/drain (LDD) regions (not separately illustrated). In the embodiments with different device types, similar to the implants for the wells previously described, a mask (not separately illustrated) such as a photoresist may be formed over the n-
type region 50N, while exposing the p-type region 50P, and appropriate type (e.g., p-type) impurities may be implanted into thefins 62 and/or thenanostructures type region 50P. The mask may then be removed. Subsequently, a mask (not separately illustrated) such as a photoresist may be formed over the p-type region 50P while exposing the n-type region 50N, and appropriate type impurities (e.g., n-type) may be implanted into thefins 62 and/or thenanostructures type region 50N. The mask may then be removed. The n-type impurities may be any of the n-type impurities previously described, and the p-type impurities may be any of the p-type impurities previously described. During the implanting, thechannel regions 68 remain covered by thedummy gates 84, so that thechannel regions 68 remain substantially free of the impurity implanted to form the LDD regions. The LDD regions may have a concentration of impurities in the range of 1015 cm−3 to 1019 cm−3. An anneal may be used to repair implant damage and to activate the implanted impurities. - It is noted that the previous disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized, additional spacers may be formed and removed, and/or the like. Furthermore, the n-type devices and the p-type devices may be formed using different structures and steps.
- In
FIGS. 8A and 8B , source/drain recesses 94 are formed in thenanostructures nanostructures fins 62. The source/drain recesses 94 may also extend into thesubstrate 50. In various embodiments, the source/drain recesses 94 may extend to a top surface of thesubstrate 50 without etching thesubstrate 50; thefins 62 may be etched such that bottom surfaces of the source/drain recesses 94 are disposed below the top surfaces of theSTI regions 70; or the like. The source/drain recesses 94 may be formed by etching thenanostructures dummy gates 84 collectively mask portions of thefins 62 and/or thenanostructures nanostructures nanostructures - Optionally,
inner spacers 96 are formed on the sidewalls of the remaining portions of thefirst nanostructures 64, e.g., those sidewalls exposed by the source/drain recesses 94. As will be subsequently described in greater detail, source/drain regions will be subsequently formed in the source/drain recesses 94, and thefirst nanostructures 64 will be subsequently replaced with corresponding gate structures. Theinner spacers 96 act as isolation features between the subsequently formed source/drain regions and the subsequently formed gate structures. Further, theinner spacers 96 may be used to substantially prevent damage to the subsequently formed source/drain regions by subsequent etching processes, such as etching processes used to subsequently remove thefirst nanostructures 64. - As an example to form the
inner spacers 96, the source/drain recesses 94 can be laterally expanded. Specifically, portions of the sidewalls of thefirst nanostructures 64 exposed by the source/drain recesses 94 may be recessed. Although sidewalls of thefirst nanostructures 64 are illustrated as being straight, the sidewalls may be concave or convex. The sidewalls may be recessed by any acceptable etching process, such as one that is selective to the material of the first nanostructures 64 (e.g., selectively etches the material of thefirst nanostructures 64 at a faster rate than the material of the second nanostructures 66). The etching may be isotropic. For example, when thesecond nanostructures 66 are formed of silicon and thefirst nanostructures 64 are formed of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process may be a dry etch using a fluorine-based gas such as hydrogen fluoride (HF) gas. In some embodiments, the same etching process may be continually performed to both form the source/drain recesses 94 and recess the sidewalls of thefirst nanostructures 64. Theinner spacers 96 can then be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material may be silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than 3.5, may be utilized. The insulating material may be deposited by a conformal deposition process, such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch such as a RIE, a NBE, or the like. Although outer sidewalls of theinner spacers 96 are illustrated as being flush with respect to the sidewalls of thegate spacers 90, the outer sidewalls of theinner spacers 96 may extend beyond or be recessed from the sidewalls of thegate spacers 90. In other words, theinner spacers 96 may partially fill, completely fill, or overfill the sidewall recesses. Moreover, although the sidewalls of theinner spacers 96 are illustrated as being straight, the sidewalls of theinner spacers 96 may be concave or convex. - In
FIGS. 9A and 9B , epitaxial source/drain regions 98 are formed in the source/drain recesses 94. The epitaxial source/drain regions 98 are formed in the source/drain recesses 94 such that each dummy gate 84 (and corresponding channel regions 68) is disposed between respective adjacent pairs of the epitaxial source/drain regions 98. In some embodiments, thegate spacers 90 and theinner spacers 96 are used to separate the epitaxial source/drain regions 98 from, respectively, thedummy gates 84 and thefirst nanostructures 64 by an appropriate lateral distance so that the epitaxial source/drain regions 98 do not short out with subsequently formed gates of the resulting nano-FETs. A material of the epitaxial source/drain regions 98 may be selected to exert stress in therespective channel regions 68, thereby improving performance. - The epitaxial source/
drain regions 98 in the n-type region 50N may be formed by masking the p-type region 50P. Then, the epitaxial source/drain regions 98 in the n-type region 50N are epitaxially grown in the source/drain recesses 94 in the n-type region 50N. The epitaxial source/drain regions 98 may include any acceptable material appropriate for n-type devices. For example, the epitaxial source/drain regions 98 in the n-type region 50N may include materials exerting a tensile strain on thechannel regions 68, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions 98 in the n-type region 50N may have surfaces raised from respective surfaces of thefins 62 and thenanostructures - The epitaxial source/
drain regions 98 in the p-type region 50P may be formed by masking the n-type region 50N. Then, the epitaxial source/drain regions 98 in the p-type region 50P are epitaxially grown in the source/drain recesses 94 in the p-type region 50P. The epitaxial source/drain regions 98 may include any acceptable material appropriate for p-type devices. For example, the epitaxial source/drain regions 98 in the p-type region 50P may include materials exerting a compressive strain on thechannel regions 68, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions 98 in the p-type region 50P may have surfaces raised from respective surfaces of thefins 62 and thenanostructures - The epitaxial source/
drain regions 98, thenanostructures fins 62 may be implanted with impurities to form source/drain regions, similar to the process previously described for forming LDD regions, followed by an anneal. The source/drain regions may have an impurity concentration in the range of 1019 cm−3 to 1021 cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously described. In some embodiments, the epitaxial source/drain regions 98 may be in situ doped during growth. - As a result of the epitaxy processes used to form the epitaxial source/
drain regions 98, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of thefins 62 and thenanostructures drain regions 98 to merge as illustrated byFIG. 9C . In some embodiments, adjacent epitaxial source/drain regions 98 remain separated after the epitaxy process is completed as illustrated byFIG. 9D . In the illustrated embodiments, the spacer etch used to form thegate spacers 90 is adjusted to also formfin spacers 92 on sidewalls of thefins 62 and/or thenanostructures fins 62 and/or thenanostructures STI regions 70, thereby blocking the epitaxial growth. In another embodiment, the spacer etch used to form thegate spacers 90 is adjusted to not form fin spacers, so as to allow the epitaxial source/drain regions 98 to extend to the surface of theSTI regions 70. - The epitaxial source/
drain regions 98 may include one or more semiconductor material layers. For example, the epitaxial source/drain regions 98 may each include aliner layer 98A, amain layer 98B, and afinishing layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source/drain regions 98. Each of theliner layer 98A, themain layer 98B, and thefinishing layer 98C may be formed of different semiconductor materials and may be doped to different impurity concentrations. In some embodiments, theliner layer 98A may have a lesser concentration of impurities than themain layer 98B, and thefinishing layer 98C may have a greater concentration of impurities than theliner layer 98A and a lesser concentration of impurities than themain layer 98B. In embodiments in which the epitaxial source/drain regions 98 include three semiconductor material layers, the liner layers 98A may be grown in the source/drain recesses 94, themain layers 98B may be grown on the liner layers 98A, and the finishing layers 98C may be grown on themain layers 98B. - In
FIGS. 10A and 10B , a first inter-layer dielectric (ILD) 104 is deposited over the epitaxial source/drain regions 98, thegate spacers 90, the masks 86 (if present) or thedummy gates 84. Thefirst ILD 104 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Acceptable dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. - In some embodiments, a contact etch stop layer (CESL) 102 is formed between the
first ILD 104 and the epitaxial source/drain regions 98, thegate spacers 90, and the masks 86 (if present) or thedummy gates 84. TheCESL 102 may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etching selectivity from the etching of thefirst ILD 104. TheCESL 102 may be formed by any suitable method, such as CVD, ALD, or the like. - In
FIGS. 11A and 11B , a removal process is performed to level the top surfaces of thefirst ILD 104 with the top surfaces of the masks 86 (if present) or thedummy gates 84. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process may also remove themasks 86 on thedummy gates 84, and portions of thegate spacers 90 along sidewalls of themasks 86. After the planarization process, the top surfaces of thegate spacers 90, thefirst ILD 104, theCESL 102, and the masks 86 (if present) or thedummy gates 84 are coplanar (within process variations). Accordingly, the top surfaces of the masks 86 (if present) or thedummy gates 84 are exposed through thefirst ILD 104. In the illustrated embodiment, themasks 86 remain, and the planarization process levels the top surfaces of thefirst ILD 104 with the top surfaces of themasks 86. - In
FIGS. 12A and 12B , the masks 86 (if present) and thedummy gates 84 are removed in an etching process, so thatrecesses 110 are formed. Portions of the dummy dielectrics 82 in therecesses 110 are also removed. In some embodiments, thedummy gates 84 are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch thedummy gates 84 at a faster rate than thefirst ILD 104 or thegate spacers 90. During the removal, the dummy dielectrics 82 may be used as etch stop layers when thedummy gates 84 are etched. The dummy dielectrics 82 are then removed. Eachrecess 110 exposes and/or overlies portions of thechannel regions 68. Portions of thesecond nanostructures 66 which act as thechannel regions 68 are disposed between adjacent pairs of the epitaxial source/drain regions 98. - The remaining portions of the
first nanostructures 64 are then removed to expand therecesses 110. The remaining portions of thefirst nanostructures 64 can be removed by any acceptable etching process that selectively etches the material of thefirst nanostructures 64 at a faster rate than the material of thesecond nanostructures 66. The etching may be isotropic. For example, when thefirst nanostructures 64 are formed of silicon germanium and thesecond nanostructures 66 are formed of silicon, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), NH4OH, H2O2, H2O, HF, C3H8O2, C2H4C3, the like, or combinations thereof. In some embodiments, a trim process (not separately illustrated) is performed to decrease the thicknesses of the exposed portions of thesecond nanostructures 66. As illustrated more clearly inFIGS. 14A through 20B (subsequently described in greater detail), the remaining portions of thesecond nanostructures 66 can have rounded corners. - In
FIGS. 13A and 13B , agate dielectric layer 112 is formed in therecesses 110. Agate electrode layer 114 is formed on thegate dielectric layer 112. Thegate dielectric layer 112 and thegate electrode layer 114 are layers for replacement gates, and each wrap around all (e.g., four) sides of thesecond nanostructures 66. - The
gate dielectric layer 112 is disposed on the sidewalls and/or the top surfaces of thefins 62; on the top surfaces, the sidewalls, and the bottom surfaces of thesecond nanostructures 66; and on the sidewalls of thegate spacers 90. Thegate dielectric layer 112 may also be formed on the top surfaces of thefirst ILD 104 and thegate spacers 90. Thegate dielectric layer 112 may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, combinations thereof, multi-layers thereof, or the like. Thegate dielectric layer 112 may include a dielectric material having a k-value greater than 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although a single layeredgate dielectric layer 112 is illustrated inFIGS. 13A and 13B , as will be subsequently described in greater detail, thegate dielectric layer 112 may include an interfacial layer and a main layer. - The
gate electrode layer 114 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, multi-layers thereof, or the like. Although a single-layeredgate electrode layer 114 is illustrated inFIGS. 13A and 13B , as will be subsequently described in greater detail, thegate electrode layer 114 may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and a fill material. -
FIGS. 14A through 24B illustrate a process in which layers for replacement gates are formed in therecesses 110. Features in regions that are similar to aregion 50R inFIG. 13A are illustrated.FIG. 28 is a flow chart of anexample method 200 for forming the replacement gate layers, in accordance with some embodiments.FIGS. 14A through 24B are described in conjunction withFIG. 28 . - In
FIGS. 14A and 14B and step 202 of themethod 200, thegate dielectric layer 112 is deposited in therecesses 110 in both the first region (e.g., the n-type region 50N) and the second region (e.g., the p-type region 50P). Thegate dielectric layer 112 may also be deposited on the top surfaces of thefirst ILD 104 and the gate spacers 90 (seeFIG. 13B ). In the illustrated embodiment, thegate dielectric layer 112 is multilayered, including aninterfacial layer 112A (or more generally, a first gate dielectric layer) and an overlying high-k dielectric layer 112B (or more generally, a second gate dielectric layer). Theinterfacial layer 112A may be formed of silicon oxide or the like and the high-k dielectric layer 112B may be formed of hafnium oxide, lanthanum oxide, or the like. The formation methods of thegate dielectric layer 112 may include molecular-beam deposition (MBD), ALD, PECVD, and the like. Thegate dielectric layer 112 wraps around all (e.g., four) sides of thesecond nanostructures 66. - In some embodiments, the
second nanostructures 66 have a width W1 in a range from 1 nm to 50 nm, such as a range from 15 nm to 25 nm. In some embodiments, adjacentsecond nanostructures 66 are spaced apart by a spacing S1 in a range from 0.1 nm to 40 nm, such as a range from 3 nm to 8 nm. If the spacing S1 is higher than 40 nm, a seam or void may be formed between adjacentsecond nanostructures 66 after the subsequent formation of the gate structures. If the spacing S1 is lower than 0.1 nm, the adjacentsecond nanostructures 66 could easily short to each other. - In
FIGS. 15A and 15B and step 204 of themethod 200, a firstsacrificial layer 116A is deposited on thegate dielectric layer 112 in the first region (e.g., the n-type region 50N) and the second region (e.g., the p-type region 50P). As will be subsequently described in greater detail, the firstsacrificial layer 116A will be patterned to remove portions of the firstsacrificial layer 116A in the first region (e.g., the n-type region 50N) while leaving portions of the firstsacrificial layer 116A in the second region (e.g., the p-type region 50P). Specifically, the firstsacrificial layer 116A is used to ease the removal of work function layers from the second region (e.g., the p-type region 50P) by not allowing those work function layers to get between thesecond nanostructures 66. The firstsacrificial layer 116A includes any acceptable material that can be formed on and removed from betweensecond nanostructures 66, and may be deposited using any acceptable deposition process. For example, the firstsacrificial layer 116A is formed of TiN, WCN, WCl5, TaCl5, SnCl4, combinations thereof, or the like, which may be deposited by ALD, CVD, PVD, or the like. Although the firstsacrificial layer 116A is shown as being single layered, the firstsacrificial layer 116A can be multilayered. The firstsacrificial layer 116A may fill portions of thesecond recesses 110 extending between vertically adjacent ones of thenanostructures 66 and extending between thenanostructures 66 and thefins 62. - In
FIGS. 16A and 16B and step 206 of themethod 200, portions of the firstsacrificial layer 116A are removed from the first region (e.g., the n-type region 50N) and the second region (e.g., the p-type region 50P). Removing the portions of the firstsacrificial layer 116A allows for the subsequent formation of a secondsacrificial layer 116B to protect thegate dielectric layer 112 while potentially providing etch selectivity to the firstsacrificial layer 116A. The removal may be by acceptable photolithography and etching techniques. The etching may include any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. As illustrated inFIGS. 16A and 16B , the removal of portions of firstsacrificial layer 116A removes outer portions of the firstsacrificial layer 116A to expose thegate dielectric layer 112 but leaves the firstsacrificial layer 116A between vertically adjacent ones of thenanostructures 66 and extending between thenanostructures 66 and thefins 62 in both the first andsecond regions sacrificial layer 116A while leaving inner portions may be referred to as a trimming process. - After the removal of portions of the first
sacrificial layer 116A, thegate dielectric layer 112 remains over and covers isolations regions 70 (see, e.g.,FIG. 13A ). These portions ofgate dielectric layer 112 can help to protect theisolation regions 70 from damage from subsequent deposition and removal processes. - In some embodiments, a single etch is performed to remove the portions of the first
sacrificial layer 116A. The single etch may be selective to the materials of the firstsacrificial layer 116A (e.g., selectively etches the material of the firstsacrificial layer 116A at a faster rate than the material(s) of the gate dielectric layer 112). In some embodiments, multiple etch steps/processes are performed to remove the portions of the firstsacrificial layer 116A. - In
FIGS. 17A and 17B and step 208 of themethod 200, a secondsacrificial layer 116A is deposited on thegate dielectric layer 112 and the remaining firstsacrificial layer 116A in the first region (e.g., the n-type region 50N) and the second region (e.g., the p-type region 50P). As will be subsequently described in greater detail, the secondsacrificial layer 116B will be patterned to remove it and the firstsacrificial layer 116A from in the first region (e.g., the n-type region 50N) while leaving the secondsacrificial layer 116B and the firstsacrificial layer 116A in the second region (e.g., the p-type region 50P). Specifically, the secondsacrificial layer 116B is used to protect thegate dielectric layer 112 fromfirst mask layer 118A formed in the first and second regions by not allowing thefirst mask layer 118A to be formed directly on thegate dielectric layer 112. The secondsacrificial layer 116B includes any acceptable material that can be formed on and removed from thegate dielectric layer 112 without damaging thegate dielectric layer 112, and may be deposited using any acceptable deposition process. For example, the secondsacrificial layer 116B is formed of TiN, WCN, WCl5, TaCl5, SnCl4, combinations thereof, or the like, which may be deposited by ALD, CVD, PVD, or the like. In some embodiments, the secondsacrificial layer 116B is formed of a different material than the firstsacrificial layer 116A. Although the secondsacrificial layer 116B is shown as being single layered, the secondsacrificial layer 116B can be multilayered. - In some embodiments, the second
sacrificial layer 116B is formed of a same material as the firstsacrificial layer 116A and there is no visible interface between thelayers sacrificial layer 116B is omitted and the firstsacrificial layer 116A is not patterned as illustrated inFIGS. 16A and 16B such that the firstsacrificial layer 116A protects thedielectric layer 112 from thefirst mask layer 118A. - In
FIGS. 18A and 18B and step 210 of themethod 200, thefirst mask layer 118A is formed in thesecond recesses 110 over the secondsacrificial layer 116B in the first andsecond regions first mask layer 118A may be deposited by spin-on-coating or the like. Thefirst mask layer 118A may include a polymer material, such as poly(methyl)acrylate, poly(maleimide), novolacs, poly(ether)s, combinations thereof, or the like. In some embodiments, thefirst mask layer 118A may be a bottom anti-reflective coating (BARC) material. - As illustrated in
FIGS. 18A and 18B , thefirst mask layer 118A is patterned to remove thefirst mask layer 118A from therecesses 110 in thefirst region 50N. Thefirst mask layer 118A may be removed by plasma ashing, an etching process such as an isotropic or an anisotropic etching process, or the like. After patterning thefirst mask layer 118A, the first and secondsacrificial layers first region 50N using thefirst mask layer 118A as a mask. The removal may be by acceptable photolithography and etching techniques. The etching may include any acceptable etch process, such as a RIE, NBE, a wet etch, the like, or a combination thereof. The etching may be anisotropic. - In some embodiments, a single etch is performed to remove the portions of the first and second
sacrificial layers sacrificial layers sacrificial layers sacrificial layers sacrificial layers - In
FIGS. 19A and 19B , thefirst mask layer 118A is patterned to remove thefirst mask layer 118A from therecesses 110 in thesecond region 50P. Thefirst mask layer 118A may be removed by plasma ashing, an etching process such as an isotropic or an anisotropic etching process, or the like. After removing thefirst mask layer 118A from therecesses 110 in thesecond region 50P, the secondsacrificial layer 116B is removed from thesecond region 50P. The removal may be by acceptable photolithography and etching techniques. The etching may include any acceptable etch process, such as a RIE, NBE, the like, or a combination thereof. The etching may be anisotropic. - In some embodiments, a single etch is performed to remove the second
sacrificial layers 116B. The single etch may be selective to the materials of the secondsacrificial layer 116B (e.g., selectively etches the materials of the secondsacrificial layer 116B at a faster rate than the material(s) of thegate dielectric layer 112 and/or the firstsacrificial layer 116A). In some embodiments, multiple etch steps/processes are performed to remove the secondsacrificial layer 116B. - As illustrated in
FIGS. 19A and 19B , the removal the secondsacrificial layer 116B removes outer portions of the secondsacrificial layer 116B to expose portions of thegate dielectric layer 112 but leaves the firstsacrificial layer 116A between vertically adjacent ones of thenanostructures 66 and extending between thenanostructures 66 and thefins 62 in both thesecond region 50P. This removal of outer portions of the secondsacrificial layer 116B while leaving inner portions may be referred to as a trimming process. - In
FIGS. 20A and 20B and step 214 of themethod 200, a first workfunction tuning layer 114A is deposited on thegate dielectric layer 112 in the first region (e.g., the n-type region 50N) and on thegate dielectric layer 112 and the firstsacrificial layer 116A in the second region (e.g., the p-type region 50P). As will be subsequently described in greater detail, the first workfunction tuning layer 114A will be patterned to remove portions of the first workfunction tuning layer 114A in the second region (e.g., the p-type region 50P) while leaving portions of the first workfunction tuning layer 114A in the first region (e.g., the n-type region 50N). The first workfunction tuning layer 114A may be referred to as an “n-type work function tuning layer” when it is removed from the second region (e.g., the p-type region 50P). The first workfunction tuning layer 114A includes any acceptable material to tune a work function of a device to a desired amount given the application of the device to be formed, and may be deposited using any acceptable deposition process. For example, when the first workfunction tuning layer 114A is a n-type work function tuning layer, it may be formed of a n-type work function metal (NWFM) such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), TiAlC:N, titanium aluminum nitride (TiAlN), tantalum silicon aluminum (TaSiAl), WCl5, SnCl4, NbCl5, MoCl4, combinations thereof, or the like, which may be deposited by ALD, CVD, PVD, or the like. Although the first workfunction tuning layer 114A is shown as being single layered, the first workfunction tuning layer 114A can be multilayered. For example, the first workfunction tuning layer 114A can include a layer of TiAlN and a layer of TiAlC. - The first work
function tuning layer 114A is formed to a thickness that does not cause merging of the portions of the first workfunction tuning layer 114A between thesecond nanostructures 66 in the first region (e.g., the n-type region 50N). As described in more detail below, the ALD process used to form the first workfunction tuning layer 114A allows for a thinner first workfunction tuning layer 114A (that does not merge betweensecond nanostructures 66 in the illustrated cross-section in thefirst region 50N) while also having the desired effective work function value. The first workfunction tuning layer 114A cannot merge between thesecond nanostructures 66 in the second region (e.g., the p-type region 50P) in the illustrated cross-section due to the remaining portions of the firstsacrificial layer 116A in the second region. By not depositing the first workfunction tuning layer 114A between thesecond nanostructures 66 in the second region (e.g., the p-type region 50P), manufacturing ease can be improved, particularly in advanced semiconductor nodes with small feature sizes, as work function tuning layer materials can be difficult to remove from small spaces. In some embodiments, the first workfunction tuning layer 114A is formed to a thickness in a range from 5 Å to 120 Å, such as in a range from 20 Å to 80 Å. - In some embodiments, the first work
function tuning layer 114A is formed of titanium aluminum carbide, which is deposited by an ALD process. Specifically, the first workfunction tuning layer 114A may be formed by placing thesubstrate 50 in a deposition chamber and cyclically dispensing multiple source precursors into the deposition chamber. A first pulse of an ALD cycle is performed by dispensing a titanium source precursor into the deposition chamber. Acceptable titanium source precursors include titanium chloride (TiCl4) or the like. The first pulse can be performed at a temperature in the range of 100° C. to 600° C. and at a pressure in the range of 1 torr to 100 torr, e.g., by maintaining the deposition chamber at such a temperature and pressure. The first pulse can be performed for a duration in the range of 0.5 seconds to 20 seconds, e.g., by keeping the titanium source precursor in the deposition chamber for such a duration. The titanium source precursor is then purged from the deposition chamber, such as by an acceptable vacuuming process and/or by flowing an inert gas (sometimes called a carrier gas) into the deposition chamber. A second pulse of the ALD cycle is performed by dispensing an aluminum source precursor into the deposition chamber. Acceptable aluminum source precursors include triethylaluminium (TEA) (Al2(C2H5)6) and the like. The second pulse can be performed at a temperature in the range of 100° C. to 600° C. and at a pressure in the range of 1 torr to 100 torr, e.g., by maintaining the deposition chamber at such a temperature and pressure. The second pulse can be performed for a duration in the range of 0.5 seconds to 20 seconds, e.g., by keeping the aluminum source precursor in the deposition chamber for such a duration. The aluminum source precursor is then purged from the deposition chamber, such as by an acceptable vacuuming process and/or by flowing an inert gas into the deposition chamber. Performing either of the ALD pulses at a temperature higher than 600° C. may negatively impact the uniformity of the deposition and have inconsistent concentration of materials in the deposited layer. Performing either of the ALD pulses at a temperature less than 100° C. may negatively impact throughput and/or productivity of the manufacturing process and may lead to a higher cost of manufacturing. Each ALD cycle results in the deposition of an atomic layer (sometimes called a monolayer) of titanium aluminum carbide. The ALD cycles are repeated until the first workfunction tuning layer 114A has a desired thickness (previously described). The ALD cycles can be repeated from 1 to 10 times. Performing the ALD process with parameters in these ranges allows the first workfunction tuning layer 114A to be formed to a desired thickness (previously described), quality, and composition. Performing the ALD process with parameters outside of these ranges may not allow the first workfunction tuning layer 114A to be formed to the desired thickness, quality, or composition. - The above-described ALD process for forming the first work
function tuning layer 114A has the same number of titanium pulses as aluminum pulses in each ALD cycle. In some embodiments, there are more aluminum pulses than titanium pulses per ALD cycle. For example, each ALD cycle could include one titanium pulse and two aluminum pulses. As another example, each ALD cycle could include two titanium pulse and three aluminum pulses. By ensuring that there are at least as many aluminum pulses as titanium pulses in each ALD cycle, the first work function layer has a higher aluminum concentration. In some embodiments, the atomic percentage (at %) of aluminum in the first workfunction tuning layer 114A is in a range from 3% to 80%, such as in a range from 20% to 40%. In some embodiments, the first workfunction tuning layer 114A has a gradient metal concentration with a higher concentration of aluminum at an inner portion near thesecond nanostructures 66 and a lower concentration at an outer portion away from thesecond nanostructures 66. In some embodiments, the disclosed method of forming the first workfunction tuning layer 114A has improved the effective work function by 10% to 15%. - In some embodiments, the ALD process for forming the first work
function tuning layer 114A includes flowing a carrier gas from a port on the bottom of the deposition chamber (e.g., below or on the back side of the substrate 50) whereas the titanium and aluminum precursors described above are flowed into one or more ports on the top of the deposition chamber (e.g., above or on the front side of the substrate 50). In some embodiments, the carrier gas flowed into the bottom of the deposition chamber is N2 or the like and at a flow rate in a range from 2 sccm to 100 sccm. In some embodiments, the carrier flow is a pulse performed at the end of each ALD cycle. In some embodiments, the carrier flow is a pulse performed after each titanium or aluminum precursor pulse in each ALD cycle. By including this back side carrier flow in the ALD process, the uniformity of the deposition thickness of the first workfunction tuning layer 114A is improved by 23% as compared to not including the back side carrier flow. - Further in
FIGS. 20A and 20B and step 214 of themethod 200, aglue layer 114B is formed on the first workfunction tuning layer 114A in the first region (e.g., the n-type region 50N) and the second region (e.g., the p-type region 50P). As illustrated inFIG. 20A , theglue layer 114B merges between adjacentsecond nanostructures 66 in thefirst region 50N in the illustrated cross-section. In some embodiments, theglue layer 114B is formed to a thickness in a range from 10 nm to 50 nm. Theglue layer 114B includes any acceptable material to promote adhesion and prevent diffusion. For example, theglue layer 114B may be formed of a metal or metal nitride such as titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, silicon-doped tantalum aluminide, or the like, which may be deposited by ALD, CVD, PVD, or the like. - In some embodiments, the
glue layer 114B is formed by a similar ALD process with titanium precursors, such as TiCl4 or the like, tantalum precursors, such as pentakis(dimethylamido)tantalum (PDMAT) (C10H30N5Ta), tantalum chloride (TaCl5), or the like, and/or nitrogen precursors such as NH3, or the like. The titanium or tantalum precursors may be flowed into the deposition chamber at flow rates in a range from 50 sccm to 100 sccm. The nitrogen precursors may be flowed into the deposition chamber at flow rates in a range from 50 sccm to 50,000 sccm. Performing the ALD process at flow rates higher than the ranges may negatively impact the uniformity of the deposition and result in waste of the precursor. Performing the ALD process at flow rates less than the ranges may negatively impact throughput and/or productivity of the manufacturing process and may lead to a lower concentration of material in the deposited layer. In some embodiments, the ALD process can be performed at a temperature in the range of 100° C. to 600° C. and at a pressure in a range from 0.0001 torr to 1 torr. Performing the ALD process at a temperature higher than 600° C. may negatively impact the uniformity of the deposition and have inconsistent concentration of materials in the deposited layer. Performing the ALD process at a temperature less than 100° C. may negatively impact throughput and/or productivity of the manufacturing process and may lead to a higher cost of manufacturing. - In
FIGS. 21A and 21B and step 216 of themethod 200, asecond mask layer 118B is formed in thesecond recesses 110 over theglue layer 114B in the first andsecond regions second mask layer 118B may be similar to thefirst mask layer 118A described above and the description is not repeated herein. - As illustrated in
FIGS. 21A and 21B , thesecond mask layer 118B is patterned to remove thesecond mask layer 118B from therecesses 110 in thesecond region 50P. Thesecond mask layer 118B may be removed by plasma ashing, an etching process such as an isotropic or an anisotropic etching process, or the like. After patterning thesecond mask layer 118B, the first workfunction tuning layer 114A, theglue layer 114B, and remaining portions of the firstsacrificial layer 116A are removed from thesecond region 50P using thesecond mask layer 118B as a mask. Removing the first workfunction tuning layer 114A, theglue layer 114B, and remaining portions of the firstsacrificial layer 116A from the second region (e.g., the p-type region 50P) expands therecesses 110 in the second region to re-expose thegate dielectric layer 112 in the second region (e.g., the p-type region 50P). The removal may be by acceptable photolithography and etching techniques. The etching may include any acceptable etch process, such as a RIE, NBE, the like, a wet etch using for example, ammonium hydroxide (NH4OH), dilute hydrofluoric (dHF) acid, the like, or a combination thereof. The etching may be isotropic. - In some embodiments, a single etch is performed to remove the first work
function tuning layer 114A, theglue layer 114B, and remaining portions of the firstsacrificial layer 116A. The single etch may be selective to the materials of the first workfunction tuning layer 114A, theglue layer 114B, and remaining portions of the firstsacrificial layer 116A (e.g., selectively etches the materials of the first workfunction tuning layer 114A, theglue layer 114B, and remaining portions of the firstsacrificial layer 116A at a faster rate than the material(s) of the gate dielectric layer 112). In some embodiments, multiple etch steps/processes are performed to remove the first workfunction tuning layer 114A, theglue layer 114B, and remaining portions of the firstsacrificial layer 116A. As discussed before, the remaining portions of the firstsacrificial layer 116A are easier to remove from between thesecond nanostructures 66 than the work function tuning layers, and thus, the disclosed method provides better control for tuning the threshold voltage of the devices. - In
FIGS. 22A and 22B , thesecond mask layer 118B is patterned to remove thesecond mask layer 118B from therecesses 110 in thefirst region 50N. Thesecond mask layer 118B may be removed by plasma ashing, an etching process such as an isotropic or an anisotropic etching process, or the like. - After removing the
second mask layer 118B from therecesses 110 in thesecond region 50N, inFIGS. 22A and 22B and step 218 of themethod 200, a second workfunction tuning layers glue layer 114B in the first region (e.g., the n-type region 50N) and on thegate dielectric layer 112 in the second region (e.g., the p-type region 50P). As will be subsequently described in greater detail, p-type devices will be formed having the second workfunction tuning layers type region 50P), and n-type devices will be formed having the first workfunction tuning layer 114A, theglue layer 114B, and the second workfunction tuning layers type region 50N). The second workfunction tuning layers type region 50P). The second workfunction tuning layers function tuning layers function tuning layers glue layer 114B and the description is not repeated herein. Although the second workfunction tuning layers function tuning layers - The second work
function tuning layers function tuning layer second nanostructures 66 in the second region (e.g., the p-type region 50P). In some embodiments, the second workfunction tuning layers function tuning layer 114C to a thickness of less than 20 Å may not result in merging of portions of the second workfunction tuning layers function tuning layer - The material of the first work
function tuning layer 114A is different from the material of the second workfunction tuning layers function tuning layer 114A can be formed of a n-type work function metal (NWFM) and the second workfunction tuning layers - In
FIGS. 23A and 23B and step 220 of themethod 200, afill layer 114E is deposited on the second workfunction tuning layer 114D. After formation is complete, thegate electrode layer 114 includes the first workfunction tuning layer 114A, theglue layer 114B, the second workfunction tuning layers fill layer 114E. - The
fill layer 114E includes any acceptable material of a low resistance. For example, thefill layer 114E may be formed of a metal such as tungsten, aluminum, cobalt, ruthenium, combinations thereof or the like, which may be deposited by ALD, CVD, PVD, or the like. Thefill layer 114E fills the remaining portions of therecesses 110. As illustrated in the cross-sections inFIGS. 23A and 23B , thefill layer 114E does not extend between adjacentsecond nanostructures 66 in either thefirst region 50N or thesecond region 50P as the area between adjacentsecond nanostructures 66 in both regions has already been filled by other layers. - Although the
glue layer 114B is used promote adhesion and prevent diffusion of the first workfunction tuning layer 114A during processing, it may not significantly affect the electrical characteristics of the resulting devices, and may be left in the portions of thegate electrode layer 114 in the first region (e.g., the n-type region 50N). Theglue layer 114B is disposed between and physically separates the portions of the first workfunction tuning layer 114A and the second workfunction tuning layer 114C in the first region (e.g., the n-type region 50N). Conversely, the second region (e.g., the p-type region 50P) is free of the first workfunction tuning layer 114A and theglue layer 114B, such that the second workfunction tuning layer 114C and thegate dielectric layer 112 in the second region (e.g., the p-type region 50P) are not separated by a glue layer, and may be in physical contact. -
FIGS. 24A and 24B illustrate an embodiment that includes aprotective layer 114F between the first workfunction tuning layer 114A and theglue layer 114B. Theprotective layer 114F is formed of a material that is resistant to oxidation and prevents diffusion of the first workfunction tuning layer 114A, and thus, inhibits the modification of the first workfunction tuning layer 114A by subsequent processing. - In some embodiments, the
protective layer 114F is formed of amorphous silicon, tantalum nitride, titanium nitride, the like, or a combination thereof which may be deposited by CVD, ALD, or the like. Although theprotective layer 114F is shown as being single layered, theprotective layer 114F can be multilayered. For example, theprotective layer 114F can include a layer of amorphous silicon and a layer of titanium nitride. In some embodiments, theprotective layer 114F is formed to a thickness in a range from 0.1 nm to 10 nm. - In
FIGS. 25A and 25B , a removal process is performed to remove the excess portions of the materials of thegate dielectric layer 112 and thegate electrode layer 114, which excess portions are over the top surfaces of thefirst ILD 104 and thegate spacers 90, thereby forminggate dielectrics 122 andgate electrodes 124. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. Thegate dielectric layer 112, when planarized, has portions left in the recesses 110 (thus forming the gate dielectrics 122). Thegate electrode layer 114, when planarized, has portions left in the recesses 110 (thus forming the gate electrodes 124). The top surfaces of thegate spacers 90; theCESL 102; thefirst ILD 104; the gate dielectrics 122 (e.g., theinterfacial layers 112A and the high-k dielectric layers 112B, seeFIGS. 23A-24B ); and the gate electrodes 124 (e.g., the first workfunction tuning layer 114A, theglue layer 114B, the second workfunction tuning layers protective layer 114F, and thefill layer 114E, seeFIGS. 23A-24B ) are coplanar (within process variations). Thegate dielectrics 122 and thegate electrodes 124 form replacement gates of the resulting nano-FETs. Each respective pair of agate dielectric 122 and agate electrode 124 may be collectively referred to as a “gate structure.” The gate structures each extend along top surfaces, sidewalls, and bottom surfaces of achannel region 68 of thesecond nanostructures 66. - In
FIGS. 26A and 26B , asecond ILD 134 is deposited over thegate spacers 90, theCESL 102, thefirst ILD 104, thegate dielectrics 122, and thegate electrodes 124. In some embodiments, thesecond ILD 134 is a flowable film formed by a flowable CVD method. In some embodiments, thesecond ILD 134 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, which may be deposited by any suitable method, such as CVD, PECVD, or the like. - In some embodiments, an etch stop layer (ESL) 132 is formed between the
second ILD 134 and thegate spacers 90, theCESL 102, thefirst ILD 104, thegate dielectrics 122, and thegate electrodes 124. TheESL 132 may include a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etching selectivity from the etching of thesecond ILD 134. - In
FIGS. 27A and 27B ,gate contacts 142 and source/drain contacts 144 are formed to contact, respectively, thegate electrodes 124 and the epitaxial source/drain regions 98. Thegate contacts 142 are physically and electrically coupled to thegate electrodes 124. The source/drain contacts 144 are physically and electrically coupled to the epitaxial source/drain regions 98. - As an example to form the
gate contacts 142 and the source/drain contacts 144, openings for thegate contacts 142 are formed through thesecond ILD 134 and theESL 132, and openings for the source/drain contacts 144 are formed through thesecond ILD 134, theESL 132, thefirst ILD 104, and theCESL 102. The openings may be formed using acceptable photolithography and etching techniques. A liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of thesecond ILD 134. The remaining liner and conductive material form thegate contacts 142 and the source/drain contacts 144 in the openings. Thegate contacts 142 and the source/drain contacts 144 may be formed in distinct processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of thegate contacts 142 and the source/drain contacts 144 may be formed in different cross-sections, which may avoid shorting of the contacts. - Optionally, metal-
semiconductor alloy regions 146 are formed at the interfaces between the epitaxial source/drain regions 98 and the source/drain contacts 144. The metal-semiconductor alloy regions 146 can be silicide regions formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed of a metal germanide (e.g. titanium germanide, cobalt germanide, nickel germanide, etc.), silicon-germanide regions formed of both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 146 can be formed before the material(s) of the source/drain contacts 144 by depositing a metal in the openings for the source/drain contacts 144 and then performing a thermal anneal process. The metal can be any metal capable of reacting with the semiconductor materials (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source/drain regions 98 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. After the thermal anneal process, a cleaning process, such as a wet clean, may be performed to remove any residual metal from the openings for the source/drain contacts 144, such as from surfaces of the metal-semiconductor alloy regions 146. The material(s) of the source/drain contacts 144 can then be formed on the metal-semiconductor alloy regions 146. - Embodiments may achieve advantages. In some embodiments, the work function tuning layers for the n-type devices are formed before the work function tuning layers for the p-type devices to allow more control of the threshold voltages of the resulting devices. The method of forming the work function tuning layers for the n-type devices before the work function tuning layers for the p-type devices includes the formation and patterning of sacrificial layers to prevent the work function tuning layers for the n-type devices from being formed between the nanostructures of the p-type devices. This helps to prevent the work function tuning layers from remaining on the p-type devices which could degrade the performance of the p-type devices. In some embodiments, a protection layer is formed between the work function tuning layer and a glue layer to inhibit (e.g., substantially prevents or at least reduces) diffusion of the work function tuning layer. The threshold voltages of the resulting devices may thus be more accurately tuned.
- An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region. The device also includes a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region. The device also includes a gate dielectric layer wrapping around each of the first and second sets of nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, the first work function tuning layer including an n-type work function metal. The device also includes a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures. The device also includes a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal. The device also includes a fill layer on the second work function tuning layer.
- Embodiments may include one or more of the following features. The device where the glue layer includes titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, silicon-doped tantalum aluminide. The device further including a protective layer between the first work function tuning layer and the glue layer on the first set of nanostructures, the protective layer wrapping around each of the first set of nanostructures. The protective layer includes amorphous silicon. The glue layer separates and fills an area between respective portions of the protective layer on adjacent nanostructures of the first set of nanostructures. The glue layer separates and fills an area between respective portions of the first work function tuning layer on adjacent nanostructures of the first set of nanostructures. The second work function tuning layer separates and fills an area between respective portions of the gate dielectric layer on adjacent nanostructures of the second set of nanostructures. The fill layer does not extend between adjacent nanostructures of the second set of nanostructures.
- An embodiment includes a method including forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. The method also includes forming a gate dielectric layer having a first portion and a second portion, the first portion deposited on the first channel region, the second portion deposited on the second channel region. The method also includes forming a first work function tuning layer on the first portion of the gate dielectric layer and the second portion of the gate dielectric layer. The method also includes forming a glue layer on the first work function tuning layer. The method also includes removing the glue layer and the first work function tuning layer from the second portion of the gate dielectric layer. The method also includes forming a second work function tuning layer on the remaining glue layer and the second portion of the gate dielectric layer. The method also includes forming a fill layer on the second work function tuning layer.
- Embodiments may include one or more of the following features. The method where the first work function tuning layer includes an n-type work function metal, and where the second work function tuning layer including an p-type work function metal. The method further including before forming the first work function tuning layer, forming a sacrificial layer on the second portion of the gate dielectric layer between adjacent nanostructures of the second set of nanostructures, the first work function layer being formed on the sacrificial layer and the second portion of the gate dielectric layer. Forming the sacrificial layer on the second portion of the gate dielectric layer between adjacent nanostructures of the second set of nanostructures further includes forming a first sacrificial layer on the first portion and the second portion of the gate dielectric layer, trimming the first sacrificial layer to expose portions of the first portion and the second portion of the gate dielectric layer, where after the trimming, portions of the first sacrificial layer remain between adjacent nanostructures of both the first and second sets of nanostructures, forming a second sacrificial layer on the exposed portions of the first portion and the second portion of the gate dielectric layer and the remaining portions of the first sacrificial layer, removing the first and second sacrificial layers from the first set of nanostructures to expose the first portion of the gate dielectric layer, and trimming the second sacrificial layer to expose portions of the second portion of the gate dielectric layer, where after the trimming, portions of the first sacrificial layer remain between adjacent nanostructures of the second set of nanostructures. Forming the first work function tuning layer includes depositing titanium aluminum carbide by an ALD process, the ALD process performed with titanium chloride and triethylaluminium, the ALD process performed at a temperature in a range of 100° C. to 600° C., the ALD process performed at a pressure in a range of 1 torr to 100 torr. The ALD process includes the same number of pulses of titanium chloride and triethylaluminium in each ALD cycle. The ALD process includes more pulses of triethylaluminium than titanium chloride in each ALD cycle. The method further including forming a protective layer on the first work function tuning layer on the first set of nanostructures, the glue layer being formed on the protective layer on the first set of nanostructures. The protective layer includes amorphous silicon.
- An embodiment includes a method including forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures including a first channel region and the second set of nanostructures including a second channel region. The method also includes forming a gate dielectric layer on the first channel region. The method also includes forming a second gate dielectric layer on the second channel region. The method also includes forming a sacrificial layer between the second set of nanostructures. The method also includes forming a n-type work function tuning layer on the first gate dielectric layer, the second gate dielectric layer, and the sacrificial layer, the n-type work function tuning layer wrapping around each of the first set of nanostructures. The method also includes forming a glue layer on the n-type work function tuning layer, the glue layer wrapping around each of the first set of nanostructures. The method also includes removing the glue layer, the n-type work function tuning layer, and the sacrificial layer from the second gate dielectric layer. The method also includes forming a p-type work function tuning layer on the glue layer on the first set of nanostructures and the second gate dielectric layer. The method also includes forming a fill layer on the p-type work function tuning layer.
- Embodiments may include one or more of the following features. The method where forming a sacrificial layer between the second set of nanostructures further includes forming a first sacrificial layer on the first and second gate dielectric layers, trimming the first sacrificial layer to expose portions of the first and second gate dielectric layers, where after the trimming, portions of the first sacrificial layer remain between adjacent nanostructures of both the first and second sets of nanostructures, forming a second sacrificial layer on the exposed portions of the first and second gate dielectric layers and the remaining portions of the first sacrificial layer, removing the first and second sacrificial layers from the first set of nanostructures to expose the first gate dielectric layer, and trimming the second sacrificial layer to expose portions of the second gate dielectric layer, where after the trimming, portions of the first sacrificial layer remain between adjacent nanostructures of the second set of nanostructures. Forming the n-type work function tuning layer includes depositing titanium aluminum carbide by an ALD process, the ALD process includes performing multiple ALD cycles, where each ALD cycle includes pulses of titanium chloride and triethylaluminium, the ALD process performed at a temperature in a range of 100° C. to 600° C., the ALD process performed at a pressure in a range of 1 torr to 100 torr, where the ALD process includes more pulses of triethylaluminium than titanium chloride in each ALD cycle.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A device comprising:
a first set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region;
a second set of nanostructures on the substrate, the second set of nanostructures comprising a second channel region;
a gate dielectric layer wrapping around each of the first and second sets of nanostructures;
a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, the first work function tuning layer comprising an n-type work function metal;
a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures;
a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, the second work function tuning layer comprising a p-type work function metal, the p-type work function metal different from the n-type work function metal; and
a fill layer on the second work function tuning layer.
2. The device of claim 1 , wherein the glue layer comprises titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, silicon-doped tantalum aluminide.
3. The device of claim 1 further comprising:
a protective layer between the first work function tuning layer and the glue layer on the first set of nanostructures, the protective layer wrapping around each of the first set of nanostructures.
4. The device of claim 3 , wherein the protective layer comprises amorphous silicon.
5. The device of claim 4 , wherein the glue layer separates and fills an area between respective portions of the protective layer on adjacent nanostructures of the first set of nanostructures.
6. The device of claim 1 , wherein the glue layer separates and fills an area between respective portions of the first work function tuning layer on adjacent nanostructures of the first set of nanostructures.
7. The device of claim 1 , wherein the second work function tuning layer separates and fills an area between respective portions of the gate dielectric layer on adjacent nanostructures of the second set of nanostructures.
8. The device of claim 1 , wherein the fill layer does not extend between adjacent nanostructures of the second set of nanostructures.
9. A device comprising:
a first set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region;
a second set of nanostructures on the substrate, the second set of nanostructures comprising a second channel region;
a gate dielectric layer wrapping around each of the first and second sets of nanostructures;
a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures;
a protective layer on the first work function tuning layer, the protective layer wrapping around each of the first set of nanostructures;
a second work function tuning layer over the protective layer of the first set of nanostructures and over the gate dielectric layer of the second set of nanostructures, the second work function tuning layer having a different material composition than the first work function tuning layer; and
a fill layer on the second work function tuning layer.
10. The device of claim 9 , wherein the protective layer comprises amorphous silicon.
11. The device of claim 9 further comprising:
a glue layer between the protective layer and the second work function tuning layer on the first set of nanostructures, the glue layer wrapping around each of the first set of nanostructures.
12. The device of claim 11 , wherein the glue layer comprises titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, silicon-doped tantalum aluminide.
13. The device of claim 11 , wherein the glue layer separates and fills an area between respective portions of the protective layer on adjacent nanostructures of the first set of nanostructures.
14. The device of claim 9 , wherein the second work function tuning layer separates and fills an area between respective portions of the gate dielectric layer on adjacent nanostructures of the second set of nanostructures.
15. The device of claim 9 , wherein the fill layer does not extend between adjacent nanostructures of the second set of nanostructures.
16. The device of claim 9 , wherein the fill layer does not extend between adjacent nanostructures of the first set of nanostructures.
17. A device comprising:
a first set of nanostructures on a substrate;
a second set of nanostructures on the substrate;
a gate dielectric layer wrapping around each of the first and second sets of nanostructures;
a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, the first work function tuning layer comprising an n-type work function metal;
a glue layer on the first work function tuning layer;
a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures; and
a fill layer on the second work function tuning layer, wherein the fill layer does not extend between adjacent nanostructures of the second set of nanostructures, and wherein the fill layer does not extend between adjacent nanostructures of the first set of nanostructures.
18. The device of claim 17 , wherein the first work function tuning layer comprises an n-type work function metal, the second work function tuning layer comprises a p-type work function metal, and the p-type work function metal is different from the n-type work function metal.
19. The device of claim 17 further comprising:
a amorphous silicon layer between the first work function tuning layer and the glue layer on the first set of nanostructures, the amorphous silicon layer wrapping around each of the first set of nanostructures.
20. The device of claim 19 , wherein the glue layer comprises titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, silicon-doped tantalum aluminide.
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US9385197B2 (en) * | 2014-08-29 | 2016-07-05 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor structure with contact over source/drain structure and method for forming the same |
US10458018B2 (en) * | 2015-06-26 | 2019-10-29 | Asm Ip Holding B.V. | Structures including metal carbide material, devices including the structures, and methods of forming same |
US9570580B1 (en) * | 2015-10-30 | 2017-02-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Replacement gate process for FinFET |
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US10002791B1 (en) * | 2017-04-06 | 2018-06-19 | International Business Machines Corporation | Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS |
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US10529815B2 (en) | 2017-10-31 | 2020-01-07 | International Business Machines Corporation | Conformal replacement gate electrode for short channel devices |
US10431696B2 (en) * | 2017-11-08 | 2019-10-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure with nanowire |
US10930755B2 (en) * | 2018-11-26 | 2021-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned inner spacer on gate-all-around structure and methods of forming the same |
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US10720431B1 (en) | 2019-01-25 | 2020-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of fabricating semiconductor devices having gate-all-around structure with oxygen blocking layers |
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- 2022-01-30 CN CN202210114070.4A patent/CN114975275A/en active Pending
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TW202234524A (en) | 2022-09-01 |
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