CN109148258A - 形成氧化层的方法 - Google Patents

形成氧化层的方法 Download PDF

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CN109148258A
CN109148258A CN201710455943.7A CN201710455943A CN109148258A CN 109148258 A CN109148258 A CN 109148258A CN 201710455943 A CN201710455943 A CN 201710455943A CN 109148258 A CN109148258 A CN 109148258A
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manufacture craft
oxide layer
substrate
oxygen
forming oxide
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CN109148258B (zh
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黄承栩
李瑞珉
张景翔
陈意维
刘玮鑫
邹世芳
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种形成氧化层的方法,其包含有下述步骤。首先,提供一基底。接着,处理基底的一表面,以形成一含氧离子的表面。接续,形成一旋转涂布介电层于基底的含氧离子的表面上。本发明又提供一种形成一氧化层的方法,包含有下述步骤。首先,提供一基底。接着,以过氧化氢处理基底的一表面或者以含氧气体处理基底的一表面,以形成一含氧离子的表面。接续,形成一旋转涂布介电层于基底的含氧离子的表面上。

Description

形成氧化层的方法
技术领域
本发明涉及一种形成氧化层的方法,尤其是涉及一种以旋转涂布介电质(Spin-OnDielectric,SOD)制作工艺形成氧化层的方法。
背景技术
现今介电材料的沉积方式大多以旋转涂布介电质(Spin-On Dielectric,SOD)制作工艺,或者化学气相沉积法(Chemical vapor deposition,CVD)而为之。采用旋转涂布介电质制作工艺最重要的考虑因素为,只要适当地调整、改变溶剂(DBE)系统,旋转涂布介电质制作工艺即可轻易地将流体状的介电质材料涂布至具有孔洞的基材内,此乃旋转涂布介电质制作工艺的独特优势,因此现阶段半导体业界乃以旋转涂布介电质制作工艺为应用主流。
一般而言,通常在半导体的结构上多将许多不同大小、规格、尺寸的沟槽(Trench)设计于一基材的上方,当以旋转涂布介电质制作工艺涂布介电质材料于该基材上之后,该介电质材料势必覆盖满该基材表面的不规则凹凸起伏。当旋转涂布介电质制作工艺完成后,该介电质成型膜中常易造成孔洞(Void)缺陷存在于沟槽偏下方之处。
因此,如何消除成型膜孔洞存在的缺陷,这是本领域具有通常知识者努力的目标。
发明内容
本发明提出一种形成氧化层的方法,其先形成一含氧离子的表面,再形成氧化层于此表面上,以改善所形成的氧化层的填洞品质。
本发明提供一种形成氧化层的方法,包含有下述步骤。首先,提供一基底。接着,处理基底的一表面,以形成一含氧离子的表面。接续,形成一旋转涂布介电层于基底的含氧离子的表面上。
本发明提供一种形成氧化层的方法,包含有下述步骤。首先,提供一基底。接着,以过氧化氢处理基底的一表面,以形成一含氧离子的表面。接续,形成一旋转涂布介电层于基底的含氧离子的表面上。
本发明提供一种形成氧化层的方法,包含有下述步骤。首先,提供一基底。接着,以含氧气体处理基底的一表面,以形成一含氧离子的表面。接续,形成一旋转涂布介电层于基底的含氧离子的表面上。
基于上述,本发明提出一种形成氧化层的方法,其在形成氧化层之前先以干式或湿式的处理制作工艺处理基底的一表面,以形成一含氧离子的表面,而后形成氧化层于此表面上。如此一来,本发明的用以转化成氧化层的流体介电质可完全转换为此氧化层,特别是在凹槽底部的流体介电质可完全转换为此氧化层。因而,能改善氧化层的填洞能力,防止氧化层中具有孔洞以及改善材质均匀度。
附图说明
图1~图5为本发明优选实施例中形成一氧化层的方法的剖面示意图;
图6~图10为本发明优选实施例中动态随机存取存储器元件的剖面示意图。
主要元件符号说明
1、1’:氧化衬垫层
2、2’:氮化衬垫层
3、3’:旋转涂布介电层
5、7:氧化硅层
6:氮化硅层
20:埋入式字符线
30、30’:位线栅极
32、32’:位线接触插塞
32a:间隙壁
34:存储节点接触插塞
42:衬垫层
44:旋转涂布介电层
100:基底
110:基材
A1:第一区
A2:第二区
B:第三区
P1:粒子移除制作工艺
P2:前处理制作工艺
P3:旋转涂布制作工艺
P4:退火制作工艺
R1、R2、R3、R4、R5:凹槽
S1、S2、S3:表面
W1、W2、W3:宽度
具体实施方式
图1~图5绘示本发明优选实施例中形成一氧化层的方法的剖面示意图。图1~图5绘示以本发明的形成氧化层的方法,形成隔离各具备凹入式栅极结构的动态随机存取存储器(Dynamic Random Access Memory,DRAM)单元的绝缘结构,但本发明不以此为限。
如图1所示,提供一基材110。基材110例如为一硅基材、一含硅基材、一三五族覆硅基材(例如GaN-on-silicon)、一石墨烯覆硅基材(graphene-on-silicon)或一硅覆绝缘(silicon-on-insulator,SOI)基材等半导体基材。基材110可根据所欲形成的装置功能区分为一第一区A1、一第二区A2以及一第三区B,例如第一区A1及第二区A2为存储器单元区,而第三区B为一周边区,其中周边区中的周边电路用以操作存储器单元区中的存储器单元,但本发明不以此为限。在本实施例中,存储器单元区中具有多个存储器单元,因而形成一凹入式栅极结构的动态随机存取存储器装置,但本发明非限于此。
详细而言,第一区A1的基材110中可包含多个凹槽R1、第二区A2的基材110中可包含多个凹槽R2,而第三区B的基材110中可包含一凹槽R3。本实施例的图1~图5绘示六个凹槽R1、三个凹槽R2以及一个凹槽R3,但凹槽R1/R2/R3个数非限于此。凹槽R1的宽度W1小于凹槽R2的宽度W2,且凹槽R2的宽度W2小于凹槽R3的宽度W3,此些凹槽R1/R2/R3宽度W1/W2/W3是根据各区所欲隔绝的装置尺寸而定,但本发明非限于此。
形成此些凹槽R1/R2/R3的方法,可例如:先依序全面形成多个垫层(未绘示)、蚀刻停止层(未绘示)及硬掩模层(未绘示);图案化硬掩模层(未绘示)、蚀刻停止层(未绘示)及垫层(未绘示)以暴露出部分基材110而定义出凹槽R1/R2/R3位置;蚀刻暴露出的部分基材110而形成凹槽R1/R2/R3;移除图案化的硬掩模层(未绘示)、图案化的蚀刻停止层(未绘示)及图案化的垫层(未绘示)。本发明的形成凹槽R1/R2/R3的方法不限于此。
如图2所示,可选择性覆盖一衬垫层于基材110的一表面S1。在本实施例中,衬垫层可为由下而上堆叠的一氧化衬垫层1’以及一氮化衬垫层2’,但本发明不以此为限。在一实施例中,衬垫层为双层,但在其他实施例中衬垫层可为一层或多于二层。例如,衬垫层可仅为一氧化衬垫层1’或一氮化衬垫层2’。氧化衬垫层1’及氮化衬垫层2’可例如由原子层沉积(atomic layer deposition,ALD)制作工艺形成,但本发明不以此为限。换言之,本实施例中,一基底100可选择性包含基材110、氧化衬垫层1’以及氮化衬垫层2’,且氮化衬垫层2’位于基底100的一表面S2。
在另一实施例中,衬垫层可改为由下而上堆叠的一含碳氮化衬垫层以及一氮氧化衬垫层,但本发明不以此为限。在一实施例中,衬垫层为双层,但在其他实施例中衬垫层可为一层或多于二层。例如,衬垫层可仅为一含碳氮化衬垫层或一氮氧化衬垫层。含碳氮化衬垫层及氮氧化衬垫层可例如由原子层沉积(atomic layer deposition,ALD)制作工艺形成,但本发明不以此为限。因此,基底100可选择性包含基材110、含碳氮化衬垫层以及氮氧化衬垫层,且氮氧化衬垫层位于基底100的表面S2。
如图3所示,可选择性进行一粒子移除制作工艺P1,以移除例如形成凹槽R1/R2/R3等前端制作工艺所残留的粒子。粒子移除制作工艺P1可例如为一高压清洗制作工艺,但本发明不以此为限。
接着,再进行一前处理制作工艺P2,处理基底100的表面S2,以于基底100的表面S2形成一含氧离子的表面。前处理制作工艺P2可包含一湿式前处理制作工艺、一干式前处理制作工艺或一湿式前处理制作工艺及一干式前处理制作工艺。在一实施例中,以一湿式前处理制作工艺处理基底100的表面S2,且在一优选实施例中,湿式前处理制作工艺包含过氧化氢处理剂,如此即可将表面S2形成为一富含氧离子的表面。在另一实施例中,以一干式前处理制作工艺处理基底100的表面S2,且在一优选实施例中,干式前处理制作工艺包含通入含氧气体,以将表面S2形成为一富含氧离子的表面。在一更佳的实施例中,通入含氧气体可包含通入氧气、通入臭氧、或依序或同时通入氧气及臭氧。并且,干式前处理制作工艺较佳的制作工艺温度小于500℃,但本发明不以此为限。以此方法,本发明形成的富含氧离子的表面可使后续涂布于其上的流体介电质完全转换为氧化层,特别是在凹槽底部的流体介电质可完全转换为氧化层。因此,能改善流体介电质的填洞能力,防止氧化层中具有孔洞以及改善氧化层的材质均匀度。
如图4所示,形成一旋转涂布介电层3’于基底100的含氧离子的表面S2上。形成旋转涂布介电层3’的方法可例如:进行一旋转涂布制作工艺P3,而后再进行一退火制作工艺P4。进行旋转涂布制作工艺P3是将流体介电质旋转涂布于基底100上以及凹槽R3中,并填满凹槽R3。之后,进行退火制作工艺P4,以固化流体介电质而形成旋转涂布介电层3’,并致密化旋转涂布介电层3’。在本实施例中,旋转涂布介电层3’即为由旋转涂布形成的氧化层,但本发明不以此为限。当搭配前处理制作工艺P2为一湿式前处理制作工艺,则退火制作工艺的制作工艺温度较佳小于900℃。当搭配前处理制作工艺P2为一干式前处理制作工艺,则退火制作工艺的制作工艺温度较佳小于600℃。
如图5所示,进行一平坦化制作工艺,平坦化旋转涂布介电层3’、氮化衬垫层2’以及氧化衬垫层1’,而形成氧化衬垫层1、氮化衬垫层2以及旋转涂布介电层3。本实施例的氧化衬垫层1、氮化衬垫层2以及旋转涂布介电层3构成一浅沟槽绝缘层,意即区隔具备凹入式栅极结构的动态随机存取存储器(Dynamic Random Access Memory,DRAM)单元的绝缘结构,但本发明不以此为限。在本实施例中,氧化衬垫层1填满第一区A1中的凹槽R1,并覆盖部分第二区A2的凹槽R2及第三区B的凹槽R3。氮化衬垫层2则再填满第二区A2的凹槽R2并覆盖部分第三区B的凹槽R3。旋转涂布介电层3则填满凹槽R3。
图6~图10绘示本发明优选实施例中动态随机存取存储器元件的剖面示意图,其中图6~图10的左图及右图分别为互相垂直方向的剖面示意图。如图6所示,图5的第一区A1的氧化衬垫层1构成此区中的具备凹入式栅极结构的动态随机存取存储器(DynamicRandom Access Memory,DRAM)单元的浅沟槽绝缘层。基底110中可先设置多个埋入式字符线20,并再于基底110上形成凹槽R4,以于后续制作工艺中形成位线接触插塞,而覆盖基底110表面的绝缘材料可例如包含多个氧化硅层5、氮化硅层6以及氧化硅层7等,但本发明不以此为限。
如图7所示,形成一位线栅极30于基底110上,其中位线栅极30较佳设置于基底110上并同时覆盖多个埋设于基底110内的埋入式字符线20。形成位线栅极30的方法可例如全面性堆叠多个材料层于基底110上,其中材料层由下至上可包含一非晶硅层以及一金属堆叠结构,但本发明不以此为限。金属堆叠结构又可包含由下至上堆叠的一钛层、一氮化钛层、一第一氮化钨层以及一钨层等;接着,图案化此些材料层,以形成位线栅极30’,因而在位线栅极30’的底部形成有位线接触插塞32’。再者,可形成间隙壁32a覆盖位线栅极30’的两侧,俾形成位线栅极30。间隙壁32a可例如为一氮化层,但本发明不以此为限。如此一来,即可形成位线栅极30,而其底部具有位线接触插塞32。位线栅极30’与位线接触插塞32’其实是一体成型。
如图8所示,形成存储节点接触插塞34于位线接触插塞32侧边的基底110中。形成存储节点接触插塞34的方法可例如以蚀刻制作工艺在位线接触插塞32侧边的基底110中形成凹槽,再形成存储节点接触插塞34于凹槽中,但本发明不以此为限。
图9~图10绘示以本发明的形成氧化层的方法形成一层间介电层。形成的方法可参照前述的图2~图5。首先,如图9所示,先形成一衬垫层42覆盖基材110、位线栅极30及存储节点接触插塞34。衬垫层42可例如为单层或多层,其可例如为一氧化衬垫层、一氮化衬垫层、一含碳氮化衬垫层、一氮氧化衬垫层以及此些衬垫层的组合。
接着,可进行如图3的粒子移除制作工艺P1,以移除例如位线栅极30之间及存储节点接触插塞34上经前端制作工艺等残留的粒子。粒子移除制作工艺P1可例如为一高压清洗制作工艺,但本发明不以此为限。
之后,再进行如图3之前处理制作工艺P2,处理衬垫层42的一表面S3,以于衬垫层42的表面S3形成一含氧离子的表面。前处理制作工艺P2可包含一湿式前处理制作工艺、一干式前处理制作工艺或一湿式前处理制作工艺及一干式前处理制作工艺。在一实施例中,以一湿式前处理制作工艺处理衬垫层42的表面S3,且在一优选实施例中,湿式前处理制作工艺是包含过氧化氢处理剂,如此即可将表面S3形成为一富含氧离子的表面。在另一实施例中,以一干式前处理制作工艺处理衬垫层42的表面S3,且在一优选实施例中,干式前处理制作工艺包含通入含氧气体,以将表面S3形成为一富含氧离子的表面。在一更佳的实施例中,通入含氧气体可包含通入氧气、通入臭氧、或依序或同时通入氧气及臭氧。并且,干式前处理制作工艺较佳的制作工艺温度小于500℃,但本发明不以此为限。以此方法,本发明形成的富含氧离子的表面可使后续涂布于其上的流体介电质完全转换为氧化层,特别是在凹槽底部的流体介电质可完全转换为氧化层。因此,能改善流体介电质的填洞能力,防止氧化层中具有孔洞以及改善氧化层的材质均匀度。
如图10所示,形成一旋转涂布介电层44于衬垫层42的含氧离子的表面S3上。形成旋转涂布介电层44的方法可例如:进行一旋转涂布制作工艺P3,而后再进行一退火制作工艺P4。进行旋转涂布制作工艺P3是将流体介电质旋转涂布于衬垫层42上以及凹槽R5中,并填满凹槽R5。之后,进行退火制作工艺P4,以固化流体介电质而形成旋转涂布介电层44,并致密化旋转涂布介电层44。在本实施例中,旋转涂布介电层44即为由旋转涂布形成的氧化层,但本发明不以此为限。当搭配前处理制作工艺P2为一湿式前处理制作工艺,则退火制作工艺的制作工艺温度较佳小于900℃。当搭配前处理制作工艺P2为一干式前处理制作工艺,则退火制作工艺的制作工艺温度较佳小于600℃。之后,可进行一平坦化制作工艺,平坦化旋转涂布介电层44至旋转涂布介电层44的顶面与衬垫层42的顶面切齐,但本发明不以此为限。
综上所述,本发明提出一种形成一氧化层的方法,其在形成氧化层之前先以干式或湿式的处理制作工艺处理基底的一表面,以形成一含氧离子的表面,而后形成氧化层于此表面上。如此一来,本发明的用以转化成氧化层的流体介电质可完全转换为此氧化层,特别是在凹槽底部的流体介电质可完全转换为此氧化层。因而,能改善氧化层的填洞能力,防止氧化层中具有孔洞以及改善材质均匀度。
再者,本发明的湿式前处理制作工艺较佳可包含过氧化氢处理剂,而本发明的干式前处理制作工艺较佳可包含通入含氧气体,其中通入的含氧气体更佳可包含氧气、臭氧或二者组合,但本发明不限于此。本发明在处理基底的表面之前,可先选择性进行一粒子移除制作工艺,其中粒子移除制作工艺包含一高压清洗制作工艺,以移除前端制作工艺所残留的粒子。
另外,本发明形成氧化层于含氧离子的表面上的方法可为依序进行一旋转涂布制作工艺以及一退火制作工艺。旋转涂布制作工艺是先将流体介电质旋转涂布于含氧离子的表面上,特别是凹槽的具有含氧离子的表面上。然后,进行退火制作工艺,以固化流体介电质而形成氧化层,并致密化氧化层。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。

Claims (20)

1.一种形成氧化层的方法,包含有:
提供一基底;
处理该基底的一表面,以形成一含氧离子的表面;以及
形成一旋转涂布介电层于该基底的该含氧离子的表面上。
2.如权利要求1所述的形成氧化层的方法,其中以一湿式前处理制作工艺处理该基底的该表面。
3.如权利要求2所述的形成氧化层的方法,其中该湿式前处理制作工艺包含过氧化氢处理剂。
4.如权利要求1所述的形成氧化层的方法,其中以一干式前处理制作工艺处理该基底的该表面。
5.如权利要求4所述的形成氧化层的方法,其中该干式前处理制作工艺包含通入含氧气体。
6.如权利要求5所述的形成氧化层的方法,其中该含氧气体包含氧气或臭氧。
7.如权利要求4所述的形成氧化层的方法,其中该干式前处理制作工艺的制作工艺温度小于500℃。
8.如权利要求1所述的形成氧化层的方法,还包含:
在处理该基底的该表面之前,进行一粒子移除制作工艺。
9.如权利要求8所述的形成氧化层的方法,其中该粒子移除制作工艺包含一高压清洗制作工艺。
10.如权利要求1所述的形成氧化层的方法,其中该氧化层包含一浅沟槽绝缘层或一层间介电层。
11.一种形成氧化层的方法,包含有:
提供一基底;
以过氧化氢处理该基底的一表面,以形成一含氧离子的表面;以及
形成一旋转涂布介电层于该基底的该含氧离子的表面上。
12.如权利要求11所述的形成氧化层的方法,其中形成该旋转涂布介电层的方法包含进行一旋转涂布制作工艺,而后再进行一退火制作工艺。
13.如权利要求12所述的形成氧化层的方法,其中该退火制作工艺的制作工艺温度小于900℃。
14.如权利要求11所述的形成氧化层的方法,其中该基底包含一衬垫层于该表面,因而该含氧离子的表面为该衬垫层的一表面,其中该衬垫层包含氧化衬垫层或/且氮化衬垫层。
15.一种形成氧化层的方法,包含有:
提供一基底;
以含氧气体处理该基底的一表面,以形成一含氧离子的表面;以及
形成一旋转涂布介电层于该基底的该含氧离子的表面上。
16.如权利要求15所述的形成氧化层的方法,其中该含氧气体包含氧气或臭氧。
17.如权利要求15所述的形成氧化层的方法,其中处理该基底的该表面的制作工艺温度小于500℃。
18.如权利要求15所述的形成氧化层的方法,其中形成该旋转涂布介电层的方法包含进行一旋转涂布制作工艺,而后再进行一退火制作工艺。
19.如权利要求18所述的形成氧化层的方法,其中该退火制作工艺的制作工艺温度小于600℃。
20.如权利要求15所述的形成氧化层的方法,其中该基底包含一衬垫层于该表面,因而该含氧离子的表面为该衬垫层的一表面,其中该衬垫层包含含碳氮化衬垫层或/且氮氧化衬垫层。
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CN113471137B (zh) * 2020-03-30 2024-05-07 华邦电子股份有限公司 半导体隔离结构及其形成方法

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