CN109119399A - 包括包含空隙的再分布层焊盘的电子器件 - Google Patents
包括包含空隙的再分布层焊盘的电子器件 Download PDFInfo
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- CN109119399A CN109119399A CN201810650999.2A CN201810650999A CN109119399A CN 109119399 A CN109119399 A CN 109119399A CN 201810650999 A CN201810650999 A CN 201810650999A CN 109119399 A CN109119399 A CN 109119399A
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Abstract
本发明公开了包括包含空隙的再分布层焊盘的电子器件。一种电子器件,包括焊料球、包括开口的电介质层以及包括与焊料球连接的RDL焊盘的再分布层(RDL),该RDL焊盘包括至少一个空隙,该空隙至少部分地设置在RDL焊盘的在电介质层的开口的横向外侧的区域中。
Description
技术领域
本公开涉及电子器件和半导体器件。本公开特别地涉及包括焊料球和与焊料球连接的再分布层焊盘的电子器件,该再分布层焊盘包括用于增加球栅阵列(BGA)封装组件的互连可靠性的应力释放结构。
背景技术
球栅阵列(BGA)是用于永久安装诸如微处理器或其他类型的集成电路的设备的一种类型的半导体芯片封装。作为电子器件的一部分的BGA能够提供比其他封装类型更多的互连引脚,因为原则上电子器件的整个底表面能够用于在其上布置焊料球或焊料凸块。
然而,BGA封装组件可能由于所涉及的材料的热膨胀失配以及还由于来自模块中的组件的机械应力加载而经历热机械应力。热机械应力加载可能导致界面和块体材料的疲劳。使用扇出晶圆级封装(例如eWLB(嵌入式晶圆级球栅阵列))技术平台制造的组装BGA封装中的疲劳相关观察的示例是焊料球疲劳、凸块下金属化(UBM)疲劳和再分布层(RDL)疲劳。
发明内容
根据本公开的第一方面,一种电子器件包括焊料球、包括开口的电介质层以及包括与焊料球连接的RDL焊盘的再分布层(RDL),RDL焊盘包括在至少一个空隙,该空隙至少部分地设置在RDL焊盘的在电介质层的开口的横向外侧的区域中。
根据本公开的第二方面,一种电子器件包括焊料球和与焊料球连接的金属层焊盘,该金属层焊盘包括至少一个空隙,空隙被形成为槽,槽包括沿着圆弧区段布置的细长形式。
根据本公开的第三方面,一种半导体器件包括:衬底;设置在衬底上的第一电介质层;设置在第一电介质层上的第一金属层焊盘;设置在第一金属层焊盘上且在第一电介质层上的第二电介质层,第二电介质层包括开口;在第二电介质层的开口中设置第一金属层焊盘上的第二金属层焊盘;以及设置在第二金属层焊盘上的焊料球,其中第一金属层焊盘包括至少一个空隙,空隙至少部分地设置在第二金属层焊盘的横向外侧,并且空隙形成为槽,槽包括沿着圆弧区段布置的细长形式。
本领域技术人员在阅读下面的详细描述时以及在考虑附图时认识到附加特征和优点。
附图说明
附图被包含以提供对示例的进一步理解并且被并入本说明书中且构成本说明书的一部分。附图图示了示例并且与描述一起用于解释示例的原理。其他示例和示例的许多预期优点将容易被领会到,因为通过参考下面的详细描述,它们变得更好理解。
附图的元件不一定相对于彼此按比例。相似的参考数字指代对应的相似部分。
图1示出根据其中焊料球直接与再分布层(RDL)焊盘连接的示例的电子器件的示意性横截面侧视图表示。
图2示出根据其中焊料球经由凸块下金属化(UBM)焊盘与RDL焊盘连接的示例的电子器件的示意性横截面侧视图表示。
图3包括图3A和图3B并且示出了根据其中电子器件包括两个几乎半圆形的槽的示例的电子器件的示意性俯视图表示(A)和横截面侧视图表示(B)。
图4包括图4A和图4B并且示出了根据其中电子器件包括几乎完整的圆的槽的示例的电子器件的示意性俯视图表示(A)和横截面侧视图表示(B)。
图5包括图5A和图5B并且示出了根据其中电子器件包括一个几乎半圆形的槽的示例的电子器件的示意性俯视图表示(A)和横截面侧视图表示(B)。
图6包括图6A和图6B并且示出了根据其中电子器件包括两个几乎四分之一圆的槽的示例的电子器件的示意性俯视图表示(A)和横截面侧视图表示(B)。
图7包括图7A和图7B并且示出了根据其中电子器件包括一个半圆形的槽的示例的电子器件的示意性俯视图表示(A)和横截面侧视图表示(B)。
具体实施方式
现在参照附图描述各方面和示例,其中相似的参考数字通常始终用于指代相似的元件。在下面的描述中,为了解释的目的,阐述了许多具体细节以便提供对示例的一个或多个方面的透彻理解。然而,对于本领域技术人员而言可能明显的是,示例的一个或多个方面可以以具体细节的较小程度来实践。在其他情况下,以示意形式示出已知的结构和元件以便便于描述示例的一个或多个方面。应理解的是,在不脱离本公开的范围的情况下,可以利用其他示例并且可以做出结构或逻辑改变。应该进一步指出的是,附图不是按比例的或不一定是按比例的。
在下面的详细描述中,参考附图,附图形成本文的一部分,并且其中通过图示的方式示出了其中可以实践本公开的具体方面。就这方面而言,可以参考所描述的附图的定向而使用诸如“顶部”、“底部”、“前”、“后”等的方向术语。由于所描述的器件的部件可以以多个不同的定向定位,所以方向术语可以用于说明的目的并且决不是限制性的。理解的是,在不脱离本公开的范围的情况下,可以利用其他方面并且可以做出结构或逻辑改变。因此,下面的详细描述不应以限制性意义来理解,并且本公开的范围由所附权利要求限定。
另外,虽然可能仅关于若干实现方式中的一个公开了示例的特定特征或方面,但是可以将这样的特征或方面与其他实现方式的一个或多个其他特征或方面组合,当对于任何给定的或特定的应用而言这可以是期望的和有利的时。此外,就在详细描述或权利要求中使用的术语“包含”、“具有”、“带有”或其其他变型而言,这样的术语旨在以类似于术语“包括”的方式是包含性的。可以使用术语“耦合”和“连接”连同衍生词。应该理解的是,这些术语可以用于指示两个元件彼此协作或相互作用,而不管它们是直接物理或电接触,还是它们彼此没有直接物理或电接触。而且,术语“示例性”仅仅意在作为示例,而不是最佳或最优。因此,下面的详细描述不应以限制性意义来理解,并且本公开的范围由所附权利要求限定。
电子器件可以包括半导体管芯或半导体芯片,其可以包括在其外表面中的一个或多个上的接触元件或接触焊盘,其中接触元件与相应半导体管芯的电路(例如晶体管)电连接,并且用于将半导体管芯电连接到外侧。接触元件可以具有任何期望的形式或形状。它们能够例如具有小岛(即,半导体管芯的外表面上的平坦接触层)的形式。接触元件或接触焊盘可以由任何导电材料制成,例如,由金属(如铝、金或铜)、或例如金属合金(例如由铝和铜)、或导电有机材料或导电半导体材料制成。接触元件也可以被形成为上面提及的材料或另外的材料中的一种或多种的层堆叠,以便创建例如NiPdAu的堆叠。
电子器件的示例可以包括具有嵌入其中的半导体芯片的密封剂或包封材料。包封材料能够是任何电绝缘材料,类似例如任何种类的模制材料、任何种类的树脂材料或任何种类的环氧材料、双马来酰亚胺或氰酸酯。包封材料也能够是聚合物材料、聚酰亚胺材料、热塑性材料、陶瓷材料和玻璃材料。包封材料还可以包括上面提及的材料中的任何,并且还包含嵌入其中的填充材料,类似例如导热增强物。这些填料增强物能够由SiO、Al2O3、ZnO、AlN、BN、MgO、Si3N4或陶瓷或金属材料(类似例如Cu、Al、Ag或Mo)制成。此外,例如,填料增强物可以具有纤维的形状并且能够由碳纤维或纳米管制成。
图1和图2示出了根据第一方面的电子器件的示例,其中,图1和图2中示出的器件代表本公开的总体想法:其将应力释放结构设计到再分布层焊盘中以便降低或甚至防止再分布层疲劳。这是通过如下来完成的:增加再分布层焊盘的机械灵活性以便允许更好的焊料球活动或位移,这进而引起再分布层焊盘上的较低应力负荷。
如图1中示出的电子器件10包括焊料球1、包括开口的电介质层4以及包括与焊料球1连接的RDL焊盘3.1的再分布层(RDL)3,RDL焊盘3.1包括至少一个空隙3.11,空隙3.11至少部分地设置在RDL焊盘3.1的在电介质层4的开口的横向外侧的区域中。RDL 3可以设置在衬底5上,衬底5例如能够是另外的电介质层或密封层。稍后将示出和解释其更具体的示例。
因此,图1的电子器件10包括焊料球1和RDL焊盘3.1之间的直接连接,其中焊料球1在电介质层4的开口内连接到RDL焊盘3.1。然而,还可能的是,电子器件含有附加的凸块下金属化(UBM),如在下文中将示出的。
如图2所示出的电子器件15包括焊料球1、与焊料球1连接的凸块下金属(UBM)层焊盘2以及包括与UBM层焊盘2连接的RDL焊盘 3.1的再分布层(RDL)3。因此,焊料球通过UBM层焊盘2与RDL焊盘3.1连接(例如电连接)。RDL焊盘3.1包括至少一个空隙3.11,空隙3.11至少部分地设置在RDL焊盘3.1的在UBM层焊盘2的横向外侧的区域中。RDL 3和UBM层焊盘2可以由例如Cu或Al制成。UBM层焊盘2还可以包括具有包括Cu或Al或其合金的至少一个层的层堆叠。
空隙3.11充当应力释放结构并且能够是形成的歧管。在下文中将呈现空隙的不同示例,其中每一个提供RDL焊盘的弹性悬挂并且因此允许焊料球的倾斜和动摇。
关于如图1和图2所示出的电子器件的示例,上面陈述:空隙3.11位于电介质层4的开口的横向外侧(图1)或UBM焊盘2的横向外侧。要理解的是,在两个示例中,技术术语“在……的横向外侧”要以如下意义来理解:空隙3.11位于电介质层4的开口或UBM焊盘2到RDL 3的平面上的正交投影(即,诸如图1和图2中的虚线所指示的正交投影)的横向外侧。
在下文中,将描述具体特征、它们的性质和优点,其中将结合另外的附图进一步详细描述这些特征。
根据第一方面的电子器件10或15的示例,空隙3.11完全设置在RDL焊盘3.1的在电介质层4的开口的横向外侧的区域中或者甚至完全设置在UBM层焊盘2的横向外侧。这样的示例示出在图1或图2中,其中虚线分别指示电介质层4的开口或UBM层焊盘2的横向延伸。能够清楚地看到,空隙3.11完全设置在UBM层焊盘2的横向外侧。
根据第一方面的电子器件10或15的示例,空隙部分地设置在RDL焊盘的在电介质层的开口或UBM层焊盘的横向外侧的区域中,并且部分地设置在RDL焊盘的在电介质层的开口或UBM层焊盘的横向内侧的区域中。在这样的示例中,空隙将以这样一种方式设置,使得在图1或图2中,虚线中的一条将穿过空隙。
根据第一方面的电子器件10或15的示例,RDL焊盘3.1在RDL焊盘的在图1中的电介质层的开口或者图2中的UBM层焊盘2的横向内侧的区域中不包括空隙。
根据第一方面的电子器件15的示例,UBM焊盘2和RDL焊盘3.1中的一个或多个在其之上的俯视图中包括圆形形式。
根据第一方面的电子器件10或15的示例,RDL焊盘3.1包括两个或更多空隙。根据其另外的示例,所述两个或更多空隙被形成为在形状方面不同的、相似的或相同的。下面将结合另外的附图中的一些示出和描述其具体示例。
根据第一方面的电子器件10或15的示例,RDL焊盘包括两个或更多空隙,其中所述两个或更多空隙全部定位在距RDL焊盘3.1的中心点相同的径向距离处。特别地,RDL焊盘3.1可以包括基本上圆形的形式,使得RDL焊盘3.1的中心点由圆心点给出,并且所述两个或更多空隙位于距圆心点的相同的半径处。
根据第一方面的电子器件10或15的示例,空隙3.11包括槽的形式,槽包括具有长度和宽度的细长形式,其中长度大于宽度。更具体地,槽的长度可以是槽的宽度的至少3倍、更具体地至少4倍、更具体地至少5倍。
根据其另外的示例,槽包括在从5 μm至100 μm的范围内的宽度。槽可以包括在空间上恒定的或可变的宽度。
根据其另外的示例,槽沿着圆弧区段布置。根据其另外的示例,圆弧区段在几乎圆的完整圆周之上延伸。根据另一示例,圆弧区段在几乎半圆的完整圆周之上延伸。根据另一个示例,圆弧区段在半圆的完整圆周之上延伸。根据另一示例,提供了两个槽,每一个槽均在几乎半圆的完整圆周之上延伸。
根据另一示例,提供了两个槽,其中每一个均在几乎四分之一圆的完整圆周之上延伸。
根据第一方面的电子器件10和15的示例,一个或多个空隙被形成和布置为使得RDL焊盘的内部部分通过两个扭转弹簧或者通过一个悬臂弹簧被悬挂。其示例将在下面进一步示出。通过形成包括空间上可变的槽宽度的槽,还可以可能的是生成具有空间上可变的强度的弹簧。
到目前为止,本文中解释了如下总体想法:将空隙引入在半导体封装侧的金属化层中以便提供释放结构。就此应该提及的是,这个想法原则上也能够应用于客户侧的PCB,特别是应用于与封装侧的焊料球直接或间接电接触的金属化层中的一个或多个。
根据本公开的第二方面的电子器件包括焊料球和与焊料球连接的金属层焊盘,金属层焊盘包括至少一个空隙,空隙被形成为槽,槽包括沿着圆弧区段布置的细长形式。根据其示例,焊料球能够与金属层焊盘直接连接。根据其另一示例,焊料球能够与金属层焊盘间接连接,即在它们之间能够存在任何种类的中间层,如例如凸块下金属(UBM)层焊盘。
根据第二方面的电子器件的示例,电子器件进一步包括再分布线(RDL),并且金属层焊盘可以由与RDL连接的RDL焊盘给出。
根据第二方面的电子器件的示例,电子器件可以包括可以由与焊料球直接连接的凸块下金属(UBM)层焊盘给出的另外的金属层焊盘。根据其另外的示例,空隙至少部分地设置在RDL焊盘的在UBM层焊盘的横向外侧的区域中。
根据第二方面的电子器件的示例,电子器件进一步包括电介质层,该电介质层包括开口,其中焊料球通过开口与RDL焊盘或与UBM焊盘连接。根据其另外的示例,空隙至少部分地设置在RDL焊盘的在电介质层的开口的横向外侧的区域中。
第二方面的电子器件的另外的示例可以通过添加如上面结合第一方面的电子器件描述的另外的示例或特征或者下面进一步描述的特征的其他示例来形成。
另外的附图3-7示出了根据第一或第二方面中的任一个的电子器件的具体示例。这些示例是其中相应的电子器件含有UBM层焊盘(类似在图2的示例中)的示例。然而,要注意的是,这些示例也适用于其中电子器件不含有UBM层焊盘(类似在图1的示例中)的变型。
图3包括图3A和图3B,并且示出了电子器件的俯视图表示(A)和横截面侧视图表示(B),所述电子器件包括两者均在几乎半圆的完整圆周之上延伸的两个空隙。
图3的电子器件20包括衬底26、设置在衬底26上的第一电介质层25、设置在第一电介质层25上的RDL焊盘23.1、设置在RDL焊盘23.1上的第二电介质层24、设置在RDL焊盘23.1上的UBM层焊盘22以及设置在UBM层焊盘22上的焊料球21。第二电介质层24包括开口,其中UBM层焊盘22在第二电介质层24的开口中设置在RDL焊盘23.1上。图3A中的参考符号24指代第二电介质层24的内圆周。RDL焊盘23.1包括两个空隙23.11,其包括两个半圆形槽23.11的形式,如在图3A中能够看到的。
图3B是沿着图3A的线B-B的横截面,使得图3B的横截面描绘了在UBM层焊盘22的任一横向侧的两个半圆形槽23.11。
图3A示出由于两个几乎半圆形槽23.11的形式,RDL焊盘23.1包括仅经由两个受限区域23.13与RDL焊盘23.1的外部部分连接的内部部分23.12。这些受限区域23.13有效地起到扭转弹簧的作用,其允许内部部分23.12围绕垂直于B-B轴的轴的旋转活动。以这样的方式,承载焊料球21的内部部分23.12可以在焊料球21的任何活动(例如倾斜或动摇)的情况下弹性地滑回。顺便一提,电流通过受限区域23.13流入RDL焊盘23.1中以及从RDL焊盘23.1流到焊料球21,这由于在5 μm至10 μm的范围内的RDL 23的厚度而应该没有问题。
衬底26可以包括例如可以由上面提及的材料制作的包封层。包封层可以包封附图中未示出的半导体管芯或半导体芯片。衬底26可以替代地包括例如半导体芯片的电介质材料或半导体材料,或者由其构成。
图3A进一步更详细地示出了RDL 23。特别地,RDL 23包括RDL焊盘23.1、RDL过渡区23.2和RDL线23.3。例如,RDL线23.3可以通向半导体管芯,特别地通向半导体管芯的接触焊盘,并且能够通过穿过衬底26的通路连接而连接到接触焊盘。可以如图2所示出的那样形成RDL过渡区23.2,其中RDL线23.3的宽度连续增加,直到RDL过渡区23.2到达圆形形式的RDL焊盘23.1的外周界为止。RDL过渡区23.2也能够具有不同的形状。替代地,还可能的是,不存在特定的RDL过渡区23.2,并且作为替代,RDL线23.3包括恒定的宽度,直到其到达RDL焊盘23.1的外周界为止。
根据图3A,RDL焊盘23.1经由RDL过渡区23.3与仅一个RDL线23.3连接。然而,也能够是如下情况:RDL焊盘23.1与多于一个RDL线连接。特别地,RDL焊盘23.1能够与另外的RDL线连接。另外的RDL线能够以与RDL线23.3相同的方式或以不同的方式连接到RDL焊盘23.1,并且其能够与RDL线23.3直接相对地连接到RDL焊盘23.1(参见图3A中的插图(insert))。
应该补充的是,空隙位置和空隙计数独立于一个或多个RDL线到RDL焊盘的外部连接。这意味着在图3所示出的一侧或两侧RDL连接中的任一个中,空隙的布置例如能够相对于如图3A所示出的布置旋转90°,在这种情况下,当然内部位置的旋转活动的轴将处于不同,因为扭转弹簧的位置将不同。此外,在如图3A的插图中所示出的两侧连接的情况下,不需要在RDL连接的每侧都提供空隙。例如,能够仅在RDL连接的一侧有一个半圆形空隙,并且在相对的RDL连接的侧没有半圆形空隙。
应该进一步补充的是,焊盘23.1可以完全或部分地被类似铜的另外的金属层包围。这意味着,即使在诸如图3A所示出的一侧RDL连接的情况下,也能够在右侧提供另外的铜层,这样的另外的铜层在右侧与焊盘23.1邻接并且仅围绕焊盘23.1的右半部分或甚至完全围绕焊盘23.1。
图4包括图4A和图4B,并且示出了电子器件的示例的俯视图表示(A)和横截面侧视图表示(B),所述电子器件包括在几乎圆的完整圆周之上延伸的一个槽。图4的电子器件30包括与图3的电子器件20相同的层结构,使得在此将不重复其细节,并且使用与图3中相同的参考符号,除了RDL焊盘33.1和槽33.11之外。图4B的横截面视图沿着穿过空隙33.11的图4A的线B-B,其在UBM层焊盘22的一个横向侧。
图4A示出了:由于一个几乎圆周的圆形槽33.11的形式,RDL焊盘33.1包括仅经由一个受限区域33.13与RDL焊盘33.1的外部部分连接的内部部分33.12。这些受限区域33.13有效地起到悬臂弹簧的作用,其允许内部部分33.12围绕穿过受限区域33.13的平行于纸张的平面并且垂直于B-B轴的轴的旋转活动。以这样的方式,承载焊料球21的内部部分33.12可以在焊料球21的任何活动(例如焊料球21的倾斜或动摇)的情况下弹性地滑回。顺便一提,电流通过受限区域33.13流入RDL焊盘33.1中以及从RDL焊盘33.1流到焊料球21,这由于在5 μm至10 μm的范围内的RDL 33的厚度而应该没有问题。
图5包括图5A和图5B,并且示出了根据另外的示例的电子器件的俯视图表示(A)和横截面侧视图表示(B),在所述另外的示例中,提供了在几乎半圆的完整圆周之上延伸的一个槽。图5的电子器件40包括与图3的电子器件20相同的层结构,使得在此将不重复其细节,并且使用与图3中相同的参考符号,除了RDL焊盘43.1和槽43.11之外。图5B的横截面视图沿着穿过空隙43.11的图5A的线B-B,其在UBM层焊盘22的一个横向侧。RDL焊盘43.1包括内部部分43.12,该内部部分43.12通过两个受限区域43.13与外部部分连接,所述受限区域43.13以与图3的示例中所解释的类似的方式充当扭转弹簧。
图6包括图6A和图6B,并且示出了根据另外的示例的电子器件的俯视图表示(A)和横截面侧视图表示(B),在该另外的示例中提供了两者均在几乎四分之一圆之上延伸的两个槽。图6的电子器件50包括与图3的电子器件20相同的层结构,使得在此将不重复其细节,并且使用与图3中相同的参考符号,除了RDL焊盘53.1和两个槽53.11之外。图6B的横截面视图沿着图6A的线B-B。在这种情况下,线B-B不穿过槽53.11,使得它们在图6B的横截面视图中不可见。RDL焊盘53.1包括内部部分53.12,该内部部分53.12通过一个受限区域53.13与外部部分连接,所述受限区域53.13以与图4的示例中所解释的类似的方式充当悬臂弹簧。
图7包括图7A和图7B,并且示出了根据另外的示例的电子器件的俯视图表示(A)和横截面侧视图表示(B),在该另外的示例中,提供了在半圆的完整圆周之上延伸的一个槽。图7的电子器件60包括与图4的电子器件30相同的层结构,使得在此将不重复其细节,并且使用与图4中相同的参考符号,除了RDL焊盘63.1和槽63.11之外。图7B的横截面视图沿着穿过空隙63.11的图7A的线B-B,其在UBM层焊盘22的一个横向侧。与图4的示例的一个区别在于,RDL焊盘63.1包括内部部分63.12,所述内部部分63.12利用比如图4的示例中的33.13显著更宽的受限区域63.13的形成而连接到外部部分63.1。结果,内部部分被具有悬臂弹簧和扭转弹簧两者的机械性质或行为的弹簧悬挂。
本公开还涉及根据第三方面的半导体器件。第三方面的半导体器件包括:衬底;设置在衬底上的第一电介质层;设置在第一电介质层上的第一金属层焊盘;设置在第一金属层焊盘上且在第一电介质层上的第二电介质层,该第二电介质层包括开口;在第二电介质层的开口中设置在第一金属焊盘上的第二金属层焊盘;以及设置在第二金属层焊盘上的焊料球,其中,第一金属层焊盘包括至少一个空隙,该空隙至少部分设置在第二电介质层的开口的横向外侧或者甚至在第二金属层焊盘的外侧,并且空隙被形成为槽,该槽包括沿着圆弧区段布置的细长形式。
根据第三方面的半导体器件的示例在如上面详细描述的图3至图6中示出。第一金属层焊盘能够由RDL焊盘给出,并且第二金属层焊盘能够由UBM层焊盘给出。
根据第三方面的半导体器件的示例,半导体器件进一步包括再分布线(RDL),其中,如图1和图2中的电子器件的示例中所示出的那样,第一金属层焊盘是RDL的一部分并与RDL集成,并且衬底可以包括半导体管芯或者与半导体管芯连接,半导体管芯可以包括接触焊盘,接触焊盘借助于RDL和在RDL下方的电介质层中形成的通路与第一金属层焊盘连接。衬底可以包括把半导体管芯嵌入的包封层或者由其构成,在这种情况下,通路也将必须形成在该包封层中。
第三方面的半导体器件的另外的示例能够通过与如上面结合第一方面或第二方面的电子器件所描述的示例或特征中的一个或多个相组合而形成。
本公开还涉及根据第四方面的用于制作电子器件的方法。该方法包括:提供再分布层(RDL);在RDL中构造RDL焊盘,特别是具有圆形形式的RDL焊盘;以及在RDL焊盘中构造至少一个空隙。
根据第四方面的方法的示例,该方法进一步包括以这样一种方式在所述RDL焊盘上方制作凸块下金属(UBM)金属焊盘,使得至少一个空隙至少部分地设置在RDL焊盘的在UBM的横向外侧的区域中。
第四方面的方法的另外的示例能够通过与如上面结合第一方面或第二方面的电子器件以及第三方面的半导体器件所描述的示例或特征中的一个或多个相组合而形成。
虽然已经关于一个或多个实现方式说明和描述了本公开,但是在不脱离所附权利要求的精神和范围的情况下,可以对所说明的示例做出更改和/或修改。特别地关于由上面描述的部件或结构(组件、器件、电路、系统等)执行的各种功能,除非另外指示,否则用于描述这样的部件的术语(包括对“装置”的引用)旨在对应于执行所描述的部件的指定功能(例如,在功能上等同的)的任何部件或结构,即使在结构上不等同于在本文所说明的本公开的示例性实施方式中执行该功能的所公开的结构。
Claims (21)
1.一种电子器件,包括:
焊料球;
包括开口的电介质层;以及
包括与所述焊料球连接的RDL焊盘的再分布层(RDL);
所述RDL焊盘包括至少一个空隙,所述空隙至少部分地设置在所述RDL焊盘的在所述电介质层的开口的横向外侧的区域中。
2.根据权利要求1所述的电子器件,进一步包括:
所述空隙完全设置在所述RDL焊盘的在所述电介质层的开口的横向外侧的区域中。
3.根据权利要求1或2所述的电子器件,进一步包括:
与所述焊料球连接的凸块下金属(UBM)层焊盘,其中,
所述空隙至少部分地设置在所述RDL焊盘的在所述UBM层焊盘的横向外侧的区域中。
4.根据权利要求3所述的电子器件,进一步包括:
所述空隙完全设置在所述RDL焊盘的在所述UBM层焊盘的横向外侧的区域中。
5.根据前述权利要求中的任一项所述的电子器件,进一步包括:
所述RDL焊盘在所述RDL焊盘的在所述电介质层的开口的横向内侧的区域中不包括空隙。
6.根据前述权利要求中的任一项所述的电子器件,进一步包括:
所述空隙被形成为槽,所述槽包括具有长度和宽度的细长形式,其中所述长度大于所述宽度。
7.根据权利要求6所述的电子器件,进一步包括:
所述槽包括在从5 μm至100 μm的范围内的宽度。
8.根据权利要求6或7所述的电子器件,进一步包括:
所述槽沿着圆弧区段布置。
9.根据权利要求3或者回引权利要求3的权利要求4至8中的任一项所述的电子器件,进一步包括:
所述UBM层焊盘在所述电介质层的开口中设置在所述RDL焊盘上。
10.根据前述权利要求中的任一项所述的电子器件,进一步包括:
RDL包括连接到所述RDL焊盘的再分布线。
11.一种电子器件,包括:
焊料球;以及
与所述焊料球连接的金属层焊盘,所述金属层焊盘包括至少一个空隙,所述空隙被形成为槽,所述槽包括沿着圆弧区段布置的细长形式。
12.根据权利要求11所述的电子器件,进一步包括:
连接在所述焊料球和所述金属层焊盘之间的凸块下金属(UBM)层焊盘。
13.根据权利要求11或12所述的电子器件,进一步包括:
所述槽包括长度和宽度,其中,所述长度是所述宽度的至少3倍。
14.根据权利要求11至13中的任一项所述的电子器件,进一步包括:
恰好一个沿着圆弧区段布置的槽,其中,所述圆弧区段在几乎圆的完整圆周之上延伸。
15.根据权利要求11至13中的任一项所述的电子器件,进一步包括:
恰好两个槽,其中,所述两个槽中的每一个沿着圆弧区段布置,并且所述圆弧区段中的每一个在几乎半圆的完整圆周之上延伸。
16.根据权利要求11至13中的任一项所述的电子器件,进一步包括:
恰好一个沿着圆弧区段布置的槽,其中,所述圆弧区段在几乎半圆的完整圆周之上或在半圆的完整圆周之上延伸。
17.根据权利要求11至13中的任一项所述的电子器件,进一步包括:
恰好两个槽,其中,所述两个槽中的每一个沿着圆弧区段布置,并且所述圆弧区段中的每一个在几乎四分之一圆的完整圆周之上延伸。
18.一种半导体器件,包括:
衬底;
设置在所述衬底上的第一电介质层;
设置在所述第一电介质层上的第一金属层焊盘;
设置在所述第一金属层焊盘上且在所述第一电介质层上的第二电介质层,所述第二电介质层包括开口;
在所述第二电介质层的开口中设置在所述第一金属层焊盘上的第二金属层焊盘;以及
设置在所述第二金属层焊盘上的焊料球;
其中,所述第一金属层焊盘包括至少一个空隙,所述空隙至少部分地设置在所述第二金属层焊盘的横向外侧,并且所述空隙被形成为槽,所述槽包括沿着圆弧区段布置的细长形式。
19.根据权利要求18所述的半导体器件,其中,所述衬底包括包封层或由包封层构成。
20.根据权利要求18或19所述的半导体器件,进一步包括:
再分布线,其中,所述第一金属层焊盘是再分布焊盘,并且是所述再分布线的一部分且与所述再分布线集成。
21.根据权利要求20所述的半导体器件,其中,
所述衬底包括半导体管芯,所述半导体管芯包括接触焊盘,所述接触焊盘至少部分地借助于所述再分布线与所述第一金属层焊盘连接。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114303233A (zh) * | 2019-08-26 | 2022-04-08 | 思睿逻辑国际半导体有限公司 | 用于最小化集成电路封装中的机械应力的金属层图案化 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102017210654B4 (de) * | 2017-06-23 | 2022-06-09 | Infineon Technologies Ag | Elektronische Vorrichtung, die ein einen Hohlraum umfassendes Umverdrahtungsschicht-Pad umfasst |
US11276633B2 (en) | 2019-11-14 | 2022-03-15 | Samsung Electronics Co., Ltd. | Semiconductor package having UBM pad with gap separating central portion from peripheral portion |
KR102698828B1 (ko) | 2019-12-26 | 2024-08-26 | 삼성전자주식회사 | 패키지 기판 및 이를 포함하는 반도체 패키지 |
IT202000024346A1 (it) | 2020-10-15 | 2022-04-15 | St Microelectronics Srl | Struttura di elettrodo con forma migliorata, e dispositivo elettronico comprendente la struttura di elettrodo |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57119577U (zh) * | 1981-01-17 | 1982-07-24 | ||
US20040041393A1 (en) * | 2002-08-29 | 2004-03-04 | Lee Teck Kheng | Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same |
US20060237855A1 (en) * | 2005-03-29 | 2006-10-26 | Steffen Kroehnert | Substrate for producing a soldering connection to a second substrate |
CN101847610A (zh) * | 2009-03-25 | 2010-09-29 | 卡西欧计算机株式会社 | 半导体装置及其制造方法 |
CN102036475A (zh) * | 2009-10-07 | 2011-04-27 | 瑞萨电子株式会社 | 布线板 |
KR20110076605A (ko) * | 2009-12-29 | 2011-07-06 | 하나 마이크론(주) | 반도체 패키지 및 그 제조 방법 |
US20110193224A1 (en) * | 2010-02-10 | 2011-08-11 | Denso Corporation | Semiconductor device |
CN102668069A (zh) * | 2009-10-23 | 2012-09-12 | Ati科技无限责任公司 | 用于在半导体裸片中缓解应力的布线层 |
US20130119534A1 (en) * | 2011-11-16 | 2013-05-16 | International Business Machines Corporation | Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump |
US20140008786A1 (en) * | 2012-07-09 | 2014-01-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace packaging structure and method for forming the same |
US20140061898A1 (en) * | 2012-08-30 | 2014-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal Pads with Openings in Integrated Circuits |
US20140252610A1 (en) * | 2013-03-11 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging Devices and Methods of Manufacture Thereof |
US20160133592A1 (en) * | 2014-11-10 | 2016-05-12 | Rohm Co., Ltd. | Semiconductor device and manufacturing method for the same |
US20170084558A1 (en) * | 2015-09-18 | 2017-03-23 | Samsung Electronics Co., Ltd. | Semiconductor package |
US20170141055A1 (en) * | 2015-11-16 | 2017-05-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip Packages and Methods of Manufacture Thereof |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3823469A (en) * | 1971-04-28 | 1974-07-16 | Rca Corp | High heat dissipation solder-reflow flip chip transistor |
US6239703B1 (en) * | 1998-01-02 | 2001-05-29 | Intermec Ip Corp | Communication pad structure for semiconductor devices |
US6551916B2 (en) * | 1999-06-08 | 2003-04-22 | Winbond Electronics Corp. | Bond-pad with pad edge strengthening structure |
KR100306842B1 (ko) * | 1999-09-30 | 2001-11-02 | 윤종용 | 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법 |
JP4361223B2 (ja) | 2001-03-19 | 2009-11-11 | 株式会社フジクラ | 半導体パッケージ |
US6825541B2 (en) * | 2002-10-09 | 2004-11-30 | Taiwan Semiconductor Manufacturing Co., Ltd | Bump pad design for flip chip bumping |
US7098540B1 (en) * | 2003-12-04 | 2006-08-29 | National Semiconductor Corporation | Electrical interconnect with minimal parasitic capacitance |
US20060091566A1 (en) * | 2004-11-02 | 2006-05-04 | Chin-Tien Yang | Bond pad structure for integrated circuit chip |
KR100596452B1 (ko) * | 2005-03-22 | 2006-07-04 | 삼성전자주식회사 | 볼 랜드와 솔더 볼 사이에 에어 갭을 갖는 웨이퍼 레벨 칩스케일 패키지와 그 제조 방법 |
JP4247690B2 (ja) * | 2006-06-15 | 2009-04-02 | ソニー株式会社 | 電子部品及その製造方法 |
US7501708B2 (en) * | 2006-07-31 | 2009-03-10 | International Business Machines Corporation | Microelectronic device connection structure |
US20090001567A1 (en) * | 2007-06-27 | 2009-01-01 | Ultra Chip, Inc. | IC chip with finger-like bumps |
US8492263B2 (en) * | 2007-11-16 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protected solder ball joints in wafer level chip-scale packaging |
US20090160052A1 (en) * | 2007-12-19 | 2009-06-25 | Advanced Chip Engineering Technology Inc. | Under bump metallurgy structure of semiconductor device package |
KR100979497B1 (ko) * | 2008-06-17 | 2010-09-01 | 삼성전기주식회사 | 웨이퍼 레벨 패키지 및 그 제조방법 |
US7812462B2 (en) * | 2008-11-04 | 2010-10-12 | National Semiconductor Corporation | Conductive paths for transmitting an electrical signal through an electrical connector |
US7989356B2 (en) * | 2009-03-24 | 2011-08-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming enhanced UBM structure for improving solder joint reliability |
US8446006B2 (en) * | 2009-12-17 | 2013-05-21 | International Business Machines Corporation | Structures and methods to reduce maximum current density in a solder ball |
US8368202B2 (en) * | 2010-11-24 | 2013-02-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package having the same |
US8647974B2 (en) * | 2011-03-25 | 2014-02-11 | Ati Technologies Ulc | Method of fabricating a semiconductor chip with supportive terminal pad |
US9613914B2 (en) * | 2011-12-07 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure |
US8766441B2 (en) * | 2012-03-14 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for solder on slot connections in package on package structures |
US8791008B2 (en) * | 2012-03-21 | 2014-07-29 | Stats Chippac, Ltd. | Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief |
US9224688B2 (en) * | 2013-01-04 | 2015-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal routing architecture for integrated circuits |
US9349665B2 (en) * | 2013-01-18 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of packaging of semiconductor devices |
US9018757B2 (en) * | 2013-07-16 | 2015-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanisms for forming bump structures over wide metal pad |
DE102014113498B4 (de) * | 2014-09-18 | 2019-03-28 | Infineon Technologies Ag | Stromstärkesensor mit einem Messwiderstand in einer Umverteilungsschicht |
US9793231B2 (en) * | 2015-06-30 | 2017-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Under bump metallurgy (UBM) and methods of forming same |
KR20170107823A (ko) * | 2016-03-16 | 2017-09-26 | 삼성전자주식회사 | 스트레스를 분산시킬 수 있는 반도체 장치 |
US10256202B1 (en) * | 2017-01-25 | 2019-04-09 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits |
DE102017210654B4 (de) * | 2017-06-23 | 2022-06-09 | Infineon Technologies Ag | Elektronische Vorrichtung, die ein einen Hohlraum umfassendes Umverdrahtungsschicht-Pad umfasst |
US10256206B2 (en) * | 2018-03-16 | 2019-04-09 | Intel Corporation | Qubit die attachment using preforms |
-
2017
- 2017-06-23 DE DE102017210654.9A patent/DE102017210654B4/de active Active
-
2018
- 2018-06-21 US US16/014,745 patent/US10916484B2/en active Active
- 2018-06-22 CN CN201810650999.2A patent/CN109119399B/zh active Active
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57119577U (zh) * | 1981-01-17 | 1982-07-24 | ||
US20040041393A1 (en) * | 2002-08-29 | 2004-03-04 | Lee Teck Kheng | Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same |
US20060237855A1 (en) * | 2005-03-29 | 2006-10-26 | Steffen Kroehnert | Substrate for producing a soldering connection to a second substrate |
CN101847610A (zh) * | 2009-03-25 | 2010-09-29 | 卡西欧计算机株式会社 | 半导体装置及其制造方法 |
US20100244188A1 (en) * | 2009-03-25 | 2010-09-30 | Casio Computer Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN102036475A (zh) * | 2009-10-07 | 2011-04-27 | 瑞萨电子株式会社 | 布线板 |
CN102668069A (zh) * | 2009-10-23 | 2012-09-12 | Ati科技无限责任公司 | 用于在半导体裸片中缓解应力的布线层 |
KR20110076605A (ko) * | 2009-12-29 | 2011-07-06 | 하나 마이크론(주) | 반도체 패키지 및 그 제조 방법 |
US20110193224A1 (en) * | 2010-02-10 | 2011-08-11 | Denso Corporation | Semiconductor device |
US20130119534A1 (en) * | 2011-11-16 | 2013-05-16 | International Business Machines Corporation | Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump |
US20140008786A1 (en) * | 2012-07-09 | 2014-01-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace packaging structure and method for forming the same |
US20140061898A1 (en) * | 2012-08-30 | 2014-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal Pads with Openings in Integrated Circuits |
US20140252610A1 (en) * | 2013-03-11 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging Devices and Methods of Manufacture Thereof |
US20160133592A1 (en) * | 2014-11-10 | 2016-05-12 | Rohm Co., Ltd. | Semiconductor device and manufacturing method for the same |
US20170084558A1 (en) * | 2015-09-18 | 2017-03-23 | Samsung Electronics Co., Ltd. | Semiconductor package |
US20170141055A1 (en) * | 2015-11-16 | 2017-05-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip Packages and Methods of Manufacture Thereof |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114303233A (zh) * | 2019-08-26 | 2022-04-08 | 思睿逻辑国际半导体有限公司 | 用于最小化集成电路封装中的机械应力的金属层图案化 |
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