CN1090821C - 绝缘栅场效应晶体管 - Google Patents
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- 230000005669 field effect Effects 0.000 title claims description 13
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 claims abstract description 20
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- 239000011591 potassium Substances 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 10
- 239000003054 catalyst Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 22
- 229920005591 polysilicon Polymers 0.000 description 22
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 18
- 238000003475 lamination Methods 0.000 description 11
- 238000000227 grinding Methods 0.000 description 10
- 238000005498 polishing Methods 0.000 description 10
- 230000003139 buffering effect Effects 0.000 description 9
- 239000007788 liquid Substances 0.000 description 7
- 230000014759 maintenance of location Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000002950 deficient Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000003917 TEM image Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000008719 thickening Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000001963 growth medium Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- -1 this Chemical compound 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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Abstract
两侧各被一个沟槽隔离的FET，在隔离沟槽中沿着FET的至少一侧有一电介质。电介质层可以是一层ONO，中间扩散了氧化催化剂。氧化催化剂可以是钾。FET沿着贴近ONO层侧的栅氧化层比两侧之间的栅氧化层厚。
Description
本发明一般涉及半导体品件，具体涉及如何形成场效应晶体管。
高性能和高密度是集成电路(IC)芯片设计的主要目标。芯片设计者探讨实现这两个目标的一种途径是使器件和器件特征变小。器件特征(和其他电路特征)越小，则电路器件越能够紧凑地封装在一起，因而电路密度越高。电路器件越紧凑地封装在一起，则布线负载越小，从而电路速度越快，即电路性能越高。所以，半导体工艺设计者着力于减小器件特征，使器件越来越小。
仅仅缩小场效应晶体管(FET)的沟道长度来改变器件特性(如穿通电压和阈值电压Vt)将使器件变到可能不适用的地步。所以，也要改变其他器件参数(如沟道掺杂、源/漏掺杂和栅氧化层厚度)来补偿器件特性的变化。一般通过改变沟道掺杂分布型面(profile)来补偿缩短沟道的影响(短沟效应)。然而，掺杂型面的改变会使Vt升高，因而掺杂型面的改变通常伴随栅氧化层的减薄以降低Vt。减薄栅氧化层使沟道上的栅电场增强。因此，单位面积的栅电容增大，栅面积减小，沟道传输电导增大。总之，电路性能得到改善。
不幸的是由于器件特征的缩小，对老式较大尺寸器件可认为是无关紧要的缺陷在这里成为重要的缺陷。较薄的栅氧化层使器件对这些引起漏电的缺陷和降低芯片成品率和芯片可靠性的缺陷更为敏感。成品率降低伴随着芯片成本的增加这一点是很容易确定的，因为完工的晶片成本肯定会因只生产出较少的芯片而增加。与可靠性降低相关的成本，即在正常使用中芯片失效的成本是更严重的问题。这种可靠性失效的代价之所以更大，是因为这将引起系统停机，还因为在包含许多芯片的组合系统中查找失效元件也与生产成本相关。
图1表示一个在64M DRAM工艺过程中生产的FET剖面图。FET 102的两边有两个深沟槽100将其与邻近FET隔离。沿沟槽100侧壁106的氧化层套环(collar)104将FET 102与填满沟槽的多晶硅108隔离，并成为(例如)动态随机存储器(DRAM)单元的电容蓄电板。FET 102的栅由横跨薄栅氧化层112(FET 102的宽度)的多晶硅字线110形成。从漏到源的FET电流(未表出)垂直于多晶硅栅和字线110。
当从套环104去除过量的氧化层时，在沟道的每一侧形成凹坑114。另外，套环104氧化层的形成使沟道侧边116变圆。因此，当沟道102中心处基本为平面时，其侧边116处变圆。凹坑114和圆边对较大尺寸成形FET被认为是很不重要的缺陷。然而，对于64M DRAM工艺，这些缺陷却是很关键的。这种凹坑中和圆边114上的多晶硅使电场E增强，致使该处电场比沟道其他部分要强得多。由于这种增强的电场E，沟道侧边的Vt比沟道其他部分要低。所以，沟道并不是在一个均匀的栅-源电压(Vgs)下开启。实际上，侧边114领先于FET 102的其他处导通，而关断滞后(即Vgs较低)。
这种情况对逻辑电路也许可不予考虑，但对DRAM选通门是不能接受的，因为这会增加选通门沟道漏电。选通门(pass gate)沟道漏电使蓄电板上的存储电荷很快耗散掉。这将缩短DRAM的保持时间，即数据可存储在DRAM单元内无需重写和刷新的时间。一般来说，刷新频率要尽可能低，因为在刷新期间DRAM是不输入输出数据的。但保持时间短的DRAM单元必须要比保持时间长的单元更频繁地刷新。因此，保持时间短是不希望的。于是，将沟道漏电减至最小、从而制作DRAM用的平面型沟道FET就非常重要。
本发明的一个目的是降低FET沟道泄漏。
本发明的另一目的是降低FET阈值电压的沟道偏差。
本发明的又一目的是提高DRAM单元的保持时间。
本发明的又一目的是降低FET的特征尺寸。
本发明的又一目的是降低FET的特征尺寸而不降低DRAM单元的保持时间。
本发明的又一目的是降低FET的特征尺寸而不增加沟道泄漏。
本发明的又一目的是对特征尺寸减小的FET提高阈值电压的均匀性。
本发明的又一目的是对特征尺寸减小的FET降低沟道泄漏和阈值电压的偏差而不损害DRAM单元的保持时间。
本发明是一种场效应晶体管(FET)。这种优选的场效应晶体管(FET)形成在半导体衬底上，最好是形成在硅上。FET的两侧各有一个隔离沟槽，并且在沟槽内沿着FET的两侧有一层ONO层。ONO层中包括钾。FET在沿着ONO层侧的栅氧化层比沟道中心的栅氧化层厚。
图1表示按现有技术制造工艺制作的DRAM中的FET截面示图。
图2A-F表示形成优选实例FET的步骤。
图3是氧化层厚度Tox与钾浓度的关系曲线。
图4是按现有技术方法生长的FET边角处扫描电子显微镜(TEM)图象。
图5A-B是按本发明生长的FET的TEM图象。
图6是包括按现有技术生长的FET与本优选实施例FET的FETs电参量表。
本发明是一种FET以及这种FET的制作工艺。本发明的FET沿沟道侧边的栅氧化层比沟道内部的要厚。在沟道区侧边形成的ONO层含有促进局部氧化层形成的催化剂。催化剂最好是钾。
图2A-F说明这种优选实施例FET的形成步骤，这种FET基本上如图2F所示。首先，在图2A中，在半导体层(或晶片)122中形成深沟槽120。在形成沟槽120之前，先在半导体层122上形成缓冲介电叠层，用叠层121表示。刻蚀出的沟槽120穿透缓冲叠层121并深入晶片122，从而隔离并限定出一个FET区124。沟道、源和漏将在所限定的FET区124中形成。半导体层最好是硅。在这一优选实施例中，制成的这种FET是一种动态随机存储器(DRAM)单元的选通门晶体管。这种DRAM单元的存储电容板在沟槽120中形成。
在图2B中，在缓冲叠层121上和沟槽120内同样地形成ONO层126。尽管标记为单一层，但应当理解ONO层126是在两层薄氧化物层之间夹一层薄氮化物层而形成。该ONO层126衬在沟槽120内表面，沿每个沟槽120侧面垂直延伸，通过晶片122的表面128，并覆盖缓冲叠层121。接着，将N+型多晶硅层(poly)130淀积在ONO层126上。
在图2C中，将缓冲叠层121以上的多晶硅层130去除，从而仅保留沟槽120内的多晶硅132。最好采用化学-机械磨抛(CMP)将多晶硅层130除去。磨抛多晶硅层130也同时除去缓冲叠层121上的大部分ONO层126，因而只保留在沟槽120中的ONO层。经CMP处理之后，从缓冲叠层121上去除残留的ONO层126。然后，用反应离子刻蚀(RIE)法对剩余的多晶硅130进行刻蚀，使沟槽内剩余的多晶硅132下凹到低于晶片表面128最好约1.3μm。用来除去多晶硅层130的理想磨抛液是含氢氧化钾的多晶磨抛液，最好是＜0.1％KOH。ONO层126中的氮化硅是磨抛液中钾的扩散阻挡层。所以，钾穿过外层氧化层扩散进入ONO层126，并聚集在氮化硅层上。为了提高收集的钾含量，可选地也可以将晶片浸泡在KOH溶液容器中。
以含有KOH的磨抛液磨抛多晶层130和可选择的浸泡这些步骤与常规半导体芯片制造技术相矛盾。通常在半导体芯片制造中要避免这样使用钾，因为钾很容易扩散到硅中。因此，使用KOH磨抛液将会严重沾污硅，使其不宜用来形成FET。然而，ONO层126阻止钾的扩散，并沿外氧化层和氮化硅间的界面处收集钾。
接下来，如图2D所示，在沟槽120内多晶132上，沿ONO层126有选择地形成氧化层套环134。形成氧化层套环134后，在晶片122上形成另一N+型多晶层136。这第二多晶层136重新填满带多晶硅的沟槽120。
在图2E中，用CMP和RIE方法将多晶层136从缓冲叠层121除去，这样仅在沟槽120内保留多晶硅140。沟槽120内的多晶硅140与晶片表面128取平，或稍微下凹。如在前面多晶硅的去除步骤中一样，最好的磨抛液是含＜0.1％KOH的多晶硅磨抛液。用干氧化法在暴露的缓冲叠层121上和多晶硅140上生长屏蔽二氧化硅层(未表出)，要小心地避免沿ONO层126将钾去除。然后，根据需要与否确定N阱或P阱。接着，用离子注入法进行合适的掺杂来进行沟道调整。然后，将注入的杂质扩散到晶片内形成所需要的体掺杂硅片衬底122。
注入的杂质扩散后，去除屏蔽二氧化硅层和缓冲叠层121，即可生长栅氧化层。由氮化硅所收集沿沟槽内ONO层126的钾是硅氧化的催化剂。所以，如图2F所示，沿沟道侧边142(即靠近ONO层126处)的栅氧化层变厚。
接着，选择性地生长绝缘氧化层144，将沟槽120内的多晶硅140和后来的导电层隔离。最后，淀积多晶硅字线层146。该多晶硅字线层146采用任何熟知的光刻方法形成。采用集成电路芯片制造中常用的方法形成后来的芯片层并使之形成而制成芯片。
另外，可在生长栅氧化层之前将部分ONO层从所选FET附近的沟槽中(例如，在非阵列区)去除。例如，这可在形成浅沟槽(比阵列隔离沟槽120更浅)作浅沟槽隔离时选择性地将ONO层刻蚀掉。这样就形成两种类型的FET。阵列区中的FET将是优选实例的增强型栅氧化层FET；而非阵列区(或ONO层去除)中的FET则有非增强型的、基本均匀的栅氧化层。
实例说明
图3是氧化层厚度(Tox)的增加与钾浓度的关系的曲线。提高钾的积累水平使沟道侧边的氧化层增厚。这种栅氧化层的增厚进一步从侧边水平地扩展到沟道内。氧化层在垂直和水平两个方向增厚的程度取决于ONO层中收集的钾含量。如果积累的钾含量增到足够高，则整个器件的栅氧化层增厚。厚度的增加与距ONO层124(即离钾催化剂)的水平距离成反比。
此外，生长温度和生长媒体影响由于钾催化剂的存在而引起的局部氧化层厚度的增加的量。在900℃的干氧中生长的栅氧化层比800℃的湿氧中生长的栅氧化层，从侧边到中心氧化层的厚度差别更显著，即在器件侧边比在器件中心要厚得更多。
图4是一个按照现有技术在900℃的氧气中生长的FET边角处(一个侧边的横截面图)的扫描电镜图象。对于这种现有技术的FET，边角处的Tox(沿沟道侧边的Tox)比中心处的Tox(在沟道中心)薄8％。因此，由于这种较薄的边角Tox以及由于沿沟道区顶部水平方向和沿侧边(在沟槽内)垂直方向的多晶硅电场较强，这种现有技术的FET具有较低的Vt。
图5A是按本发明在800℃的湿氧中生长的一个FET边角处的TEM图象。对于这个优选实施例的FET，边角Tox比中心Tox厚30％。因此，其Tox沿沟道侧边的增大都超过现有技术FET的值。而且，由于边角处较厚的Tox而使电场稍有削弱。
图5B是一个在900℃的干氧中生长的优选实例FET边角处的TEM图象。对于这种优选实例FET，边角处Tox比中心Tox厚70％。沿此优选FET侧边加厚的氧化层将边角处的Vt提高到接近中心沟道的Vt值。
图6的表是现有技术10μm宽FET的电参数与优选实例10μm宽FET的比较，每种FET在不同晶片的芯片位置按几乎同样的条件生长。尽管两种器件具有几乎同样的中心沟道Vt和几乎同样的导通电流(Ids)，优选FET的边角Vt差不多等于中心沟道的Vt。相反，现有技术FET的边角Vt是优选实例FET边角Vt的75％。因此，对于优选实例器件，电荷在一单元中保持256ms(电荷在单元中保持的时间)后的保持率(rentention yield)是现有技术的2.6倍多。
虽然利用优选实例对本发明进行了讨论，应当理解的是对熟悉此技术的人可以作出多种改变和改进而并不偏离所述发明的实质。提出下述权利要求的范围以包括属于本发明实质的这类改变和改进。
Claims (3)
1.一种在半导体衬底上，并且在两侧各有隔离沟槽的场效应晶体管，所述场效应晶体管包括：
在所述隔离沟槽中沿着所述场效应晶体管的至少一个所述侧面的ONO电介质层；
所述ONO电介质层中包括氧化催化剂；以及
所述每一场效应晶体管沿着侧边的栅氧化层比所述侧边之间的栅氧化层厚。
2.如权利要求1的场效应晶体管，其特征在于氧化催化剂是钾。
3.如权利要求1或2的场效应晶体管，其特征在于在所述每一场效应晶体管侧边上沿着所述ONO电介质层进一步包括一个氧化物套环。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/688,457 US5757059A (en) | 1996-07-30 | 1996-07-30 | Insulated gate field effect transistor |
| US688,457 | 1996-07-30 | ||
| US688457 | 1996-07-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1175094A CN1175094A (zh) | 1998-03-04 |
| CN1090821C true CN1090821C (zh) | 2002-09-11 |
Family
ID=24764492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97113531A Expired - Fee Related CN1090821C (zh) | 1996-07-30 | 1997-06-27 | 绝缘栅场效应晶体管 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5757059A (zh) |
| EP (1) | EP0822591B1 (zh) |
| JP (1) | JP3347027B2 (zh) |
| KR (1) | KR100267431B1 (zh) |
| CN (1) | CN1090821C (zh) |
| DE (1) | DE69738059T2 (zh) |
| SG (1) | SG50866A1 (zh) |
| TW (1) | TW337600B (zh) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5858866A (en) * | 1996-11-22 | 1999-01-12 | International Business Machines Corportation | Geometrical control of device corner threshold |
| JP4955222B2 (ja) | 2005-05-20 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| CN101217137B (zh) * | 2007-12-26 | 2011-11-30 | 上海宏力半导体制造有限公司 | 一种提高p阱栅氧化层电学厚度测量精确性的测量结构 |
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| JPS63155662A (ja) * | 1986-12-18 | 1988-06-28 | Oki Electric Ind Co Ltd | Ｃｍｉｓ型ダイナミツクメモリ装置 |
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| DD242905A1 (de) * | 1985-11-20 | 1987-02-11 | Halbleiterwerk Veb | Verfahren zur herstellung von thermischen sio tief 2-isolatorschichten |
| JPS6427252A (en) * | 1987-04-13 | 1989-01-30 | Nec Corp | Semiconductor storage device |
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| US4986878A (en) * | 1988-07-19 | 1991-01-22 | Cypress Semiconductor Corp. | Process for improved planarization of the passivation layers for semiconductor devices |
| KR910007181B1 (ko) * | 1988-09-22 | 1991-09-19 | 현대전자산업 주식회사 | Sdtas구조로 이루어진 dram셀 및 그 제조방법 |
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| TW199237B (zh) * | 1990-07-03 | 1993-02-01 | Siemens Ag | |
| US5078801A (en) * | 1990-08-14 | 1992-01-07 | Intel Corporation | Post-polish cleaning of oxidized substrates by reverse colloidation |
| JPH05152429A (ja) * | 1991-11-28 | 1993-06-18 | Nec Corp | 半導体装置の製造方法 |
| US5358894A (en) * | 1992-02-06 | 1994-10-25 | Micron Technology, Inc. | Oxidation enhancement in narrow masked field regions of a semiconductor wafer |
| US5217919A (en) * | 1992-03-19 | 1993-06-08 | Harris Corporation | Method of forming island with polysilicon-filled trench isolation |
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| US5313419A (en) * | 1993-02-01 | 1994-05-17 | National Semiconductor Corporation | Self-aligned trench isolation scheme for select transistors in an alternate metal virtual ground (AMG) EPROM array |
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- 1996-07-30 US US08/688,457 patent/US5757059A/en not_active Expired - Fee Related
-
1997
- 1997-06-27 CN CN97113531A patent/CN1090821C/zh not_active Expired - Fee Related
- 1997-07-09 SG SG1997002420A patent/SG50866A1/en unknown
- 1997-07-15 DE DE69738059T patent/DE69738059T2/de not_active Expired - Lifetime
- 1997-07-15 EP EP97305281A patent/EP0822591B1/en not_active Expired - Lifetime
- 1997-07-28 KR KR1019970035568A patent/KR100267431B1/ko not_active IP Right Cessation
- 1997-07-28 JP JP21707997A patent/JP3347027B2/ja not_active Expired - Fee Related
- 1997-07-29 TW TW086110783A patent/TW337600B/zh not_active IP Right Cessation
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| JPS63155662A (ja) * | 1986-12-18 | 1988-06-28 | Oki Electric Ind Co Ltd | Ｃｍｉｓ型ダイナミツクメモリ装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100267431B1 (ko) | 2000-11-01 |
| DE69738059D1 (de) | 2007-10-11 |
| SG50866A1 (en) | 1998-07-20 |
| JP3347027B2 (ja) | 2002-11-20 |
| JPH1074829A (ja) | 1998-03-17 |
| US5757059A (en) | 1998-05-26 |
| EP0822591A1 (en) | 1998-02-04 |
| DE69738059T2 (de) | 2008-05-21 |
| EP0822591B1 (en) | 2007-08-29 |
| TW337600B (en) | 1998-08-01 |
| CN1175094A (zh) | 1998-03-04 |
| KR980012550A (ko) | 1998-04-30 |
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