CN1090815C - 形成凹穴和接触窗的方法 - Google Patents
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Abstract
一种半导体元件中,在非导电层内形成凹穴的方法,包括步骤:先提供一半导体基底,其上具有一非导电层及一设定图案的光阻层,在光阻层及非导电层上均匀淀积一聚合物层,再蚀刻聚合物层以在光阻层上形成聚合物侧壁间隙。然后蚀刻非导电层直至半导体基底,形成凹穴。在本发明中,光阻层开口侧壁的聚合物侧壁间隙可以用公知的光刻技术完成,并用以形成凹穴,例如接触窗或线间距。
Description
技术领域
本发明是有关于一种在微电子结构上形成接触窗的方法,特别是有关于一种利用形成于光阻层侧壁上的聚合物间隙壁,在半导体元件的非导电层上,形成较窄的接触窗,线间距,或沟槽。
背景技术
当今,半导体元件是建立在半导体的基底(例如硅基底)上,藉著在该基底上形成P型掺杂区及N型掺杂区,以做为元件的基本要件。将这些掺杂区经过特殊结构的连结后,便形成所要的电路。不过,这个电路必须要通过一般测试用的接触垫及通过连接到一封装之晶片,才能和外界连接。因此,在一个半导体电路中,至少要淀积及设定一导电层的图案(例如金属),以在晶片的不同区域间形成接触或者是内连线。例如,在典型的半导体工艺中,先是在晶体圆片上覆盖一绝缘层,接着在绝缘层上设定图案及蚀刻以形成接触开口,然后将导电材料淀积在接触开口内,形成接触插塞及内连线接点。
通常,和硅或者是硅化物连接的接触窗利用光刻及干蚀刻技术于绝缘层亦即介电层中形成。干蚀刻系各向异性蚀刻,用以确保所形成的接触窗能有较高的尺寸比以及较垂直的侧壁。之后,接触窗内填入导电材料(例如金属),形成和第一层金属的垂直接触。当然,接触窗也可以利用湿蚀刻技术来完成。湿蚀刻是将晶体圆片浸在适当的蚀刻液中或者是将蚀刻液喷洒在晶体圆片上。然而,湿蚀刻系各向同性蚀刻,亦即蚀刻会同时朝水平方向及垂直方向蚀刻。因此,水平方向的蚀刻会在掩膜的下端产生工艺中不必要的底沿。相反的,干蚀刻则是各向异性蚀刻。所以形成的接触窗,其接触窗在底端和顶端的宽度,可以几乎是一样大小的。并且由于干蚀刻不会产生底沿的问题,同时又不需要浪费额外的水平面积以做为接触窗,在现代亚微米元件中,大都使用干蚀刻技术。干蚀刻另外还提供了其他的优点,例如:减少化学危险、减少工艺步骤、使工艺步骤容易自动化、以及工具群集。目前最常使用的干蚀刻技术有等离子蚀刻技术及反应离子蚀刻技术。
虽然干蚀刻技术在控制元件尺寸的问题上获致重大的改进,也因此在VLSI及ULSI的工艺中广为使用,但干蚀刻仍然存在一些缺点。其中一点就是干蚀刻并无法缩小设定图案的尺寸。在现今的ULSI元件中,半导体元件无论是元件的水平尺寸,或者是元件的垂直尺寸都必须不断的缩小以达到元件密度持续增加的要求。因此能将元件尺寸缩小的工艺技术也就相形重要。而在晶片表面所能刻印的特征尺寸(Feature Size),即接触窗的大小、最小的线宽、或者是线间距,就直接地影响到晶片的密度。这也就是为什么大部分人在提到高密度晶片设计的革命时,通常指的就是用来缩小特征尺寸的光刻技术。
在主要的光刻技术中(光学、电子束、X射线、离子束),使用紫外线光源的光学光刻技术是最重要的一种。目前,最常使用在光学光刻中的紫外线光源有弧光灯光源及雷射光源。至于其所放射出来的光线,主要光谱则包括有深紫外线(波长在100~300nm之间),中紫外线(波长在300~360nm之间),以及近紫外线(波长在360~450nm之间)。比方说,当使用水银-氙弧光灯光源的时候,所释放的光线,其波长主要有深紫外线(DUV)、365nm(I-line)、450nm(H-line)、和436nm(G-line)。又既然,大部分使用的光阻材料,要能够适当的曝光,都需要有大于2.5eV的光子能量,因此也就只有波长436nm或者是波长更短的光线才能在这类光刻技术中使用。例如,当晶片表面所要刻印的特征尺寸大于2μm时,水银-氙弧光灯所释放的所有光线都可以用来使光阻层曝光,不过,当所要刻印的特征尺寸渐小的时候,就必须利用透镜及滤光镜来修正其中某一两组波长的光线,并将光谱中其他波长的光线移去。譬如,在光刻技术中要使光阻层曝光,G-line可以用在所要刻印的特征尺寸在约0.8μm的工艺中,I-line可以用在所要刻印的特征尺寸在约0.4~0.8μm的工艺中,至于波长更短的光(例如DUV中248nm的光线)则可以用在所要刻印的特征尺寸更小于0.4μm时的工艺里。
在目前VLSI的制造中,16M及容量更大的DRAM大都使用小于0.4μm的工艺技术(0.25μm的工艺技术),也就是说:其接触窗的直径,均在0.3μm以下。既然I-line只能在约0.4μm的工艺技术中使用,所以在制造16M及容量更大的DRAM时,就必须使用波长更短的DUV光线,以及更敏感的光阻材料。然而,不论是使用波长更短的DUV光线,或者是使用更敏感的DUV光阻材料,都将大大的提高半导体元件制造所需的成本。
图1及图2为公知的光刻过程,其利用光刻方法,以及蚀刻技术在介电屋中形成具有垂直侧壁的接触窗。图中介绍:此公知方法所形成接触窗的最小直径,其限制取决于I-line的波长。参考图1,半导体元件10具有一半导体基底12,而介电层14则淀积在半导体基底12之上。半导体基底12可以是硅基底,而介电层14则可以是二氧化硅层(SiO2)或者是四氮化三硅层(Si3N4)。
首先,在介电层14上淀积一光阻层16,然后,经设定图案在光阻层上形成开口20。其中,设定光阻层16的图案是利用紫外线I-line光源的光学光刻技术,且其所能刻印的特征尺寸被限制在0.4μm以上(参考图1)。参考图2,等到光阻层16经曝光形成开口20之后,再用干蚀刻技术在介电层14上蚀刻出一接触窗22,接触窗22的直径为A。因为干蚀刻技术(反应离子蚀刻技术)系各向异性蚀刻,所以形成的接触窗22具有垂直的侧壁,即接触窗22的底端和顶端具有几乎一样的直径,约在0.4μm左右。
不过,当要形成更小于0.4μm的接触窗时,本公知方法就必须以更困难的光刻技术,使用深紫外线波长的光线以及更敏感的光阻材料才能办到。
发明内容
因此本发明的主要目的是提供一种形成接触窗的方法,其接触窗可以比正常使用I-line光源的光刻技术所产生的接触窗,具有更小的直径。
本发明的另一目的在于提供一种在电子元件中形成更窄的凹穴的方法,其不需要再使用昂贵的深紫外线光刻技术以及深紫外线的光阻材料。
本发明的另一目的在于提供一种在半导体元件中形成更窄的凹穴的方法,其仅需在公知I-line光源的光刻技术工艺中做少许的调整。
本发明的又一目的在于提供一种在半导体元件中形成更窄的凹穴(例如接触窗或者是线间距)的方法,其利用在相同的反应条件(In-situ)下,在光阻层上形成聚合物侧壁间隙。
本发明的又一目的在于提供一种形成更窄的接触窗或线间距的方法,其利用光阻层上形成的聚合物侧壁间隙做掩膜,在半导体基底上的非导电层上蚀刻凹穴。
本发明的又一目的在于提供一种形成更窄的接触窗的方法,其利用反应气体以形成聚合物侧壁间隙,该反应气体类似于干蚀刻接触窗的过程中所使用的反应气体。
本发明的更一目的在于提供一种形成更窄的接触窗的方法,其可在同一个反应室中,在光阻层上形成一聚合物侧壁间隙,并用以在介电层上蚀刻接触窗。
本发明的再一目的在于提供一种形成更窄的接触窗的方法,其利用反应气体混合物,包括C4F8和CHF3,在光阻层上形成聚合物侧壁间隙。
为实现本发明的上述和其他目的,本发明提供一种在相同反应室中,利用光阻层上的聚合物侧壁间隙形成更窄的凹穴的方法。
本发明提供一种在半导体元件中形成更窄凹穴(例如:接触窗,线间距,沟槽)的方法。其利用在相同反应条件下,形成于光阻层上的聚合物侧壁间隙,来做为干蚀刻凹穴的掩膜。
根据本发明的一种在相同反应条件下利用形成于光阻层上的聚合物侧壁间隙以形成更窄凹穴的方法,其步骤为:先提供一半导体基底,在基底上淀积一非导电层,在非导电层上淀积并设定一光阻层的图案,以露出此非导电层欲用作凹穴的预定面积。然后淀积一聚合物层于光阻层及露出的非导电层上。各向异性蚀刻聚合物层以在光阻层侧壁上形成聚合物间隙壁,然后以此聚合物间隙壁为掩膜,蚀刻非导电层至露出半导体基底。
根据本明的一种在非导电层内形成凹穴的方法,其步骤为:先提供一半导体基底,在基底上淀积一非导电层,在非导电层上淀积并设定一光阻层的图案。然后均匀的淀积一聚合物层于非导电层及光阻层上,蚀刻聚合物层以在光阻层上形成聚合物侧壁间隙。然后在非导电层中蚀刻凹穴至露出半导体基底。
根据本发明的一种在同一个反应室中形成更窄接触窗的方法,其步骤为:先提供一硅基底,在硅基底上淀积一介电层,然后在介电层上淀积并设定一光阻层的图案,以露出介电层欲用做凹穴的第一开口。接着,均匀地淀积一聚合物层于光阻层及第一开口上,各向异性蚀刻聚合物层以在第一开口中形成聚合物侧壁间隙,其覆盖光阻层的侧壁。之后,用聚合物侧壁间隙做掩膜,各向异性蚀刻介电层直到硅基底上露出第二开口,此第二开口小于第一开口的大小。然后,从介电层上移去光阻层,形成更窄的接触窗。
附图说明
为让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举一较佳实施例,并配合附图,详细说明如下:
图1为公知半导体基底的放大剖面图,其中基底上有一介电层,介电层上设定一光阻层的图案。
图2示出图1的半导体元件,在该介电层上形成具有垂直侧壁的接触窗。
图3为本发明半导体基底的放大剖面图,其中基底上有一介电层,介电层上设定一光阻层的图案,在光阻层和介电层上均匀形成一聚合物层。
图4示出图3的半导体元件,在光阻层侧壁上形成聚合物侧壁间隙。
图5示出图4的半导体元件,以聚合物侧壁间隙为掩膜,经干蚀刻步骤形成接触窗。
具体实施方式
参考图3,其系半导体元件30的放大剖面图,半导体元件30乃建立在硅基底32上,并在硅基底23上形成一介电层34(例如:氧化层)。其中,该介电层34可以经过热氧化过程而形成,或者是适当的淀积其他的介电材料形成,例如氮化物或硼磷硅玻璃(BPSG,boro-phosphor-silicateglass)。介电层34亦可以淀积其他合适的介电材料,其厚度大约是在3000A和12000A之间。
为了在介电层34内形成凹穴(例如:接触窗,线间距,和沟槽),需要在介电层34上淀积一光阻层38。光阻层38系一种曝光材料,其可以使用于紫外线I-line波长的光学光刻技术中。接着,设定光阻层38的图案,曝露用以做为接触窗的开口42。此时,并不是象公知方法中,直接在介电层34中干蚀刻接触窗,而是在光阻层38上淀积聚合物层44。本发明的一新颖性即在于,聚合物层44可以在相同的反应室中(图中未示),很容易的淀积在光阻层38上,并且接着做下一步蚀刻的动作。聚合物层44因此具有可以在相同反应条件下淀积的优点。
其中,淀积聚合物层44的反应气体混合物可以是下一个蚀刻步骤中所使用的气体混合物,即由C4F8,CHF3,CO,以及Ar所组成的混合气体。一般淀积聚合物层44所使用的气体混合物比例是:20sccm的C4F8,80sccm的CHF3,140sccm的CO,以及100sccm的Ar。反应气体混合物可以选择性的加入40sccm的N2。当淀积过程是在反应离子蚀刻的反应室进行时,上电极维持在20℃,下电极维持在0℃,而反应室侧壁则维持在40℃。在反应室压力400mTorr时,提供500W的射频功率做一分钟的淀积。在这个环境下,聚合物层淀积的速率大约是3000A/min。
在聚合物层44的淀积过程中,要注意的是:聚合物层44乃均匀一致的覆盖在光阻层38的侧壁48以及开口42上,并且覆盖在介电层34上露出一面积52。在淀积过程中,聚合物层44的厚度和品质直接决定了所形成接触窗的直径。也就是说:如果聚合物层愈厚,相对的,所制造的聚合物侧壁间隙亦愈厚,故可以形成较窄的接触窗,其接触窗是由反应气体混合物的比例,加于反应室的功率,反应室的压力,以及氦冷却气体的流速来控制及决定。因此,本发明在淀积聚合物层的方法时,较公知制造接触窗的方法更具有工艺上的优点。藉由适当的调整上述处理工艺的参数,可以淀积较厚的聚合物层来制造更窄直径的接触窗,相反的,亦可以淀积较薄的聚合物层来制造更宽直径的接触窗。
本发明在工艺上的另一个优点是,使得淀积聚合物层的过程和反应离子蚀刻的过程可以在同一个反应室里执行。因为用于形成聚合物层的反应气体混合物相当类似于在介电层上蚀刻接触窗时,反应离子蚀刻中所使用的反应气体混合物。例如,在淀积和蚀刻过程中,反应气体混合物中的CHF3,N2,和Ar是一样的,差别仅在于蚀刻过程中,另外使用CF4,而在淀积过程中,则另外使用C4F8和CO。并且,由于反应气体混合物的相似,使得本发明得以简化在工艺中关于气体储存和气体输送的设备。
参考图4,等到在介电层34上形成聚合物层44之后,进行干蚀刻工艺以形成聚合物侧壁间隙48a。此时候,可以使用反应离子蚀刻技术,因为反应离子蚀刻技术可以非等向的仅将聚合物层44的顶端46(参考图3)以及淀积在介电层34面积52部分的聚合物材料蚀刻掉,并且将侧壁间隙48a完整留下。蚀刻气体混合物可以使用CF4,CHF3,N2,和Ar。在该间隙壁形成的步骤中,可以使用低功率、软去除过程(low power,softash process)。其适当的反应气体混合物系100sccm的CF4,25sccm的CHF3,10sccm的N2,和200sccm的Ar,其适当的反应室条件系200W功率,300m Torr的反应室压力。
参考图5,于是形成直径更窄的接触窗60。事实上,这个步骤相当于切换反应室的条件至氧化蚀刻工艺的环境(200m Torr的反应室压力;1200W的射频功率;25sccm的CF4;25sccm的CHF3;和300sccm的Ar),利用聚合物侧壁间隙48b做为掩膜,以蚀刻形成直径更窄的接触窗60。例如,一开始,接触窗56的开口直径大概在0.4~0.5μm之间(参考图4中的开口56),等到经过氧化干蚀刻工艺之后,会被放大到0.6μm左右(参考图5中的开口66)。此时,若是以聚合物侧壁间隙54为掩膜,特别是以该侧壁间隙48b底端的厚度为掩膜,则所形成的开口52直径可以减小到0.2~0.3μm之间。根据实际情形,在氧化干蚀刻工艺中所制造的接触窗60,其侧壁68会有点倾斜,而所形成接触窗60的底端面积64,其直径大概可以小到0.1~0.2μm。
待接触窗60形成之后(也可能是线间距或是沟槽),利用公知的方法,象是结合等离子氧化物去除法(oxide ashing process)和湿式清除法(wetcleaning),将光阻层38去除。如此半导体元件30可以准备好用来淀积导电层做接触插塞或下一个工艺步骤(图中未示)。
虽然本发明利用光阻层上形成的聚合物侧壁间隙,以形成更窄的接触窗已以一较佳实施例揭露如上,但值得注意的是,依据本发明的方法,亦可以提供下列几个工艺上的改进。首先,形成侧壁间隙的聚合物层可以在相同的反应条件下,和下一个干蚀刻步骤在同一个反应室中进行。这可以省下晶体圆片在不同反应室中转移的时间,并一并消除晶体圆片在转移过程中受污染的可能。其次,利用本发明的方法来制造直径更窄的接触窗,可以在不必使用昂贵的深紫外线光源及对应的深紫外线光阻材料的情况下,实现特征尺寸0.25μm甚至更小的工艺技术。因此本发明的实施,可以在既有晶体圆片厂的工艺中仅做少入场的调整便完成,因为在淀积聚合物侧壁间隙时所需的反应气体,和下一个干蚀刻步骤中所使用的反应气体基本上是相同的。
虽然本发明已以一些较佳实施例揭露如上,然其并非用以限定本发明,任何本领域的普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视后附之权利要求所界定者为准。
Claims (20)
1.一种在相同的反应条件下利用在光阻层侧壁上形成的聚合物间隙壁形成一凹穴的方法,其步骤包括:
提供一半导体基底,该半导体基底上覆盖有一非导电层;
在该非导电层上,淀积及设定一光阻层的图案,以在该非导电层上露出欲用于形成该凹穴的一预定面积;
淀积一聚合物层以覆盖该光阻层及该凹穴的预定面积;
各向异性蚀刻该聚合物层以形成该光阻层侧壁上的聚合物间隙壁;以及
蚀刻该非导电层直至露出该半导体基底,形成该凹穴。
2.如权利要求1所述的方法,其中所形成的该凹穴为接触窗,线间距,及沟槽中的一种。
3.如权利要求1所述的方法,其中该聚合物侧壁间隙以反应离子蚀刻技术形成。
4.如权利要求1所述的方法,其步骤更包括一将该光阻层从该非导电层上去除的步骤。
5.如权利要求1所述的方法,其中淀积该聚合物层所使用的反应气体,和在该非导电层上蚀刻该凹穴所使用的反应气体大致相同。
6.如权利要求1所述的方法,其中淀积该聚合物层所使用的反应气体系包括CHF3。
7.如权利要求1所述的方法,其中淀积该聚合物层所使用的反应气体系包括CHF3,C4F8,和CO。
8.如权利要求1所述的方法,其中使用该聚合物侧壁间隙为掩膜,以在该非导电层中形成凹穴。
9.如权利要求1所述的方法,其中该聚合物层的淀积步骤,形成该聚合物层的蚀刻步骤,以及该凹穴的蚀刻步骤是在同一个反应室中进行。
10.如权利要求1所述的方法,其中该非导电层中的该凹穴系经氧化干蚀刻步骤完成。
11.一种在非导电层内形成凹穴的方法,其步骤包括:
提供一半导体基底,在该半导体基底上淀积一非导电层;
在该非导电层上形成一经设定图案的光阻层;
均匀的淀积一聚合物层于该非导电层,以及该光阻层之上;
蚀刻该聚合物层以形成该光阻层上的聚合物侧壁间隙;以及
蚀刻该非导电层至露出该半导体基底,以形成该凹穴。
12.如权利要求11所述的方法,其中该非导电层由介电材料所形成。
13.如权利要求11所述的方法,其中该半导体基底为一硅基底。
14.如权利要求11所述的方法,其中该聚合物层及该非导电层系以干蚀刻技术形成。
15.如权利要求11所述的方法,其中形成的该凹穴为接触窗或线间距。
16.如权利要求11所述的方法,其中步骤还包括一利用等离子氧化物去除法和湿式清除法,将光阻层38去除的步骤。
17.如权利要求11所述的方法,其中形成于该非导电层内的该凹穴,其直径不大于0.5μm。
18.一种在单一反应室中形成一接触窗的方法,其步骤包括:
提供一硅基底;
淀积一介电层于该硅基底上;
淀积一光阻层于该介电层上;
设定该光阻层的图案以形成一第一开口至露出该介电层,用以制作该接触窗;
均匀的淀积一聚合物层于该第一开口及该光阻层上;
各向异性蚀刻该聚合物层,在该第一开口中形成一聚合物侧壁间隙,覆盖该光阻层;
以该些聚合物侧壁间隙为掩膜,各向异性蚀刻该介电层以形成一第二开口至露出该硅基底,其中该第二开口将会小于该第一开口,使更窄的接触窗得以形成;
从该介电层上移去该光阻层。
19.如权利要求18所述的方法,其中该第二开口的直径较该第一开口直径的一半更小。
20.如权利要求18所述的方法,其中该聚合物层是以一反应气体淀积,且该反应气体相似于各向异性蚀刻步骤中所使用的反应气体。
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US747273 | 1996-11-13 | ||
US08/747,273 US5895740A (en) | 1996-11-13 | 1996-11-13 | Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers |
Publications (2)
Publication Number | Publication Date |
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CN1188327A CN1188327A (zh) | 1998-07-22 |
CN1090815C true CN1090815C (zh) | 2002-09-11 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100437974C (zh) * | 2005-12-05 | 2008-11-26 | 力晶半导体股份有限公司 | 导线的制造方法以及缩小导线与图案间距的方法 |
CN101208787B (zh) * | 2005-06-28 | 2010-09-08 | 朗姆研究公司 | 使用蚀刻掩模堆叠的多掩模处理 |
Families Citing this family (85)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6225174B1 (en) * | 1996-06-13 | 2001-05-01 | Micron Technology, Inc. | Method for forming a spacer using photosensitive material |
US6429120B1 (en) * | 2000-01-18 | 2002-08-06 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
JPH10223615A (ja) * | 1997-02-12 | 1998-08-21 | Nitto Denko Corp | レジスト材と側壁保護膜との一括除去方法 |
TW370687B (en) * | 1998-04-21 | 1999-09-21 | United Microelectronics Corp | Manufacturing method for forming an opening with deep ultra-violet photoresist |
US6284656B1 (en) | 1998-08-04 | 2001-09-04 | Micron Technology, Inc. | Copper metallurgy in integrated circuits |
US6288442B1 (en) * | 1998-09-10 | 2001-09-11 | Micron Technology, Inc. | Integrated circuit with oxidation-resistant polymeric layer |
US6100014A (en) * | 1998-11-24 | 2000-08-08 | United Microelectronics Corp. | Method of forming an opening in a dielectric layer through a photoresist layer with silylated sidewall spacers |
US6291137B1 (en) * | 1999-01-20 | 2001-09-18 | Advanced Micro Devices, Inc. | Sidewall formation for sidewall patterning of sub 100 nm structures |
US6423475B1 (en) * | 1999-03-11 | 2002-07-23 | Advanced Micro Devices, Inc. | Sidewall formation for sidewall patterning of sub 100 nm structures |
US6316169B1 (en) * | 1999-06-25 | 2001-11-13 | Lam Research Corporation | Methods for reducing profile variation in photoresist trimming |
KR100327346B1 (ko) * | 1999-07-20 | 2002-03-06 | 윤종용 | 선택적 폴리머 증착을 이용한 플라즈마 식각방법 및 이를이용한 콘택홀 형성방법 |
DE19945140B4 (de) * | 1999-09-21 | 2006-02-02 | Infineon Technologies Ag | Verfahren zur Herstellung einer Maskenschicht mit Öffnungen verkleinerter Breite |
DE19950565A1 (de) * | 1999-10-20 | 2001-05-10 | Infineon Technologies Ag | Schichterzeugungsverfahren bei der Herstellung eines Halbleiterbauelements und Halbleiterbauelement |
US7211512B1 (en) * | 2000-01-18 | 2007-05-01 | Micron Technology, Inc. | Selective electroless-plated copper metallization |
US7262130B1 (en) | 2000-01-18 | 2007-08-28 | Micron Technology, Inc. | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals |
US6376370B1 (en) * | 2000-01-18 | 2002-04-23 | Micron Technology, Inc. | Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy |
US6420262B1 (en) * | 2000-01-18 | 2002-07-16 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US6277704B1 (en) * | 2000-05-24 | 2001-08-21 | Micron Technology, Inc. | Microelectronic device fabricating method, method of forming a pair of conductive device components of different base widths from a common deposited conductive layer |
US6674167B1 (en) * | 2000-05-31 | 2004-01-06 | Micron Technology, Inc. | Multilevel copper interconnect with double passivation |
US6423629B1 (en) * | 2000-05-31 | 2002-07-23 | Kie Y. Ahn | Multilevel copper interconnects with low-k dielectrics and air gaps |
US6569774B1 (en) * | 2000-08-31 | 2003-05-27 | Micron Technology, Inc. | Method to eliminate striations and surface roughness caused by dry etch |
CN100418011C (zh) * | 2001-01-08 | 2008-09-10 | 国际商业机器公司 | 微结构的制造方法 |
US6660456B2 (en) | 2001-06-27 | 2003-12-09 | International Business Machines Corporation | Technique for the size reduction of vias and other images in semiconductor chips |
US6569778B2 (en) * | 2001-06-28 | 2003-05-27 | Hynix Semiconductor Inc. | Method for forming fine pattern in semiconductor device |
US7125496B2 (en) * | 2001-06-28 | 2006-10-24 | Hynix Semiconductor Inc. | Etching method using photoresist etch barrier |
KR100429135B1 (ko) * | 2001-08-16 | 2004-04-28 | 동부전자 주식회사 | 반도체 소자의 섈로우 트렌치 분리 방법 |
US20030224254A1 (en) * | 2001-10-18 | 2003-12-04 | Macronix International Co., Ltd. | Method for reducing dimensions between patterns on a photomask |
US7361604B2 (en) * | 2001-10-18 | 2008-04-22 | Macronix International Co., Ltd. | Method for reducing dimensions between patterns on a hardmask |
CN100383667C (zh) * | 2002-02-08 | 2008-04-23 | 旺宏电子股份有限公司 | 半导体元件的图案转移的方法 |
US7122296B2 (en) * | 2002-03-05 | 2006-10-17 | Brewer Science Inc. | Lithography pattern shrink process and articles |
KR100473729B1 (ko) * | 2002-10-25 | 2005-03-10 | 매그나칩 반도체 유한회사 | 반도체 소자의 소자 분리막 형성 방법 |
TW575907B (en) * | 2002-12-24 | 2004-02-11 | Macronix Int Co Ltd | Patterning method for fabricating integrated circuit |
US7220665B2 (en) | 2003-08-05 | 2007-05-22 | Micron Technology, Inc. | H2 plasma treatment |
US7250371B2 (en) * | 2003-08-26 | 2007-07-31 | Lam Research Corporation | Reduction of feature critical dimensions |
CN1301547C (zh) * | 2003-12-10 | 2007-02-21 | 南亚科技股份有限公司 | 形成位元线接触窗的方法 |
US20050289159A1 (en) * | 2004-06-29 | 2005-12-29 | The Boeing Company | Web-enabled real-time link selection apparatus and method |
US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7655387B2 (en) | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
US20060134917A1 (en) * | 2004-12-16 | 2006-06-22 | Lam Research Corporation | Reduction of etch mask feature critical dimensions |
US7271107B2 (en) * | 2005-02-03 | 2007-09-18 | Lam Research Corporation | Reduction of feature critical dimensions using multiple masks |
US7465525B2 (en) * | 2005-05-10 | 2008-12-16 | Lam Research Corporation | Reticle alignment and overlay for multiple reticle process |
US7539969B2 (en) * | 2005-05-10 | 2009-05-26 | Lam Research Corporation | Computer readable mask shrink control processor |
US7429536B2 (en) | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7695632B2 (en) * | 2005-05-31 | 2010-04-13 | Lam Research Corporation | Critical dimension reduction and roughness control |
US7560390B2 (en) | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
CN100401152C (zh) * | 2005-08-15 | 2008-07-09 | 中华映管股份有限公司 | 图案化工艺与接触窗 |
US7273815B2 (en) * | 2005-08-18 | 2007-09-25 | Lam Research Corporation | Etch features with reduced line edge roughness |
US7829262B2 (en) | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7572572B2 (en) | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
KR100650859B1 (ko) | 2005-11-09 | 2006-11-27 | 주식회사 하이닉스반도체 | 반도체 소자의 미세패턴 형성방법 |
US20070154852A1 (en) * | 2005-12-29 | 2007-07-05 | Jeong Yel Jang | Method for patterning a thin film using a plasma by-product |
US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US8187483B2 (en) * | 2006-08-11 | 2012-05-29 | Jason Plumhoff | Method to minimize CD etch bias |
US7560360B2 (en) * | 2006-08-30 | 2009-07-14 | International Business Machines Corporation | Methods for enhancing trench capacitance and trench capacitor |
US7611980B2 (en) | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US7666578B2 (en) | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
US7309646B1 (en) * | 2006-10-10 | 2007-12-18 | Lam Research Corporation | De-fluoridation process |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8262920B2 (en) * | 2007-06-18 | 2012-09-11 | Lam Research Corporation | Minimization of mask undercut on deep silicon etch |
US8563229B2 (en) | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
US20090043646A1 (en) * | 2007-08-06 | 2009-02-12 | International Business Machines Corporation | System and Method for the Automated Capture and Clustering of User Activities |
US7737039B2 (en) | 2007-11-01 | 2010-06-15 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
KR20090050698A (ko) * | 2007-11-16 | 2009-05-20 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
US7803521B2 (en) * | 2007-11-19 | 2010-09-28 | International Business Machines Corporation | Photoresist compositions and process for multiple exposures with multiple layer photoresist systems |
US7659208B2 (en) | 2007-12-06 | 2010-02-09 | Micron Technology, Inc | Method for forming high density patterns |
US7790531B2 (en) | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
KR100933854B1 (ko) * | 2008-01-14 | 2009-12-24 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성방법 |
US8030218B2 (en) | 2008-03-21 | 2011-10-04 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
US7772122B2 (en) * | 2008-09-18 | 2010-08-10 | Lam Research Corporation | Sidewall forming processes |
US8492282B2 (en) | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
KR101732936B1 (ko) * | 2011-02-14 | 2017-05-08 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
CN103367224A (zh) * | 2012-03-31 | 2013-10-23 | 联华电子股份有限公司 | 在基板中形成沟槽的方法 |
CN103871868A (zh) * | 2012-12-11 | 2014-06-18 | 北大方正集团有限公司 | 一种直孔刻蚀方法 |
US9252183B2 (en) | 2013-01-16 | 2016-02-02 | Canon Kabushiki Kaisha | Solid state image pickup apparatus and method for manufacturing the same |
US8883648B1 (en) * | 2013-09-09 | 2014-11-11 | United Microelectronics Corp. | Manufacturing method of semiconductor structure |
US9159561B2 (en) | 2013-12-26 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for overcoming broken line and photoresist scum issues in tri-layer photoresist patterning |
US9679850B2 (en) * | 2015-10-30 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of fabricating semiconductor structure |
US20180323078A1 (en) * | 2015-12-24 | 2018-11-08 | Intel Corporation | Pitch division using directed self-assembly |
US10727045B2 (en) * | 2017-09-29 | 2020-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing a semiconductor device |
US10566194B2 (en) | 2018-05-07 | 2020-02-18 | Lam Research Corporation | Selective deposition of etch-stop layer for enhanced patterning |
US11398377B2 (en) * | 2020-01-14 | 2022-07-26 | International Business Machines Corporation | Bilayer hardmask for direct print lithography |
CN114336275B (zh) * | 2022-03-15 | 2023-02-21 | 度亘激光技术(苏州)有限公司 | 电极接触窗口的制作方法及半导体器件的制备方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4707218A (en) * | 1986-10-28 | 1987-11-17 | International Business Machines Corporation | Lithographic image size reduction |
US4838991A (en) * | 1987-10-30 | 1989-06-13 | International Business Machines Corporation | Process for defining organic sidewall structures |
US5420067A (en) * | 1990-09-28 | 1995-05-30 | The United States Of America As Represented By The Secretary Of The Navy | Method of fabricatring sub-half-micron trenches and holes |
US5296410A (en) * | 1992-12-16 | 1994-03-22 | Samsung Electronics Co., Ltd. | Method for separating fine patterns of a semiconductor device |
KR970007173B1 (ko) * | 1994-07-14 | 1997-05-03 | 현대전자산업 주식회사 | 미세패턴 형성방법 |
US5567658A (en) * | 1994-09-01 | 1996-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for minimizing peeling at the surface of spin-on glasses |
-
1996
- 1996-11-13 US US08/747,273 patent/US5895740A/en not_active Expired - Lifetime
-
1997
- 1997-08-28 CN CN97117756.2A patent/CN1090815C/zh not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101208787B (zh) * | 2005-06-28 | 2010-09-08 | 朗姆研究公司 | 使用蚀刻掩模堆叠的多掩模处理 |
CN100437974C (zh) * | 2005-12-05 | 2008-11-26 | 力晶半导体股份有限公司 | 导线的制造方法以及缩小导线与图案间距的方法 |
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US5895740A (en) | 1999-04-20 |
CN1188327A (zh) | 1998-07-22 |
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