CN108695230A - 具有二极管隔离的堆栈式纳米片场效应晶体管 - Google Patents

具有二极管隔离的堆栈式纳米片场效应晶体管 Download PDF

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CN108695230A
CN108695230A CN201810288229.8A CN201810288229A CN108695230A CN 108695230 A CN108695230 A CN 108695230A CN 201810288229 A CN201810288229 A CN 201810288229A CN 108695230 A CN108695230 A CN 108695230A
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semiconductor layer
layer
semiconductor
junction
isolated area
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CN108695230B (zh
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臧辉
李在坤
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GlobalFoundries US Inc
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Abstract

本发明揭露具有二极管隔离的堆栈式纳米片场效应晶体管，涉及场效应晶体管的结构及涉及场效应晶体管的结构的形成方法。提供具有第一导电类型的衬底。在该衬底上形成具有第二导电类型的第一半导体层。在该第一半导体层上形成具有第一导电类型的第二半导体层。形成场效应晶体管，其包括在该第二半导体层上的垂直堆栈中配置有多个纳米片通道层的鳍片、以及绕着该等纳米片通道层环绕的栅极结构。该第一半导体层与该衬底的一部分界定第一p‑n接面，并且该第二半导体层与该第一半导体层界定第二p‑n接面。该第一p‑n接面及该第二p‑n接面配置成与该栅极结构及该等纳米片通道层垂直对准。

Description

具有二极管隔离的堆栈式纳米片场效应晶体管
技术领域
本发明关于半导体装置制作及集成电路，并且更具体来说，关于涉及场效应晶体管的结构、以及涉及场效应晶体管的结构的形成方法。
背景技术
用于场效应晶体管的装置结构包括源极、漏极、位于该源极与漏极之间的通道、以与栅极结构，该栅极结构包括栅极电极、以及将该栅极电极与该通道分开的栅极介电质。施加至该栅极电极的栅极电压用于提供切换(switching)，透过该通道将该源极与漏极彼此选择性连接。平面型场效应晶体管的通道位于衬底(substrate)的顶端表面下方，其上支撑该栅极结构。
鳍式场效应晶体管(FinFET)是一种非平面型装置结构，可比平面型场效应晶体管更密集地受堆积于集成电路中。FinFET可包括鳍片，其由半导体材料的本体、形成于该本体的诸区段中的重度掺杂源极/漏极区、以及绕着位于该鳍片本体中介于该源极/漏极区之间的通道环绕的栅极电极所组成。介于该等栅极结构与鳍片本体之间的配置改良对该通道的控制，并且与平面型晶体管作比较，降低该FinFET处于其“断开(Off)”状态时的漏电流。这进而能够比在平面型晶体管中使用更低的阈值电压，并且导致效能改善且功率消耗降低。
堆栈式纳米线(nanowire)或纳米片(nanosheet)场效应晶体管已开发为可允许另外提升堆积密度的FinFET类型。堆栈式纳米片场效应晶体管可在纳米片通道区上形成有栅极堆栈的衬底上包括配置成三维阵列的多个纳米片。该栅极堆栈可将环绕式栅极配置中各纳米片的通道区的所有侧边围绕。
发明内容
在本发明的具体实施例中，一种方法包括提供具有第一导电类型的衬底、在该衬底上形成具有第二导电类型的第一半导体层、以及在该第一半导体层上形成具有该第一导电类型的第二半导体层。本方法更包括形成场效应晶体管的鳍片，其包括在该第二半导体层上配置成垂直堆栈的多个纳米片通道层，本方法还包括形成绕着该等纳米片通道层环绕的栅极结构。该第一半导体层与该衬底的一部分界定第一p-n接面(junction)，并且该第二半导体层与该第一半导体层界定第二p-n接面。该第一p-n接面及该第二p-n接面配置成与该栅极结构及该等纳米片通道层垂直对准。
在本发明的具体实施例中，一种结构包括衬底、位在该衬底上的第一半导体层、以及位在该第一半导体层上的第二半导体层。该衬底及该第二半导体层上具有第一导电类型，并且该第一半导体层具有第二导电类型。该第一半导体层垂直配置成与该衬底的一部分界定第一p-n接面，并且该第二半导体层垂直配置成与该第一半导体层界定第二p-n接面。该结构更包括位在该第二半导体层上的场效应晶体管。该场效应晶体管包括在垂直堆栈中配置有多个纳米片通道层的鳍片、以及绕着该等纳米片通道层环绕的栅极结构。该第一p-n接面及该第二p-n接面配置成与该栅极结构及该等纳米片通道层垂直对准。
在本发明的具体实施例中，一种结构包括具有第一导电类型的衬底、具有第二导电类型的半导体层、以及位在该半导体层上的场效应晶体管。该第一半导体层垂直配置成与该衬底的一部分界定p-n接面。该场效应晶体管包括在垂直堆栈中配置有多个纳米片通道层的鳍片、以及绕着该等纳米片通道层环绕的栅极结构。该p-n接面配置成与该栅极结构及该等纳米片通道层垂直对准。
附图说明
附图是合并于本说明书的一部分并构成该部分，绘示本发明的各项具体实施例，并且连同上述对本发明的一般性说明、及下文对具体实施例提供的详细说明，目的是为了阐释本发明的具体实施例。
图1至图5根据本发明的具体实施例，为一种装置结构在处理方法的接续阶段时的截面图。
图2A为该装置结构大体上在穿过诸栅极结构其中一者延展的平面中取看的截面图。
图6至图8根据本发明的替代具体实施例，为装置结构的截面图。
主要组件符号说明：
10 掺杂层
11 p-n接面
12 掺杂层
13 p-n接面
14 衬底
16 半导体层
18 牺牲半导体层
20 鳍片
21 n型井
22 沟槽隔离区
24 牺牲栅极结构
28 硬掩膜区段
30 间隔物
32 沟槽
34 介电质间隔物
36 沟槽隔离区
38 间隙填充层
40 源极/漏极区
42 功能性栅极结构
50 场效应晶体管
52 p-n接面
d0、dl 深度。
具体实施方式
请参阅图1，并且根据本发明的具体实施例，掺杂层10及掺杂层12位于衬底14上，掺杂层10垂直配置于掺杂层12与衬底14之间。衬底14可以是由单晶硅(single-crystalsilicon)、或绝缘体上覆半导体(semiconductor-on-insulator；SOI)衬底的硅装置层所组成的主体衬底。掺杂层10及掺杂层12各与衬底14具有磊晶关系，并且彼此具有磊晶关系，使得晶体结构都相同。
掺杂层12的半导体材料与掺杂层10的半导体材料具有相反导电性，并且在代表性具体实施例中，衬底14的半导体材料与掺杂层10的半导体材料亦具有相反类型。在一具体实施例中，掺杂层10的半导体材料可轻度掺杂有电活性掺质，诸如选自于周期表第五族(例如：磷(P)、砷(As)或锑(Sb))对于付与n型导电性有效的n型掺质，并且掺杂层12与衬底14的半导体材料可轻度掺杂有选自于周期表第三族(例如：硼(B))在浓度方面对于付与p型导电性有效的电活性掺质。掺杂层10及掺杂层12可通过衬底14的离子布植来形成，或可磊晶生长于衬底14上。
若掺杂层10、12是通过磊晶生长所形成，则衬底14的晶体结构为了生长掺杂层10与12的晶体结构而建立结晶模板。举例而言，掺杂层10与12可使用以范围自400℃至850℃的生长温度进行的低温磊晶(low temperature epitaxial；LTE)生长程序来形成，诸如气相磊晶术(vapor phase epitaxy；VPE)。掺杂层10、12的半导体材料可在生长至具有相反导电性类型期间予以原位掺杂。
若掺杂层10、12是通过离子布植所形成，授予一种导电性类型的含能离子受引穿过衬底14的顶端表面，并且大体上因能量损失而终止于该顶端表面下方的垂直深度上方以形成掺杂层12。授予相反导电性类型的含能离子受引穿过衬底14的顶端表面，并且大体上因能量损失而终止于该顶端表面下方的垂直深度上方以形成掺杂层10。在各实例中，该等离子可产生自合适的来源气体，并且使用离子布植工具以所选布植条件植入衬底14。布植条件(例如：离子种类、剂量、动能)可经选择以判定各掺杂层10、12的导电性及深度分布(例如：厚度)。
半导体层16与牺牲半导体层18是以交替串联方式在掺杂层12上形成为垂直堆栈。半导体层16可以是由诸如单晶硅(Si)的半导体材料所组成的纳米线或纳米片。牺牲半导体层18可由诸如硅锗(SiGe)的半导体材料所组成。半导体层16与18可由透过磊晶生长程序形成的单晶半导体材料所构成，并且至少该半导体层16可未经掺杂。牺牲半导体层18的半导体材料经选择而对半导体层16的半导体材料选择性遭受移除。“选择性”一词参照材料移除程序(例如：蚀刻)于本文中使用时，表示凭借选择适当的蚀刻剂，目标材料的材料移除率(即蚀刻率)大于经受材料移除程序的至少另一材料的移除率。半导体层16及牺牲半导体层18的数目可有别于代表性具体实施例中所示的数目。
请参阅图2、图2A，图中相似的参考组件符号是指图1中相似的特征，而在处理方法的后续制作阶段，鳍片20可通过光刻与蚀刻程序来形成，诸如侧壁影像移转(sidewallimaging transfer；SIT)程序或自对准双图案化(self-aligned double patterning；SADP)。鳍片20是由半导体层16与18的半导体材料所构成的三维本体，并且可与其它等同鳍片(图未示)配置成纵向平行列。鳍片20相对于掺杂层12的顶端表面顺着垂直方向凸出。
形成从掺杂层12的顶端表面起延展的沟槽隔离区22，其穿透掺杂层10与掺杂层12，并且进一步穿入衬底14至浅深度。沟槽隔离区22可由介电材料诸如硅的氧化物(例如：二氧化硅(SiO2))所组成，通过化学气相沉积(chemical vapor deposition；CVD)来沉积，并且回蚀至掺杂层12的顶端表面。
形成与鳍片20及沟槽隔离区22的外部表面重叠的牺牲栅极结构24。牺牲栅极结构24可由诸如多晶硅的半导体材料所组成，通过CVD来沉积并且利用反应性离子蚀刻(reactive ion etching；RIE)来图案化。由于图案化，牺牲栅极结构24可通过各别硬掩膜(hardmask)区段28来覆盖。间隔物(spacer)30位于与牺牲栅极结构24的垂直侧壁相邻处。间隔物30可由受沉积及异向性蚀刻的低k介电材料诸如碳氧化硅(SiOC)所组成。
请参阅图3，图中相似的参考组件符号是指图2中相似的特征，而在处理方法的后续制作阶段，形成从鳍片20的顶端表面延展穿过鳍片20、及掺杂层10、12两者进入衬底14至浅深度的沟槽32。沟槽32位于诸牺牲栅极结构24之间的间隔物中。沟槽32在掺杂层10、12及衬底14的各别部分相对于掺杂层12的顶端表面具有给定深度d0。
通过形成沟槽32使鳍片20的垂直侧壁曝露之后，利用对半导体层16选择性移除牺牲半导体层18的蚀刻程序使牺牲半导体层18凹陷。在介于半导体层16的诸相邻对之间的凹口中形成介电质间隔物34。介电质间隔物34可由介电材料诸如氮化硅(Si3N4)所组成，通过原子层沉积(atomic layer deposition；ALD)予以沉积于该等凹口中、及鳍片20的垂直侧壁与顶端表面上，并且通过等向性蚀刻程序诸如热磷酸蚀刻予以蚀刻，将不位于该等凹口内侧的介电材料移除。
请参阅图4，图中相似的参考组件符号是指图3中相似的特征，而在处理方法的后续制作阶段，沟槽32在掺杂层10、12与衬底14中的各别部分是以介电材料填充而形成沟槽隔离区36。构成沟槽隔离区36的介电材料可以是硅的氧化物(例如：二氧化硅(SiO2))，通过CVD来沉积，并且回蚀至掺杂层12的顶端表面。沟槽隔离区36符合掺杂层10、12与衬底14中沟槽32的形状。沟槽隔离区36从沟槽32的最大深度垂直延展至掺杂层12的顶端表面，并且因此延展至鳍片20的底端表面。结果是，沟槽隔离区36具有与沟槽32的最大深度相等的高度或厚度。沟槽隔离区36将各掺杂层10与12区分成多个区段。
场效应晶体管50的源极/漏极区40形成于诸牺牲栅极结构24之间所曝露的鳍片20的侧表面相邻处。源极/漏极区40位于沟槽隔离区36上，并且在沟槽隔离区36上面顺着垂直方向延展。“源极/漏极区”一词于本文中使用时，意为半导体材料的掺杂区，其可作用为场效应晶体管的源极或漏极。源极/漏极区40与半导体层16连接，并且通过介电质间隔物34与牺牲半导体层18实体隔离。至少部分由于沟槽32可提供自对准的关系，诸沟槽隔离区36其中一者与各源极/漏极区40对准。
构成源极/漏极区40的半导体材料可重度掺杂成具有p型导电性或n型导电性。在一具体实施例中，源极/漏极区40可通过选择性磊晶生长(selective epitaxial growth；SEG)程序来形成，其中半导体材料为了在半导体表面(例如：半导体层16)上磊晶生长而集结，但不为了从绝缘体表面(例如：硬掩膜区段28、间隔物30及沟槽隔离区36)开始磊晶生长而集结。
请参阅图5，图中相似的参考组件符号是指图4中相似的特征，而在处理方法的后续制作阶段，间隙填充层38经沉积及平坦化而与硬掩膜区段28共面。间隙填充层38可由透过CVD沉积的介电材料诸如二氧化硅(SiO2)所组成。在取代栅极程序中，牺牲栅极结构24及牺牲半导体层18遭受移除，并且以场效应晶体管50的功能性栅极结构42来取代。半导体层16界定场效应晶体管50的配置成垂直堆栈的纳米线或纳米片通道区。功能性栅极结构42的区段位于先前遭由已移除牺牲半导体层18占位的空间中，并且围绕环绕式栅极配置中的半导体层16，于该环绕式栅极配置中，绕着个别半导体层16环绕栅极结构的区段。
功能性栅极结构42可包含由诸如高k介电质的介电材料所组成的栅极介电层、由一或多个阻障金属层及/或诸如碳化钛铝(TiAlC)或氮化钛(TiN)等功函数金属层所组成的金属栅极电极、以及由诸如钨(W)的导体所组成的金属栅极填充层。该栅极介电层配置于该栅极电极与半导体层16之间。“牺牲栅极结构”一词于本文中使用时，是指供待随后形成的功能性栅极结构用的占位(placeholder)结构。“功能性栅极结构”一词于本文中使用时，是指用于对半导电性装置(semiconducting device)的输出电流(即通道中的载子流量)进行控制的永久栅极结构。
接着进行硅化(silicidation)、中段(middle-of-line；MOL)、及后段(back-end-of-line；BEOL)处理，其包括对上覆于装置结构的局部互连结构形成接触并进行配线，以及对通过互连配线与场效应晶体管50的功能性栅极结构42及源极/漏极区40耦接的互连结构形成介电层、贯孔插塞及配线。
掺杂层10及掺杂层12具有相反导电性类型，界定二极管的p-n接面11特性。掺杂层10与衬底14亦具有相反导电性类型，界定与其它二极管串联的二极管的p-n接面13。在一具体实施例中，掺杂层12与衬底14可由p型半导体材料所组成，并且掺杂层10可由n型半导体材料所组成。
通过p-n接面11、13所界定的这些背对背二极管与衬底14中的寄生通道电容以电串联方式连接，该寄生通道电容与场效应晶体管50的切换期间施加至功能性栅极结构42的电压相关联。有效电容等于寄生通道电容加二极管电容。由于引进的二极管电容大，有效电容比寄生通道电容小相当多。
掺杂层10、12及p-n接面11、13垂直配置于场效应晶体管50的半导体层16及功能性栅极结构42所界定的纳米片通道层下方。沟槽隔离区36仅垂直位于场效应晶体管50的源极/漏极区40下方，并且通过将p-n接面11、13区分成诸区段而中断p-n接面11、13的连续性。p-n接面11、13的区段是与各组功能性栅极结构42、及半导体层16所界定的纳米片通道层垂直对准而置。沟槽隔离区36为掺杂层10、12的侧缘建立侧向边界，并且为p-n接面11、13建立终止平面。p-n接面11、13位于比沟槽32、及沟槽32中沟槽隔离区36的最大深度更浅的各别深度处。
在一具体实施例中，场效应晶体管50可以是长通道装置，其中鳍片20具有长到足以可将鳍片20的侧边引起的边缘效应忽略的宽度与长度。
请参阅图6，其中相似的参考组件符号是指图5中相似的特征，并且根据本发明的具体实施例，可修改沟槽隔离区36及p-n接面13的配置，使得p-n接面13相对于沟槽隔离区36下方(即更深处)掺杂层12的顶端表面再定位至一深度。具体而言，可将p-n接面13定位于比深度d0(图3)更大的深度dl处。在一具体实施例中，可增加掺杂层10顺着垂直方向的高度或厚度以提供该修改。在一具体实施例中，可将沟槽32修改成仅部分穿过掺杂层10延展，从而因为穿透深度更浅而未穿入衬底14。
请参阅图7，其中相似的参考组件符号是指图5中相似的特征，而且根据本发明的具体实施例，可将掺杂层10从该结构排除，并且衬底14的半导体材料的导电性类型可经选择而与掺杂层12的半导体材料的导电性类型相反。衬底14的突指(finger)部分在相邻沟槽隔离36之间垂直延展，以与水平位于相邻沟槽隔离36之间的掺杂层12的相关联区段参与形成p-n接面52。仅存在单一p-n接面52，故而提供单一二极管，该二极管与衬底14中的寄生通道电容以电串联方式连接，该寄生通道电容与场效应晶体管50的切换期间施加至功能性栅极结构42的电压相关联。
在一具体实施例中，可将掺杂层12的半导体材料掺杂成具有p型导电性，并且可将衬底14的半导体材料掺杂成具有n型导电性。具有此一垂直导电性类型配置的掺杂层12与衬底14对于p型的场效应晶体管50尤其适用。在一具体实施例中，可将掺杂层12的半导体材料掺杂成具有n型导电性，并且可将衬底14的半导体材料掺杂成具有p型导电性。具有此一垂直导电性类型配置的掺杂层12与衬底14对于n型的场效应晶体管50尤其适用。
请参阅图8，其中相似的参考组件符号是指图5中相似的特征，而且根据本发明的具体实施例，可将掺杂层10的半导体材料掺杂成具有p型导电性，可将掺杂层12的半导体材料掺杂成具有n型导电性，并且可将掺杂层10定位于p型衬底14中通过例如离子布植所形成的n型井(well)21的半导体材料中。
本方法如以上所述，用于制作集成电路芯片。产生的集成电路芯片可由制作商以空白晶圆形式(例如：作为具有多个未封装芯片的单一晶圆)、当作裸晶粒、或以封装形式来配送。在后例中，芯片嵌装于单芯片封装(例如：塑料载体，有导线黏贴至主板或其它更高层阶载体)中、或多芯片封装(例如：具有表面互连或埋置型互连任一者或两者的陶瓷载体)中。无论如何，芯片可与其它芯片、离散电路组件、及/或其它信号处理装置整合，作为中间产品或或最终产品的部分。
本文中对“垂直”、“水平”、“侧向”等用语的参照属于举例，并非限制，用来建立参考架构。诸如“水平”与“侧向”等用语是指平面中与半导体衬底的顶端表面平行的方向，与其实际三维空间方位无关。诸如“垂直”与“正交”等用语是指与“水平”及“侧向”方向垂直的方向。诸如“上面”及“下面”等用语指出组件或结构彼此的相对位置，及/或与半导体衬底的顶端表面相对的位置，与相对高度截然不同。
“连接”或“耦接”至另一组件、或与该另一组件“连接”或“耦接”的特征可直接连接或耦接至其它组件，或者，转而可出现一或多个中介组件。如无中介组件，一特征可“直接连接”或“直接耦接”至另一组件。如有至少一个中介组件，一特征可“间接连接”或“间接耦接”至另一组件。
本发明的各项具体实施例的描述已为了说明目的而介绍，但用意不在于穷举或受限于所揭示的具体实施例。许多修改及变例对所属领域技术人员将会显而易见，但不会脱离所述具体实施例的范畴及精神。本文中使用的术语是为了最佳阐释具体实施例的原理、对市场出现的技术所作的实务应用或技术改良、或让所属领域技术人员能够理解本文中所揭示的具体实施例而选择。

Claims (20)

1.一种结构，其包含：
层堆栈，其包括具有第一导电类型的第一半导体层及具有第二导电类型的第二半导体层，该第一半导体层垂直配置成与该第二半导体层界定第一p-n接面；以及
位在该第一半导体层上的场效应晶体管，该场效应晶体管包括在垂直堆栈中配置有多个纳米片通道层的鳍片、及绕着该纳米片通道层环绕的栅极结构，
其中，该第一p-n接面配置成与该栅极结构及该纳米片通道层垂直对准。
2.如权利要求1所述的结构，更包含：
穿过该第一半导体层及该第一p-n接面延展的第一沟槽隔离区；以及
穿过该第一半导体层及该第一p-n接面延展的第二沟槽隔离区，该第二沟槽隔离区与该第一沟槽隔离区水平相隔，
其中，该第一p-n接面水平配置于该第一沟槽隔离区与该第二沟槽隔离区之间。
3.如权利要求2所述的结构，其中，该第二半导体层为半导体衬底。
4.如权利要求2所述的结构，其中，该层堆栈包括具有该第一导电类型的第三半导体层，该第二半导体层垂直配置于该第一半导体层与该第三半导体层之间，并且该第三半导体层与该第二半导体层界定第二p-n接面。
5.如权利要求4所述的结构，其中，该第一沟槽隔离区及该第二沟槽隔离区各穿过该第二半导体层及该第二p-n接面延展至该第三半导体层内，并且该第二p-n接面水平配置于该第一沟槽隔离区与该第二沟槽隔离区之间。
6.如权利要求4所述的结构，其中，该第三半导体层为半导体衬底。
7.如权利要求4所述的结构，其中，该第三半导体层为位在半导体衬底中的井体。
8.如权利要求4所述的结构，其中，该第一沟槽隔离区及该第二沟槽隔离区相对于该第一半导体层的顶端表面延展至第一深度，该第二p-n接面相对于该第一半导体层的该顶端表面位于第二深度处，并且该第二深度大于该第一深度。
9.如权利要求2所述的结构，其中，该场效应晶体管包括第一源极/漏极区及第二源极/漏极区，该栅极结构及该纳米片通道层水平配置于该第一源极/漏极区与该第二源极/漏极区之间，该第一源极/漏极区配置成与该第一沟槽隔离区垂直对准，并且该第二源极/漏极区配置成与该第二沟槽隔离区垂直对准。
10.如权利要求1所述的结构，其中，该第二半导体层为半导体衬底。
11.如权利要求1所述的结构，其中，该层堆栈包括具有该第一导电类型的第三半导体层，该第二半导体层垂直配置于该第一半导体层与该第三半导体层之间，并且该第三半导体层与该第二半导体层界定第二p-n接面。
12.如权利要求11所述的结构，其中，该第三半导体层为半导体衬底。
13.如权利要求11所述的结构，其中，该第三半导体层为位在半导体衬底中的井体。
14.一种方法，其包含：
形成层堆栈，其包括具有第一导电类型的第一半导体层及具有第二导电类型的第二半导体层，该第一半导体层垂直配置成与该第二半导体层界定第一p-n接面；以及
形成位在该第一半导体层上的场效应晶体管，该场效应晶体管包括在垂直堆栈中配置有多个纳米片通道层的鳍片、及绕着该纳米片通道层环绕的栅极结构，
其中，该第一p-n接面配置成与该栅极结构及该纳米片通道层垂直对准。
15.如权利要求14所述的方法，更包含：
形成穿过该第一半导体层及该第一p-n接面延展的第一沟槽隔离区；以及
形成穿过该第一半导体层及该第一p-n接面延展的第二沟槽隔离区，
其中，该第二沟槽隔离区与该第一沟槽隔离区水平相隔，并且该第一p-n接面水平配置于该第一沟槽隔离区与该第二沟槽隔离区之间。
16.如权利要求15所述的方法，其中，该层堆栈包括具有该第一导电类型的第三半导体层，该第二半导体层垂直配置于该第一半导体层与该第三半导体层之间，并且该第三半导体层与该第二半导体层界定第二p-n接面。
17.如权利要求16所述的方法，其中，该第一沟槽隔离区及该第二沟槽隔离区各穿过该第二半导体层及该第二p-n接面延展至该第三半导体层内，并且该第二p-n接面水平配置于该第一沟槽隔离区与该第二沟槽隔离区之间。
18.如权利要求16所述的方法，其中，该第一沟槽隔离区及该第二沟槽隔离区相对于该第一半导体层的顶端表面延展至第一深度，该第二p-n接面相对于该第一半导体层的该顶端表面位于第二深度处，并且该第二深度大于该第一深度。
19.如权利要求14所述的方法，其中，该层堆栈包括具有该第一导电类型的第三半导体层，该第二半导体层垂直配置于该第一半导体层与该第三半导体层之间，并且该第三半导体层与该第二半导体层界定第二p-n接面。
20.如权利要求19所述的方法，其中，该第三半导体层为半导体衬底、或位在该半导体衬底中的井体。
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