TW201901960A - 具有二極體隔離之堆疊奈米片場效電晶體 - Google Patents

具有二極體隔離之堆疊奈米片場效電晶體 Download PDF

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TW201901960A
TW201901960A TW107105262A TW107105262A TW201901960A TW 201901960 A TW201901960 A TW 201901960A TW 107105262 A TW107105262 A TW 107105262A TW 107105262 A TW107105262 A TW 107105262A TW 201901960 A TW201901960 A TW 201901960A
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semiconductor layer
trench isolation
junction
isolation region
layer
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輝 臧
李在坤
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明揭露涉及場效電晶體的結構及涉及場效電晶體的結構的形成方法。提供具有第一導電類型的基板。在該基板上形成具有第二導電類型的第一半導體層。在該第一半導體層上形成具有第一導電類型的第二半導體層。形成場效電晶體，其包括在該第二半導體層上的垂直堆疊中配置有多個奈米片通道層的鰭片、以及繞著該等奈米片通道層環繞的閘極結構。該第一半導體層與該基板的一部分界定第一p-n接面，並且該第二半導體層與該第一半導體層界定第二p-n接面。該第一p-n接面及該第二p-n接面配置成與該閘極結構及該等奈米片通道層垂直對準。

Description

具有二極體隔離之堆疊奈米片場效電晶體
本發明關於半導體裝置製作及積體電路，並且更具體來說，關於涉及場效電晶體的結構、以及涉及場效電晶體的結構的形成方法。
用於場效電晶體的裝置結構包括源極、汲極、位於該源極與汲極之間的通道、以與閘極結構，該閘極結構包括閘極電極、以及將該閘極電極與該通道分開的閘極介電質。施加至該閘極電極的閘極電壓用於提供切換(switching)，透過該通道將該源極與汲極彼此選擇性連接。平面型場效電晶體的通道位於基板(substrate)的頂端表面下方，其上支撐該閘極結構。
鰭式場效電晶體(FinFET)是一種非平面型裝置結構，可比平面型場效電晶體更密集地受堆積於積體電路中。FinFET可包括鰭片，其由半導體材料的本體、形成於該本體的諸區段中的重度摻雜源極/汲極區、以及繞著位於該鰭片本體中介於該源極/汲極區之間的通道環繞的閘極電極所組成。介於該等閘極結構與鰭片本體之間的配 置改良對該通道的控制，並且與平面型電晶體作比較，降低該FinFET處於其“斷開(Off)”狀態時的漏電流。這進而能夠比在平面型電晶體中使用更低的閾值電壓，並且導致效能改善且功率消耗降低。
堆疊式奈米線(nanowire)或奈米片(nanosheet)場效電晶體已開發為可允許另外提升堆積密度的FinFET類型。堆疊式奈米片場效電晶體可在奈米片通道區上形成有閘極堆疊的基板上包括配置成三維陣列的多個奈米片。該閘極堆疊可將環繞式閘極配置中各奈米片的通道區的所有側邊圍繞。
在本發明的具體實施例中，一種方法包括提供具有第一導電類型的基板、在該基板上形成具有第二導電類型的第一半導體層、以及在該第一半導體層上形成具有該第一導電類型的第二半導體層。本方法更包括形成場效電晶體的鰭片，其包括在該第二半導體層上配置成垂直堆疊的多個奈米片通道層，本方法還包括形成繞著該等奈米片通道層環繞的閘極結構。該第一半導體層與該基板的一部分界定第一p-n接面(junction)，並且該第二半導體層與該第一半導體層界定第二p-n接面。該第一p-n接面及該第二p-n接面配置成與該閘極結構及該等奈米片通道層垂直對準。
在本發明的具體實施例中，一種結構包括基板、位在該基板上的第一半導體層、以及位在該第一半 導體層上的第二半導體層。該基板及該第二半導體層上具有第一導電類型，並且該第一半導體層具有第二導電類型。該第一半導體層垂直配置成與該基板的一部分界定第一p-n接面，並且該第二半導體層垂直配置成與該第一半導體層界定第二p-n接面。該結構更包括位在該第二半導體層上的場效電晶體。該場效電晶體包括在垂直堆疊中配置有多個奈米片通道層的鰭片、以及繞著該等奈米片通道層環繞的閘極結構。該第一p-n接面及該第二p-n接面配置成與該閘極結構及該等奈米片通道層垂直對準。
在本發明的具體實施例中，一種結構包括具有第一導電類型的基板、具有第二導電類型的半導體層、以及位在該半導體層上的場效電晶體。該第一半導體層垂直配置成與該基板的一部分界定p-n接面。該場效電晶體包括在垂直堆疊中配置有多個奈米片通道層的鰭片、以及繞著該等奈米片通道層環繞的閘極結構。該p-n接面配置成與該閘極結構及該等奈米片通道層垂直對準。
10、12‧‧‧摻雜層
11、13、52‧‧‧p-n接面
14‧‧‧基板
16‧‧‧半導體層
18‧‧‧犧性半導體層、半導體層
20‧‧‧鰭片
21‧‧‧n型井
22‧‧‧溝槽隔離區
24‧‧‧犧性閘極結構
28‧‧‧硬遮罩區段
30‧‧‧間隔物
32‧‧‧溝槽
34‧‧‧介電質間隔物
36‧‧‧溝槽隔離區、溝槽隔離
38‧‧‧間隙填充層
40‧‧‧源極/汲極區
42‧‧‧功能性閘極結構
50‧‧‧場效電晶體
d0、dl‧‧‧深度
附圖是合併於本說明書的一部分並構成該部分，繪示本發明的各項具體實施例，並且連同上述對本發明的一般性說明、及下文對具體實施例提供的詳細說明，目的是為了闡釋本發明的具體實施例。
第1圖至第5圖根據本發明的具體實施例，為一種裝置結構在處理方法的接續階段時的截面圖。
第2A圖為該裝置結構大體上在穿過諸閘極 結構其中一者延展的平面中取看的截面圖。
第6圖至第8圖為根據本發明的替代具體實施例的裝置結構的截面圖。
請參閱第1圖，並且根據本發明的具體實施例，摻雜層10及摻雜層12位於基板14上，摻雜層10垂直配置於摻雜層12與基板14之間。基板14可以是由單晶矽(single-crystal silicon)、或絕緣體上覆半導體(semiconductor-on-insulator；SOI)基板的矽裝置層所組成的主體基板。摻雜層10及摻雜層12各與基板14具有磊晶關係，並且彼此具有磊晶關係，使得晶體結構都相同。
摻雜層12的半導體材料與摻雜層10的半導體材料具有相反導電性，並且在代表性具體實施例中，基板14的半導體材料與摻雜層10的半導體材料亦具有相反類型。在一具體實施例中，摻雜層10的半導體材料可輕度摻雜有電活性摻質，諸如選自於週期表第五族(例如：磷(P)、砷(As)或銻(Sb))有效賦予n型導電性的n型摻質，並且摻雜層12與基板14的半導體材料可輕度摻雜有選自於週期表第三族(例如：硼(B))在濃度方面有效賦予p型導電性的電活性摻質。摻雜層10及摻雜層12可通過基板14的離子佈植來形成，或可磊晶生長於基板14上。
若摻雜層10、12是通過磊晶生長所形成，則基板14的晶體結構為了生長摻雜層10與12的晶體結構而建立結晶範本。舉例而言，摻雜層10與12可使用以範 圍自400℃至850℃的生長溫度進行的低溫磊晶(low temperature epitaxial；LTE)生長程序來形成，諸如氣相磊晶術(vapor phase epitaxy；VPE)。摻雜層10、12的半導體材料可在生長至具有相反導電性類型期間予以原位摻雜。
若摻雜層10、12是通過離子佈植所形成，則賦予一種導電性類型的含能離子受導引穿過基板14的頂端表面，然後通常會因能量損失而停在該頂端表面下方的垂直深度上方以形成摻雜層12。授予相反導電性類型的含能離子受導引穿過基板14的頂端表面，然後通常會因能量損失而停在該頂端表面下方的垂直深度上方以形成摻雜層10。在各實例中，該等離子可產生自合適的來源氣體，並且使用離子佈植工具以所選佈植條件植入基板14。佈植條件(例如：離子種類、劑量、動能)可經選擇以判定各摻雜層10、12的導電性及深度分佈(例如：厚度)。
半導體層16與犧牲半導體層18是以交替串聯方式在摻雜層12上形成為垂直堆疊。半導體層16可以是由諸如單晶矽(Si)的半導體材料所組成的奈米線或奈米片。犧牲半導體層18可由諸如矽鍺(SiGe)的半導體材料所組成。半導體層16與18可由透過磊晶生長程序形成的單晶半導體材料所構成，並且至少該半導體層16可未經摻雜。犧牲半導體層18的半導體材料經選擇而對半導體層16的半導體材料選擇性遭受移除。“選擇性”一詞參照材料移除程序(例如：蝕刻)於本文中使用時，表示憑藉選擇適當的蝕刻劑，目標材料的材料移除率(即蝕刻率)大於經受 材料移除程序的至少另一材料的移除率。半導體層16及犧牲半導體層18的數目可有別於代表性具體實施例中所示的數目。
請參閱第2圖、第2A圖，圖中相同的參考元件符號是指第1圖中相似的特徵，而在處理方法的後續製作階段，鰭片20可通過光微影與蝕刻程序來形成，諸如側壁影像移轉(sidewall imaging transfer；SIT)程序或自對準雙圖案化(self-aligned double patterning；SADP)。鰭片20是由半導體層16與18的半導體材料所構成的三維本體，並且可與其它等同鰭片(圖未示)配置成縱向平行列。鰭片20相對於摻雜層12的頂端表面順著垂直方向凸出。
形成從摻雜層12的頂端表面起延展的溝槽隔離區22，其穿透摻雜層10與摻雜層12，並且進一步穿入基板14至淺深度。溝槽隔離區22可由介電材料諸如矽的氧化物(例如：二氧化矽(SiO2))所組成，通過化學氣相沉積(chemical vapor deposition；CVD)來沉積，並且回蝕至摻雜層12的頂端表面。
形成與鰭片20及溝槽隔離區22的外部表面重疊的犧牲閘極結構24。犧牲閘極結構24可由諸如多晶矽的半導體材料所組成，通過CVD來沉積並且利用反應性離子蝕刻(reactive ion etching；RIE)來圖案化。由於圖案化，犧牲閘極結構24可通過各別硬遮罩(hardmask)區段28來覆蓋。間隔物(spacer)30位於與犧牲閘極結構24的垂直側壁相鄰處。間隔物30可由受沉積及非等向性蝕刻 的低k介電材料諸如碳氧化矽(SiOC)所組成。
請參閱第3圖，圖中相同的參考元件符號是指第2圖中相似的特徵，而在處理方法的後續製作階段，形成從鰭片20的頂端表面延展穿過鰭片20、及摻雜層10、12兩者進入基板14至淺深度的溝槽32。溝槽32位於諸犧牲閘極結構24之間的間隔物中。溝槽32在摻雜層10、12及基板14的各別部分相對於摻雜層12的頂端表面具有給定深度d0。
通過形成溝槽32使鰭片20的垂直側壁曝露之後，利用對半導體層16選擇性移除犧牲半導體層18的蝕刻程序使犧牲半導體層18凹陷。在介於半導體層16的諸相鄰對之間的凹口中形成介電質間隔物34。介電質間隔物34可由介電材料諸如氮化矽(Si3N4)所組成，通過原子層沉積(atomic layer deposition；ALD)予以沉積於該等凹口中、及鰭片20的垂直側壁與頂端表面上，並且通過等向性蝕刻程序諸如熱磷酸蝕刻予以蝕刻，將不位於該等凹口內側的介電材料移除。
請參閱第4圖，圖中相同的參考元件符號是指第3圖中相似的特徵，而在處理方法的後續製作階段，溝槽32在摻雜層10、12與基板14中的各別部分是以介電材料填充而形成溝槽隔離區36。構成溝槽隔離區36的介電材料可以是矽的氧化物(例如：二氧化矽(SiO2))，通過CVD來沉積，並且回蝕至摻雜層12的頂端表面。溝槽隔離區36符合摻雜層10、12與基板14中溝槽32的形狀。 溝槽隔離區36從溝槽32的最大深度垂直延展至摻雜層12的頂端表面，並且因此延展至鰭片20的底端表面。結果是，溝槽隔離區36具有與溝槽32的最大深度相等的高度或厚度。溝槽隔離區36將各摻雜層10與12區分成多個區段。
場效電晶體50的源極/汲極區40形成於諸犧牲閘極結構24之間所曝露的鰭片20的側表面相鄰處。源極/汲極區40位於溝槽隔離區36上，並且在溝槽隔離區36上面順著垂直方向延展。“源極/汲極區”一詞於本文中使用時，意為半導體材料的摻雜區，其可作用為場效電晶體的源極或汲極。源極/汲極區40與半導體層16連接，並且通過介電質間隔物34與犧牲半導體層18實體隔離。至少部分由於溝槽32可提供自對準的關係，諸溝槽隔離區36其中一者與各源極/汲極區40對準。
構成源極/汲極區40的半導體材料可重度摻雜成具有p型導電性或n型導電性。在一具體實施例中，源極/汲極區40可通過選擇性磊晶生長(selective epitaxial growth；SEG)程序來形成，其中半導體材料為了在半導體表面(例如：半導體層16)上磊晶生長而集結，但不為了從絕緣體表面(例如：硬遮罩區段28、間隔物30及溝槽隔離區36)開始磊晶生長而集結。
請參閱第5圖，圖中相同的參考元件符號是指第4圖中相似的特徵，而在處理方法的後續製作階段，間隙填充層38經沉積及平坦化而與硬遮罩區段28共 面。間隙填充層38可由透過CVD沉積的介電材料諸如二氧化矽(SiO2)所組成。在取代閘極程序中，犧牲閘極結構24及犧牲半導體層18遭受移除，並且以場效電晶體50的功能性閘極結構42來取代。半導體層16界定場效電晶體50的配置成垂直堆疊的奈米線或奈米片通道區。功能性閘極結構42的區段位於先前遭由已移除犧牲半導體層18占位的空間中，並且圍繞環繞式閘極配置中的半導體層16，於該環繞式閘極配置中，繞著個別半導體層16環繞閘極結構的區段。
功能性閘極結構42可包含由諸如高k介電質的介電材料所組成的閘極介電層、由一或多個阻障金屬層及/或諸如碳化鈦鋁(TiAlC)或氮化鈦(TiN)等功函數金屬層所組成的金屬閘極電極、以及由諸如鎢(W)的導體所組成的金屬閘極填充層。該閘極介電層配置於該閘極電極與半導體層16之間。“犧牲閘極結構”一詞於本文中使用時，是指供待隨後形成的功能性閘極結構用的占位(placeholder)結構。“功能性閘極結構”一詞於本文中使用時，是指用於對半導電性裝置(semiconducting device)的輸出電流(即通道中的載子流量)進行控制的永久閘極結構。
接著進行矽化(silicidation)、中段(middle-of-line；MOL)、及後段(back-end-of-line；BEOL)處理，其包括對上覆於裝置結構的局部互連結構形成接觸並進行配線，以及對通過互連配線與場效電晶體50的功能性閘極結構42及源極/汲極區40耦接的互連結構形成介電 層、貫孔插塞及配線。
摻雜層10及摻雜層12具有相反導電性類型，界定二極體的p-n接面11特性。摻雜層10與基板14亦具有相反導電性類型，界定與其它二極體串聯的二極體的p-n接面13。在一具體實施例中，摻雜層12與基板14可由p型半導體材料所組成，並且摻雜層10可由n型半導體材料所組成。
通過p-n接面11、13所界定的這些背對背二極體與基板14中的寄生通道電容以電串聯方式連接，該寄生通道電容與場效電晶體50的切換期間施加至功能性閘極結構42的電壓相關聯。有效電容等於寄生通道電容加二極體電容。由於引進的二極體電容大，有效電容比寄生通道電容小相當多。
摻雜層10、12及p-n接面11、13垂直配置於場效電晶體50的半導體層16及功能性閘極結構42所界定的奈米片通道層下方。溝槽隔離區36僅垂直位於場效電晶體50的源極/汲極區40下方，並且通過將p-n接面11、13區分成諸區段而中斷p-n接面11、13的連續性。p-n接面11、13的區段是與各組功能性閘極結構42、及半導體層16所界定的奈米片通道層垂直對準而置。溝槽隔離區36為摻雜層10、12的側緣建立側向邊界，並且為p-n接面11、13建立終止平面。p-n接面11、13位於比溝槽32、及溝槽32中溝槽隔離區36的最大深度更淺的各別深度處。
在一具體實施例中，場效電晶體50可以是 長通道裝置，其中鰭片20具有長到足以可將鰭片20的側邊引起的邊緣效應忽略的寬度與長度。
請參閱第6圖，其中相同的參考元件符號是指第5圖中相似的特徵，並且根據本發明的具體實施例，可修改溝槽隔離區36及p-n接面13的配置，使得p-n接面13相對於溝槽隔離區36下方(即更深處)摻雜層12的頂端表面再定位至一深度。具體而言，可將p-n接面13定位於比深度d0(第3圖)更大的深度dl處。在一具體實施例中，可增加摻雜層10順著垂直方向的高度或厚度以提供該修改。在一具體實施例中，可將溝槽32修改成僅部分穿過摻雜層10延展，從而因為穿透深度更淺而未穿入基板14。
請參閱第7圖，其中相同的參考元件符號是指第5圖中相似的特徵，而且根據本發明的具體實施例，可將摻雜層10從該結構排除，並且基板14的半導體材料的導電性類型可經選擇而與摻雜層12的半導體材料的導電性類型相反。基板14的突指(finger)部分在相鄰溝槽隔離36之間垂直延展，以與水平位於相鄰溝槽隔離36之間的摻雜層12的相關聯區段參與形成p-n接面52。僅存在單一p-n接面52，故而提供單一二極體，該二極體與基板14中的寄生通道電容以電串聯方式連接，該寄生通道電容與場效電晶體50的切換期間施加至功能性閘極結構42的電壓相關聯。
在一具體實施例中，可將摻雜層12的半導體材料摻雜成具有p型導電性，並且可將基板14的半導體 材料摻雜成具有n型導電性。具有此一垂直導電性類型配置的摻雜層12與基板14對於p型的場效電晶體50尤其適用。在一具體實施例中，可將摻雜層12的半導體材料摻雜成具有n型導電性，並且可將基板14的半導體材料摻雜成具有p型導電性。具有此一垂直導電性類型配置的摻雜層12與基板14對於n型的場效電晶體50尤其適用。
請參閱第8圖，其中相同的參考元件符號是指第5圖中相似的特徵，而且根據本發明的具體實施例，可將摻雜層10的半導體材料摻雜成具有p型導電性，可將摻雜層12的半導體材料摻雜成具有n型導電性，並且可將摻雜層10定位於p型基板14中通過例如離子佈植所形成的n型井(well)21的半導體材料中。
本方法如以上所述，用於製作積體電路晶片。產生的積體電路晶片可由製作商以空白晶圓形式(例如：作為具有多個未封裝晶片的單一晶圓)、當作裸晶粒、或以封裝形式來配送。在後例中，晶片嵌裝於單晶片封裝(例如：塑膠載體，有導線黏貼至主機板或其它更高層階載體)中、或多晶片封裝(例如：具有表面互連或埋置型互連任一者或兩者的陶瓷載體)中。無論如何，晶片可與其它晶片、離散電路元件、及/或其它信號處理裝置整合，作為中間產品或或最終產品的部分。
本文中對“垂直”、“水平”、“側向”等用語的參照屬於舉例，並非限制，用來建立參考架構。諸如“水平”與“側向”等用語是指平面中與半導體基板的頂端表面平行 的方向，與其實際三維空間方位無關。諸如“垂直”與“正交”等用語是指與“水平”及“側向”方向垂直的方向。諸如“上面”及“下面”等用語指出元件或結構彼此的相對位置，及/或與半導體基板的頂端表面相對的位置，與相對高度截然不同。
“連接”或“耦接”至另一元件、或與該另一元件“連接”或“耦接”的特徵可直接連接或耦接至其它元件，或者，轉而可出現一或多個仲介元件。如無仲介元件，一特徵可“直接連接”或“直接耦接”至另一組件。如有至少一個仲介元件，一特徵可“間接連接”或“間接耦接”至另一組件。
本發明的各項具體實施例的描述已為了說明目的而介紹，但用意不在於窮舉或受限於所揭示的具體實施例。許多修改及變例對所屬領域技術人員將會顯而易見，但不會脫離所述具體實施例的範疇及精神。本文中使用的術語是為了最佳闡釋具體實施例的原理、對市場出現的技術所作的實務應用或技術改良、或讓所屬領域技術人員能夠理解本文中所揭示的具體實施例而選擇。

Claims (20)

  1. 一種結構，包含：層堆疊，包括具有第一導電類型的第一半導體層及具有第二導電類型的第二半導體層，該第一半導體層垂直配置成與該第二半導體層界定第一p-n接面；以及場效電晶體，位在該第一半導體層上，該場效電晶體包括在垂直堆疊中配置有多個奈米片通道層的鰭片、及繞著該奈米片通道層環繞的閘極結構，其中，該第一p-n接面配置成與該閘極結構及該奈米片通道層垂直對準。
  2. 如申請專利範圍第1項所述的結構，更包含：穿過該第一半導體層及該第一p-n接面延展的第一溝槽隔離區；以及穿過該第一半導體層及該第一p-n接面延展的第二溝槽隔離區，該第二溝槽隔離區與該第一溝槽隔離區水平相隔，其中，該第一p-n接面水平配置於該第一溝槽隔離區與該第二溝槽隔離區之間。
  3. 如申請專利範圍第2項所述的結構，其中，該第二半導體層為半導體基板。
  4. 如申請專利範圍第2項所述的結構，其中，該層堆疊包括具有該第一導電類型的第三半導體層，該第二半導體層垂直配置於該第一半導體層與該第三半導體層之間，並且該第三半導體層與該第二半導體層界定第二p-n 接面。
  5. 如申請專利範圍第4項所述的結構，其中，該第一溝槽隔離區及該第二溝槽隔離區各穿過該第二半導體層及該第二p-n接面延展至該第三半導體層內，並且該第二p-n接面水平配置於該第一溝槽隔離區與該第二溝槽隔離區之間。
  6. 如申請專利範圍第4項所述的結構，其中，該第三半導體層為半導體基板。
  7. 如申請專利範圍第4項所述的結構，其中，該第三半導體層為位在半導體基板中的井體。
  8. 如申請專利範圍第4項所述的結構，其中，該第一溝槽隔離區及該第二溝槽隔離區相對於該第一半導體層的頂端表面延展至第一深度，該第二p-n接面相對於該第一半導體層的該頂端表面位於第二深度處，並且該第二深度大於該第一深度。
  9. 如申請專利範圍第2項所述的結構，其中，該場效電晶體包括第一源極/汲極區及第二源極/汲極區，該閘極結構及該奈米片通道層水平配置於該第一源極/汲極區與該第二源極/汲極區之間，該第一源極/汲極區配置成與該第一溝槽隔離區垂直對準，並且該第二源極/汲極區配置成與該第二溝槽隔離區垂直對準。
  10. 如申請專利範圍第1項所述的結構，其中，該第二半導體層為半導體基板。
  11. 如申請專利範圍第1項所述的結構，其中，該層堆疊包 括具有該第一導電類型的第三半導體層，該第二半導體層垂直配置於該第一半導體層與該第三半導體層之間，並且該第三半導體層與該第二半導體層界定第二p-n接面。
  12. 如申請專利範圍第11項所述的結構，其中，該第三半導體層為半導體基板。
  13. 如申請專利範圍第11項所述的結構，其中，該第三半導體層為位在半導體基板中的井體。
  14. 一種方法，包含：形成層堆疊，該層堆疊包括具有第一導電類型的第一半導體層及具有第二導電類型的第二半導體層，該第一半導體層垂直配置成與該第二半導體層界定第一p-n接面；以及形成位在該第一半導體層上的場效電晶體，該場效電晶體包括在垂直堆疊中配置有多個奈米片通道層的鰭片、及繞著該奈米片通道層環繞的閘極結構，其中，該第一p-n接面配置成與該閘極結構及該奈米片通道層垂直對準。
  15. 如申請專利範圍第14項所述的方法，更包含：形成穿過該第一半導體層及該第一p-n接面延展的第一溝槽隔離區；以及形成穿過該第一半導體層及該第一p-n接面延展的第二溝槽隔離區，其中，該第二溝槽隔離區與該第一溝槽隔離區水 平相隔，並且該第一p-n接面水平配置於該第一溝槽隔離區與該第二溝槽隔離區之間。
  16. 如申請專利範圍第15項所述的方法，其中，該層堆疊包括具有該第一導電類型的第三半導體層，該第二半導體層垂直配置於該第一半導體層與該第三半導體層之間，並且該第三半導體層與該第二半導體層界定第二p-n接面。
  17. 如申請專利範圍第16項所述的方法，其中，該第一溝槽隔離區及該第二溝槽隔離區各穿過該第二半導體層及該第二p-n接面延展至該第三半導體層內，並且該第二p-n接面水平配置於該第一溝槽隔離區與該第二溝槽隔離區之間。
  18. 如申請專利範圍第16項所述的方法，其中，該第一溝槽隔離區及該第二溝槽隔離區相對於該第一半導體層的頂端表面延展至第一深度，該第二p-n接面相對於該第一半導體層的該頂端表面位於第二深度處，並且該第二深度大於該第一深度。
  19. 如申請專利範圍第14項所述的方法，其中，該層堆疊包括具有該第一導電類型的第三半導體層，該第二半導體層垂直配置於該第一半導體層與該第三半導體層之間，並且該第三半導體層與該第二半導體層界定第二p-n接面。
  20. 如申請專利範圍第19項所述的方法，其中，該第三半導體層為半導體基板、或位在該半導體基板中的井體。
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