US11646306B2 - Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate - Google Patents
Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate Download PDFInfo
- Publication number
- US11646306B2 US11646306B2 US17/210,610 US202117210610A US11646306B2 US 11646306 B2 US11646306 B2 US 11646306B2 US 202117210610 A US202117210610 A US 202117210610A US 11646306 B2 US11646306 B2 US 11646306B2
- Authority
- US
- United States
- Prior art keywords
- layer
- region
- height
- substrate
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 claims description 38
- 238000002955 isolation Methods 0.000 claims description 15
- 238000012545 processing Methods 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims 1
- 239000010410 layer Substances 0.000 description 153
- 230000008569 process Effects 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 20
- 238000005530 etching Methods 0.000 description 16
- 238000000059 patterning Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- 239000002135 nanosheet Substances 0.000 description 12
- 239000000945 filler Substances 0.000 description 9
- 239000000203 mixture Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011143 downstream manufacturing Methods 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000004615 ingredient Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000013208 measuring procedure Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Definitions
- the present invention relates generally to the field of nanosheets, and more particularly to concurrently forming multiple different devices along with the nanosheet on the same substrate.
- Gate-all-around device such as Nanosheet Field-Effect-Transistors (FETs) are becoming a technology of increasing importance with research and development focusing on standalone nanosheet devices.
- FETs Nanosheet Field-Effect-Transistors
- An apparatus comprising a substrate divided into a plurality of different regions, wherein the substrate remains physically together.
- a first device located in a first region of the plurality of different regions, wherein the first device has a first height.
- a second device located in a second region of the plurality of different regions, wherein the second device has a second height, wherein the second device is a different device from the first device.
- a third device located in a third region of the plurality of different regions, wherein the third device has a third height, wherein the third device is a different device from the first device and the second device. Wherein the second height is smaller than the first height.
- FIGS. 1 A, 1 B, and 1 C illustrates a cross sections of different regions on the same substrate, in accordance with an embodiment of the present invention.
- FIGS. 2 A, 2 B, and 2 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- FIGS. 3 A, 3 B, and 3 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- FIGS. 4 A, 4 B, and 4 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- FIGS. 5 A, 5 B, and 5 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- FIGS. 6 A, 6 B, and 6 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- FIGS. 7 A, 7 B, and 7 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- FIGS. 8 A, 8 B and 8 C illustrates a cross section of the different devices formed at separate regions on the same substrate, in accordance with an embodiment of the present invention.
- references in the specification to “one embodiment,” “an embodiment,” an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the disclosed structures and methods, as orientated in the drawing figures.
- the terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element.
- the term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating, or semiconductor layer at the interface of the two elements.
- references in the present description to forming layer “A” over layer “B” includes situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).
- layer “C” one or more intermediate layers
- compositions comprising, “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing” or any other variation thereof, are intended to cover a non-exclusive inclusion.
- a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other element not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
- exemplary is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiment or designs.
- the terms “at least one” and “one or more” can be understood to include any integer number greater than or equal to one, i.e., one, two, three, four, etc.
- the terms “a plurality” can be understood to include any integer number greater than or equal to two, i.e., two, three, four, five, etc.
- connection can include both indirect “connection” and a direct “connection.”
- the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrations or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like.
- the terms “about” or “substantially” are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of the filing of the application. For example, about can include a range of ⁇ 8%, or 5%, or 2% of a given value. In another aspect, the term “about” means within 5% of the reported numerical value. In another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.
- Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer.
- Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others.
- Removal/etching is any process that removes material from the wafer. Examples include etching process (either wet or dry), reactive ion etching (RIE), and chemical-mechanical planarization (CMP), and the like.
- Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implant dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate electrical components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage.
- RTA rapid thermal annealing
- This application is directed to a method of concurrently forming multiple devices on the same substrate and the structure of the different devices on the substrate.
- the devices will be formed at the same time on different regions on the substrate.
- the different devices can be a bottom dielectric isolated (BDI) nanosheet, an electrostatic discharge device, and a fin device.
- the starting substrate can be, for example, a Si wafer, a quartz wafer, a Sapphire wafer, metal line, or another layer that is suitable for being the starting layer for the formation of the multiple devices.
- the substrate is separated into a plurality of separate regions for processing, but the substrate remains physically whole, i.e., the substrate is not physically cut.
- a device will be concurrently formed in each of the separate regions, where the formed devices can be the same device or different devices.
- the locations of each of the plurality of separate regions can be adjacent to each other on the substrate or the locations of each of the plurality of separate regions can be spaced apart from each other to allow for the formation of other devices or lines on the substrate.
- the height of one of the finished devices can be different from the height of another of the finished devices, or the height of one of the finished devices can be substantially the same as the height of another of the finished devices, or a combination thereof.
- FIGS. 1 A, 1 B, and 1 C illustrates a cross sections 100 of different regions on the same substrate 105 , in accordance with an embodiment of the present invention.
- the substrate 105 can be, for example, a Si wafer, a Sapphire wafer, a metal layer, a non-metal layer, or any type of material that the multiple devices can be formed on.
- the substrate 105 is divided up into a plurality of separate regions for processing, e.g., each separate region will have a device formed thereon.
- the substrate 105 remains physically one-piece during processing, i.e., the substrate 105 is not physically separated into multiple substrates 105 .
- FIG. 1 A illustrates a first region on substrate 105
- FIG. 1 A illustrates a first region on substrate 105
- FIG. 1 A illustrates a first region on substrate 105
- FIG. 1 A illustrates a first region on substrate 105
- FIG. 1 A illustrates a first region on substrate 105
- FIG. 1 A illustrates
- FIG. 1 B illustrate a second region on substrate 105
- FIG. 1 C illustrates a third region on substrate 105 .
- the plurality of separate regions can be adjacent to another region of the plurality of separate regions, or the plurality of separate regions can be spaced apart from the other plurality of separate regions.
- the 1 st region can be adjacent to the 2 nd region, but spaced apart from the 3 rd region, or the 1 st region can be adjacent to both the 2 nd and 3 rd regions, or the 1 st region can be adjacent to the 3 rd region, but spaced apart from the 2 nd region, or the 1 st region can be spaced apart from the 2 nd and 3 rd regions, while the 2 nd and 3 rd regions are adjacent to each other, or the 1 st region, the 2 nd region, and the 3 rd region can be spaced apart from each other, or any combination thereof.
- FIG. 1 B illustrates the substrate 105 was doped with different materials to change the properties of the substrate 105 in the 2 nd region.
- 2 nd region is doped to have a P-sub, N-well, N+, and P+ regions for a formation of an electrostatic discharge device.
- FIG. 1 B illustrates that the substrate 105 can undergo processing prior to the formation of any layers on top of the substrate 105 .
- FIGS. 2 A, 2 B, and 2 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- FIGS. 2 A, 2 B, and 2 C show the 1 st region, 2 nd region, and the 3 rd region of the substrate 105 .
- a plurality of layers is formed on the surface of the substrate 105 .
- the first layer 110 is formed directly on the substrate 105 .
- the first layer 110 can be formed by, for example, by epitaxially growing the first layer 110 on the substrate 105 .
- the first layer 110 can serve a different purpose in different regions.
- the first layer 110 can be used as a placeholder material in one region and the first layer 110 can be a sacrificial protective layer in another region.
- the first layer 110 can be comprised of SiGe with the germanium content ranging from 50% to 70%.
- the percentage amount of Ge in layer 110 is not a set factor, there just needs to be a difference in the percentage amount between the first layer 110 and the second layer 115 (also the fourth layer 116 and the sixth layer 117 ).
- the second layer 115 is formed directly on the first layer 110 .
- the second layer 115 can by epitaxially growing the second layer 115 on the first layer 110 .
- the second layer 115 can be comprised of SiGe with the germanium content ranging from 15% to 35%.
- the difference in the percentages between the first layer 110 and the second layer 115 affects the downstream processing steps that can be applied to the different regions.
- the difference in the percentages of Ge in the first layer 110 and the second layer 115 needs to be large enough to differentiate between the layers during downstream processing steps.
- a third layer 120 is formed directly on top of the second layer 115 .
- the third layer 120 can be for example, Si, and the third layer 120 can be formed by epitaxially growing the third layer 120 on the second layer 115 .
- a fourth layer 116 is formed directly on top of the third layer 120 .
- the fourth layer 116 is comprised of the same material as the second layer 115 .
- a fifth layer 121 is formed directly on the fourth layer 116 .
- the fifth layer 121 is comprised of the same material as the third layer 120 .
- a sixth layer 117 is formed directly on top of the fifth layer 121 .
- the sixth layer 117 is comprised of the same material as the second layer 115 .
- a seventh layer 122 is formed directly on top of the sixth layer 117 .
- the seventh layer 122 is comprised of the same material as the third layer 120 .
- FIG. 2 A, 2 B, and 2 C illustrate only three stacks of SiGe (second layer 115 , fourth layer 116 , and sixth layer 117 ) and three stacks of Si (third layer 120 , fifth layer 121 , and seventh layer 122 ) is meant for illustrative proposes only, the number of stacks can be greater or fewer than the three stacks shown.
- the stack of layers as illustrate FIG. 2 A can be known as a Gate-All-Around (GAA) Epitaxial stack (second layer 115 , the third layer 120 , the fourth layer 116 , the fifth layer 121 , the sixth layer 117 , and the seventh layer 122 ).
- GAA Gate-All-Around
- FIGS. 3 A, 3 B, and 3 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- a hard mask 125 is formed directly on top of the seventh layer 122 in each of the regions.
- a patterning layer 130 is formed directly on top of the hard mask layer 125 in each of the regions.
- the patterning layer 130 can be, for example, an organic planarization layer.
- the patterning layer 130 allows for the patterning of each of the regions, where each of the regions can be independently patterned from each other. Thus, during an etching process each region can be treated independently from the other regions.
- the end device can be a bottom dielectric isolation nanosheet.
- the patterning of the overall device allows for the multiple layers in the 1 st region not to be etched.
- the 2 nd and 3 rd region are etched to remove the multiple layers down to the first layer 110 .
- the first layer 110 in the 2 nd and 3 rd regions prevents damage to the substrate 105 by the etching process, since the etching process is stop prior to the reaching the underlying substrate 105 .
- FIGS. 4 A, 4 B, and 4 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- the patterning layer 130 is removed from the top of the 1 st region in FIG. 4 A .
- a layer 123 is formed on top of the first layer 110 in the 2 nd and 3 rd regions, as illustrated by FIGS. 4 B and 4 C .
- Layer 123 can be for example, Si, and layer 123 can be formed by epitaxially growing layer 123 on the first layer 110 in the 2 nd and 3 rd regions.
- the height H 2 of layer 123 in the 2 nd region as illustrated by FIG.
- the height H 3 of the layer 123 in the 3 rd region is substantially equal to the height H 1 in the 1 st region of the combined height of the GAA Epitaxial stack.
- the height H 2 of the layer 123 in the 2 nd region is substantially the same as the height H 3 of the layer 123 in the 3 rd region.
- FIGS. 5 A, 5 B, and 5 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- a hard mask 125 is formed directly on top of the layer 123 on the 2 nd region and 3 rd region.
- the additional hard mask 125 material adds to the thickness of the hard mask 125 formed on top of the seventh layer 122 in the 1 st region.
- a patterning layer 130 is formed directly on top of the hard mask layer 125 in each of the regions.
- the patterning layer 130 can be, for example, an organic planarization layer.
- the patterning layer 130 allows for the patterning of each of the regions, where each of the regions can be independently patterned from each other.
- each region can be treated independently from the other regions.
- the layer 123 is removed in the 2 nd region, as illustrated by FIG. 5 B , where the first layer 110 acts as an etch stop.
- the first layer 110 in the 2 nd region protects the underlying substrate 105 from being damaged by the etching process.
- FIG. 5 A illustrates that the 1 st region remains untouched by the etching process
- FIG. 5 C illustrates that the 3 rd region remains untouched by the etching process.
- FIGS. 5 A, 5 B, and 5 C illustrate that each region can be independently processed so that different devices can be formed in the different regions.
- FIGS. 6 A, 6 B, and 6 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- FIGS. 6 A, 6 B and 6 C illustrate each of the regions being etched to form the devices.
- a hard mask 124 is formed on the top surface of each region and a pattern layer (not shown) is formed on the hard mask 125 .
- Each region is patterned prior to the anisotropic etching process to determine the shape of the devices after the etching process.
- the final device determines how, and which region are to be etched.
- the etching process removes some of the substrate 105 in each of the regions.
- FIG. 6 A illustrates the formation of a nanosheet device, where the width W 1 of the nanosheet device can be controlled by the patterning of the hard mask 125 prior to the etching process.
- FIG. 6 B illustrate the formation of a passive device such as an electrostatic discharge (ESD) device, where width W 2 of the ESD device is controlled by the patterning of the hard mask 125 prior to the etching process.
- FIG. 6 C illustrates the formation of fins, where the width W 3 of the fins is controlled by the patterning of the hard mask 125 prior to the etching process.
- ESD electrostatic discharge
- FIGS. 7 A, 7 B, and 7 C illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- a trench filler layer 135 is formed in the gaps formed in the substrate 105 .
- the trench filler layer 135 can be, for example, a shallow trench isolation material such as an oxide.
- the trench filler layer 135 fills the gaps on substrate 105 on both sides of the pillar, where the height of the trench filler layer 135 reaches to about the bottom of the first layer 110 .
- FIG. 7 A illustrates a cross section of the different regions for the formation of a different device at each region, in accordance with an embodiment of the present invention.
- a trench filler layer 135 is formed in the gaps formed in the substrate 105 .
- the trench filler layer 135 can be, for example, a shallow trench isolation material such as an oxide.
- the trench filler layer 135 fills the gaps on substrate 105 on both sides of the pillar,
- the trench filler layer 135 fills the gaps on substrate 105 around the columns created in the substrate 105 , where the height of the trench filler layer 135 reaches to about the bottom of the first layer 110 .
- the trench filler layer 135 fills the gaps on substrate 105 on both sides of the fins and between the fins, where the height of the trench filler layer 135 reaches to about the bottom of the first layer 110 .
- FIGS. 8 A, 8 B and 8 C illustrates a cross section of the different devices formed at separate regions on the same substrate 105 , in accordance with an embodiment of the present invention.
- FIGS. 8 A, 8 B, and 8 C illustrate the completed devices after further processing steps.
- FIG. 8 A illustrates the replacement of the first layer 110 with a bottom dielectric isolation (BDI) layer 145 .
- the BDI layer 145 can be comprised of, for example, oxide, a low-k dielectric such as SiBCN, SiOCN, SiOC, or a combination thereof.
- the first layer 110 can be selectively replaced over the second layer 115 because of the difference of the percentage of Ge in the layers.
- the second layer 115 , the fourth layer 116 , and the sixth layer 117 are replaced with a multi-layer gate stack 140 .
- the multi-layer gate stack 140 comprises an insulative gate dielectric and at least one conductive layer over the gate dielectric material and encloses each of the third layer 120 , the fifth layer 121 , and the seventh layer 122 .
- the multi-layer gate stack 140 is comprised of a high-k metal gate material.
- the overall height H 4 of the nanosheet device is the height from the bottom of the trench filler layer 135 to the top of the device (e.g., the top of seventh layer 122 ).
- the top surface of the substrate 105 is exposed by the removal of the first layer 110 .
- the top surface of the substrate 105 should be undamaged from all the prior processing steps since the first layer 110 acted as a sacrificial protection layer.
- the first layer 110 and any of the gate metal 140 that was formed in the 2 nd region has been removed to expose the top of the substrate 105 .
- the height H 5 of the electrostatic discharge device in the 2 nd region is less than the height H 4 of the nanosheet device in the 1 st region.
- the difference in the height H 4 and the height H 5 is the height H 7 to the top of the nanosheet device (e.g., the top of the seventh layer 122 ).
- FIG. 8 C illustrates that the first layer 110 in each of the fins was replaced by the BDI layer 145 and that the multi-layer gate stack 140 has enclosed the fins.
- the fin device illustrated by FIG. 8 C can exhibit bottom dielectric isolation of at least the gate region or both the gate and Source-Drain regions.
- the height H 6 of the fins should have a height that is substantially the same as the height H 4 as the nanosheet device in the 1 st region.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nanotechnology (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/210,610 US11646306B2 (en) | 2021-03-24 | 2021-03-24 | Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/210,610 US11646306B2 (en) | 2021-03-24 | 2021-03-24 | Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
US20220310590A1 US20220310590A1 (en) | 2022-09-29 |
US11646306B2 true US11646306B2 (en) | 2023-05-09 |
Family
ID=83365049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/210,610 Active 2041-06-03 US11646306B2 (en) | 2021-03-24 | 2021-03-24 | Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate |
Country Status (1)
Country | Link |
---|---|
US (1) | US11646306B2 (en) |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5075253A (en) | 1989-04-12 | 1991-12-24 | Advanced Micro Devices, Inc. | Method of coplanar integration of semiconductor IC devices |
US20140097502A1 (en) * | 2012-10-10 | 2014-04-10 | Seoul National University R & Db Foundation | Semiconductor device and fabricating method thereof |
US9012997B2 (en) | 2012-10-26 | 2015-04-21 | International Business Machines Corporation | Semiconductor device including ESD protection device |
US9397200B2 (en) | 2014-10-24 | 2016-07-19 | Globalfoundries Inc. | Methods of forming 3D devices with dielectric isolation and a strained channel region |
US9614057B2 (en) | 2014-12-30 | 2017-04-04 | International Business Machines Corporation | Enriched, high mobility strained fin having bottom dielectric isolation |
US9640531B1 (en) | 2014-01-28 | 2017-05-02 | Monolithic 3D Inc. | Semiconductor device, structure and methods |
US20170213821A1 (en) | 2014-08-26 | 2017-07-27 | Monolithic 3D Inc. | 3d semiconductor device and structure |
US9761722B1 (en) | 2016-06-24 | 2017-09-12 | International Business Machines Corporation | Isolation of bulk FET devices with embedded stressors |
US9847391B1 (en) | 2017-04-05 | 2017-12-19 | Globalfoundries Inc. | Stacked nanosheet field-effect transistor with diode isolation |
US10032867B1 (en) | 2017-03-07 | 2018-07-24 | International Business Machines Corporation | Forming bottom isolation layer for nanosheet technology |
US10062601B2 (en) | 2013-11-13 | 2018-08-28 | Taiwan Semiconductor Manufacturing Company Limited | Systems and methods for a semiconductor structure having multiple semiconductor-device layers |
US10170638B1 (en) | 2018-01-23 | 2019-01-01 | International Business Machines Corporation | Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer |
US20190019891A1 (en) | 2016-03-30 | 2019-01-17 | Intel Corporation | Geometry tuning of fin based transistor |
US20190057868A1 (en) | 2017-05-19 | 2019-02-21 | Psemi Corporation | Managed Substrate Effects for Stabilized SOI FETs |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US20190172826A1 (en) | 2015-03-09 | 2019-06-06 | Monolithic 3D Inc. | A 3d semiconductor wafer, devices, and structure |
US10332803B1 (en) | 2018-05-08 | 2019-06-25 | Globalfoundaries Inc. | Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming |
-
2021
- 2021-03-24 US US17/210,610 patent/US11646306B2/en active Active
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5075253A (en) | 1989-04-12 | 1991-12-24 | Advanced Micro Devices, Inc. | Method of coplanar integration of semiconductor IC devices |
US20140097502A1 (en) * | 2012-10-10 | 2014-04-10 | Seoul National University R & Db Foundation | Semiconductor device and fabricating method thereof |
US9012997B2 (en) | 2012-10-26 | 2015-04-21 | International Business Machines Corporation | Semiconductor device including ESD protection device |
US10062601B2 (en) | 2013-11-13 | 2018-08-28 | Taiwan Semiconductor Manufacturing Company Limited | Systems and methods for a semiconductor structure having multiple semiconductor-device layers |
US9640531B1 (en) | 2014-01-28 | 2017-05-02 | Monolithic 3D Inc. | Semiconductor device, structure and methods |
US20170213821A1 (en) | 2014-08-26 | 2017-07-27 | Monolithic 3D Inc. | 3d semiconductor device and structure |
US9397200B2 (en) | 2014-10-24 | 2016-07-19 | Globalfoundries Inc. | Methods of forming 3D devices with dielectric isolation and a strained channel region |
US9614057B2 (en) | 2014-12-30 | 2017-04-04 | International Business Machines Corporation | Enriched, high mobility strained fin having bottom dielectric isolation |
US20190172826A1 (en) | 2015-03-09 | 2019-06-06 | Monolithic 3D Inc. | A 3d semiconductor wafer, devices, and structure |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US20190019891A1 (en) | 2016-03-30 | 2019-01-17 | Intel Corporation | Geometry tuning of fin based transistor |
US9761722B1 (en) | 2016-06-24 | 2017-09-12 | International Business Machines Corporation | Isolation of bulk FET devices with embedded stressors |
US10032867B1 (en) | 2017-03-07 | 2018-07-24 | International Business Machines Corporation | Forming bottom isolation layer for nanosheet technology |
US9847391B1 (en) | 2017-04-05 | 2017-12-19 | Globalfoundries Inc. | Stacked nanosheet field-effect transistor with diode isolation |
US20190057868A1 (en) | 2017-05-19 | 2019-02-21 | Psemi Corporation | Managed Substrate Effects for Stabilized SOI FETs |
US10170638B1 (en) | 2018-01-23 | 2019-01-01 | International Business Machines Corporation | Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer |
US10332803B1 (en) | 2018-05-08 | 2019-06-25 | Globalfoundaries Inc. | Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming |
Non-Patent Citations (2)
Title |
---|
Chen, et al., "ESD Protection Diodes in Bulk Si Gate-AII-Around Vertically Stacked Horizontal Nanowire Technology," IEEE Transactions on Device and Materials Reliability, Mar. 2019 [accessed on Feb. 25, 2020], pp. 112-119, vol. 19, Issue 1, IEEE, DOI: 10.1109/TDMR.2018.2886399, Retrieved from the Internet: URL: https://ieeexplore.ieee.org/document/8576641>. |
Zhang, et al., "Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications," 2019 IEEE International Electron Devices Meeting (IEDM), Dec. 7-11, 2019 [accessed on Sep. 24, 2020], 4 pages, IEEE, San Francisco, CA, USA, DOI: 10.1109/IEDM19573.2019.8993490, Retrieved from the Internet: <URL: https://ieeexplore.ieee.org/document/8993490>. |
Also Published As
Publication number | Publication date |
---|---|
US20220310590A1 (en) | 2022-09-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10586739B2 (en) | Self-aligned punch through stopper liner for bulk FinFET | |
US10103247B1 (en) | Vertical transistor having buried contact, and contacts using work function metals and silicides | |
US10586741B2 (en) | Gate height and spacer uniformity | |
US10622264B2 (en) | Nanosheet devices with different types of work function metals | |
US10608121B2 (en) | FinFET transistor gate and epitaxy formation | |
US10297688B2 (en) | Vertical field effect transistor with improved reliability | |
US11710768B2 (en) | Hybrid diffusion break with EUV gate patterning | |
WO2022262462A1 (en) | Thick gate oxide device option for nanosheet device | |
US20230163127A1 (en) | Stacked nanosheet devices with matched threshold voltages for nfet/pfet | |
US11646306B2 (en) | Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate | |
US11563003B2 (en) | Fin top hard mask formation after wafer flipping process | |
US20220406776A1 (en) | Stacked fet with different channel materials | |
US20240088034A1 (en) | Gaa device with the substrate including embedded insulating structure between bspdn and channels | |
US20230063973A1 (en) | Fet with reduced parasitic capacitance | |
US20230178551A1 (en) | Integration of horizontal nanosheet device and vertical nano fins | |
US20240178136A1 (en) | Local interconnect formation at double diffusion break | |
US20230369220A1 (en) | Via to backside power rail through active region | |
US20230290823A1 (en) | Nanosheet with early isolation | |
US20240074135A1 (en) | Sram with staggered stacked fet | |
US20230387007A1 (en) | Interconnect through gate cut for stacked fet device | |
US20230411358A1 (en) | Method and structure of forming independent contact for staggered cfet | |
US20240186387A1 (en) | Via and source/drain contact landing under power rail | |
US20230282722A1 (en) | Co-integration of source-drain trench metal cut and gate-contact-over active device for advanced transistor architectures | |
US10950505B2 (en) | Multiple finFET formation with epitaxy separation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FROUGIER, JULIEN;BASKER, VEERARAGHAVAN S.;GAUL, ANDREW;AND OTHERS;SIGNING DATES FROM 20210315 TO 20210321;REEL/FRAME:055695/0894 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |