CN108666221B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN108666221B
CN108666221B CN201710203255.1A CN201710203255A CN108666221B CN 108666221 B CN108666221 B CN 108666221B CN 201710203255 A CN201710203255 A CN 201710203255A CN 108666221 B CN108666221 B CN 108666221B
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fin
side wall
forming
substrate
grid
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CN108666221A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US15/941,225 priority patent/US10361305B2/en
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Abstract

一种半导体结构及其形成方法，形成方法包括：对侧墙层进行刻蚀，以在栅极结构侧壁上形成栅极侧墙，在鳍部的侧壁上形成遮挡侧墙；所述遮挡侧墙靠近所述隔离结构并远离所述鳍部顶部表面；之后对所述鳍部进行离子注入形成轻掺杂漏区域。由于受到所述遮挡侧墙的保护，被遮挡侧墙遮挡的鳍部底部受到离子掺杂的浓度较低，从而有效的防止了源漏穿通，更好的抑制了短沟道效应。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造领域，特别涉及一种半导体结构及其形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高元件密度，以及更高集成度的方向发展。晶体管作为最基本的半导体器件目前正被广泛应用，因此随着半导体器件元件密度和集成度的提高，平面晶体管的栅极尺寸也越来越小，传统的平面晶体管对沟道电流的控制能力变弱，产生短沟道效应，漏电流增大，最终影响半导体器件的电学性能。
为了进一步缩小MOSFET(Metal-Oxide-Semiconductor Field-EffectTransistor,金属-氧化物半导体场效应晶体管)器件的尺寸，人们发展了多面栅场效应晶体管结构，以提高MOSFET器件栅极的控制能力，抑制短沟道效应。其中，鳍式场效应晶体管(FinFET)就是一种常见的多面栅结构晶体管。FinFET中，栅极至少可以从两侧对超薄体(鳍部)进行控制，具有比平面MOSFET器件强得多的栅对沟道的控制能力，能够很好的抑制短沟道效应；且FinFET相对于其他器件，具有更好的现有的集成电路制作技术的兼容性。
然而，现有技术所形成鳍式场效应管的性能有待进一步提高。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，以改善所形成半导体结构的性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：
提供基底，所述基底包括衬底及位于衬底上的多个鳍部；在所述鳍部之间形成隔离结构，所述隔离结构顶部低于所述鳍部顶部；形成横跨所述鳍部的栅极结构，所述栅极结构覆盖鳍部的部分侧壁和部分顶部表面；形成覆盖所述栅极结构和所述鳍部的侧墙层；对所述侧墙层进行刻蚀，以在所述栅极结构的侧壁上形成栅极侧墙，并在鳍部靠近所述隔离结构的侧壁上形成遮挡侧墙；以所述栅极侧墙和所述遮挡侧墙为掩膜对所述鳍部进行注入工艺，在所述鳍部中形成轻掺杂漏区域。
可选的，所述侧墙层的材料是氮化硅。
可选的，所述遮挡侧墙的高度是100埃～350埃。
可选的，所述侧墙层的厚度是15埃～80埃。
可选的，形成所述遮挡侧墙采用的是干法刻蚀工艺。
可选的，所述干法刻蚀工艺的参数为：
CF4:5SCCM～100SCCM,CH3F:8SCCM～50SCCM,O2:10SCCM～100SCCM,RF:50W～300W,DC＝30V～100V,4S～50S,10mtoor～2000mtoor。
可选的，所述衬底包括用于形成N型半导体的N型区域，对所述N型区域内的所述鳍部进行轻掺杂漏注入的离子包括AS/P，离子注入剂量在1.0E14atm/cm3～1.0E16atm/cm3。
可选的，所述衬底包括用于形成P型半导体的P型区域，对所述P型区域内的所述鳍部进行轻掺杂漏注入的离子包括B/BF2，离子注入剂量在1.0E14atm/cm3～8.0E15atm/cm3。
可选的，在所述鳍部中形成轻掺杂漏区域以后，所述形成方法还包括：去除所述遮挡侧墙；在所述栅极侧墙两侧的鳍部中形成源漏掺杂区。
可选的，形成所述源漏掺杂区的步骤包括：在所述栅极侧墙两侧的鳍部中形成应力层，并对所述应力层进行离子注入。
可选的，对所述应力层进行离子注入之后，进行退火处理，在栅极侧墙两侧的鳍部中形成源漏掺杂区。
本发明还提供一种半导体结构，其特征在于，包括基底，所述基底包括衬底及位于衬底上的多个鳍部；位于所述衬底上的隔离结构，所述隔离结构顶部低于鳍部顶部；横跨所述鳍部的栅极结构，所述栅极结构覆盖鳍部的部分侧壁和部分顶部表面；位于所述栅极结构侧壁上的栅极侧墙；位于所述栅极结构两侧的鳍部中的源漏掺杂区；远离所述隔离结构的所述鳍部中的掺杂浓度高于靠近所述隔离结构的所述鳍部中的掺杂浓度。
可选的，所述栅极侧墙的材料是氮化硅。
可选的，所述栅极侧墙的厚度在60nm～200nm的范围内。
可选的，远离隔离结构的所述鳍部中的掺杂浓度比靠近隔离结构的所述鳍部中的掺杂浓度高1.3倍至2倍。
可选的，所述衬底包括用于形成N型晶体管的N型区域，远离隔离结构的所述鳍部中的掺杂浓度为1.0E20atm/cm3～1.0E22atm/cm3，靠近隔离结构的所述鳍部中的掺杂浓度为1.8E19atm/cm3～1.5E21atm/cm3。
可选的，所述衬底包括用于形成P型晶体管的P型区域，远离隔离结构的所述鳍部中的掺杂浓度为1.0E20atm/cm3～1.0E22atm/cm3，靠近隔离结构的所述鳍部中的掺杂浓度为1.8E19atm/cm3～1.5E21atm/cm3。
可选的，所述半导体结构还包括：所述栅极结构两侧鳍部中的应力层，所述应力层中含有掺杂区，所述掺杂区为所述源漏掺杂区的一部分。
与现有技术相比，本发明的技术方案具有以下优点：
本发明方案中，在所述栅极结构侧壁上形成栅极侧墙，并且在所述鳍部的侧壁上形成遮挡侧墙，所述遮挡侧墙靠近所述隔离结构并远离所述鳍部顶部表面；之后对所述鳍部进行离子注入形成轻掺杂漏区域。由于受到所述遮挡侧墙的保护，被遮挡侧墙遮挡的鳍部底部受到离子掺杂的浓度较低，从而有效的防止了源漏穿通，更好的抑制了短沟道效应。
附图说明
图1至图2是一种半导体结构形成过程中的结构示意图；
图3至图6、图8、图10是本发明实施例中半导体结构形成方法各个步骤对应的结构示意图；
图7是图6中未被栅极结构覆盖的鳍部沿X方向的剖面结构示意图；
图9是图8中所示鳍部101沿Y方向的剖面结构示意图。
具体实施方式
参考图1至图2，是一种半导体结构形成方法其中一个步骤对应的立体结构示意图。
参考图1，提供衬底10，形成位于所述衬底10上的鳍部11；在所述衬底10上及所述鳍部11之间形成隔离结构12，所述隔离结构12低于所述鳍部11顶部表面；形成横跨所述鳍部11的栅极结构(未标示)，所述栅极结构覆盖所述鳍部11的部分侧壁和部分顶部表面，所述栅极结构包括位于所述鳍部11上的栅介质层13及所述栅介质层13上的栅电极14。
参考图2，在所述栅极结构的侧壁上形成侧墙15；对所述鳍部11进行注入工艺，在所述鳍部11中形成轻掺杂漏区域。
本申请的发明人经过研究发现，由于进行所述注入工艺时，靠近所述隔离结构12的鳍部中掺杂浓度过高，易引起短沟道效应的问题，甚至导致源漏穿通。
为解决所述技术问题，本发明提供一种半导体结构的形成方法，包括：提供基底，所述基底包括衬底及位于衬底上的多个鳍部；在所述鳍部之间形成隔离结构，所述隔离结构顶部低于所述鳍部顶部；形成横跨所述鳍部的栅极结构，所述栅极结构覆盖鳍部的部分侧壁和部分顶部表面；形成覆盖所述栅极结构和所述鳍部的侧墙层；对所述侧墙层进行刻蚀，以在所述栅极结构的侧壁上形成栅极侧墙，并在鳍部靠近所述隔离结构的侧壁上形成遮挡侧墙；以所述栅极侧墙和所述遮挡侧墙为掩膜对所述鳍部进行注入工艺，在所述鳍部中形成轻掺杂漏区域。
本发明方案中，在所述栅极结构侧壁上形成侧墙的同时，在所述鳍部的侧壁上形成遮挡侧墙，所述遮挡侧墙靠近所述隔离结构并远离所述鳍部顶部表面；之后对所述鳍部进行离子注入形成轻掺杂漏区域。由于受到所述鳍侧墙的保护，被遮挡侧墙遮挡的鳍部底部受到离子掺杂的浓度较低，从而有效的防止了源漏穿通，更好的抑制了短沟道效应。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图10为本发明半导体结构形成方法一实施例各个步骤对应的结构示意图。
参考图3，提供基底，所述基底包括衬底100及位于衬底上的多个鳍部101，本实施例附图以一个鳍部为例。在所述鳍部101之间形成隔离结构102，所述隔离结构102顶部低于所述鳍部101顶部。本申请中所述顶部是指与底部相对的部位，所述底部是指与所述衬底相连的区域。
本实施例中，所述衬底100和所述鳍部101的材料为单晶硅。
在本发明其他实施例中，所述衬底的材料还可以选自锗、砷化镓或硅锗化合物；所述衬底还可以是其他半导体材料。此外，所述衬底还可以选自具有外延层或外延层上硅结构。
需要说明的，所述衬底和所述鳍部的材料也可以不相同。所述衬底上还可以具有实现各种实际所需功能的半导体层。所述衬底可以为适宜于工艺需求或易于集成的材料；所述半导体层的材料可以为适宜于形成鳍部的材料。
提供所述基底的步骤包括：提供初始基底，在所述初始基底上形成图形化的鳍部掩膜层(图未示)；以所述鳍部掩膜层为掩膜，刻蚀所述初始基底，以形成所述衬底100以及分立的鳍部101。
本实施例中，所述隔离结构102的材料为氧化硅。本发明其他实施例中，所述隔离结构的材料还可以为氮化硅或氮氧化硅。
具体的，形成所述隔离结构102的步骤包括：在相邻鳍部101之间的衬底100上形成隔离材料层，所述隔离材料层覆盖所述鳍部掩模层；去除所述隔离材料层的部分厚度，形成隔离结构102，使所形成隔离结构102的顶部表面低于所述鳍部101的顶部表面，露出所述鳍部101侧壁的部分表面。
参考图4，形成横跨所述鳍部101的栅极结构，所述栅极结构覆盖鳍部的部分侧壁和部分顶部表面。
所述栅极结构用于形成晶体管的栅极，还用于在后续晶体管源区或漏区形成过程中遮挡部分鳍部101，避免所形成晶体管源区或漏区直接接触。
所述栅极结构包括位于所述鳍部101上的栅介质层103以及位于所述栅介质层103上的栅电极104。所述栅介质层103用于隔离栅电极104与沟道。所述栅介质层103可以包括高K介质层。所述栅电极104的材料可以为多晶硅或金属。
本实施例中，所述形成方法还包括：形成位于栅电极104上的硬掩膜层105。所述硬掩膜层105用于定义所述栅极结构的尺寸和位置。所述硬掩膜层105的材料是氮化物。所述硬掩膜层105的结构也可以是叠层结构。
本发明其他实施例中，所述栅极结构还可以是伪栅结构，用于为后续所形成栅极结构占据空间位置。
参考图5，形成覆盖所述栅极结构和所述鳍部101的侧墙层106。所述侧墙层106用于形成栅极侧墙及遮挡侧墙。
所述侧墙层106的材料是氮化硅的单层结构。本发明其他实施例中，所述侧墙层的材料还可以为氧化硅、氮氧化硅、碳化硅、碳氧化硅或碳氮氧化硅。此外，所述侧墙层也可以是叠层结构。
在本实施例中，由于所述栅极结构顶部还形成有硬掩膜层105，因此所述侧墙层106还覆盖所述硬掩膜层105。
具体的，形成所述侧墙层106的工艺方法为化学气相沉积法。在其他实施例中，还可以采用物理气相沉积或等离子体气相沉积法。
所述侧墙层106的厚度不宜过大也不宜过小。如果过大，既使工艺难度增加，又造成了工艺材料的浪费；如果过小，则后续所形成的遮挡侧墙的厚度也过小，在后续离子注入工艺过程中，遮挡侧墙对鳍部底部的遮挡保护作用降低。因此，所述侧墙层106的厚度为15埃～80埃。
参考图6，对所述侧墙层106进行刻蚀，在所述栅极结构的侧壁上形成栅极侧墙107，并在鳍部101靠近所述隔离结构102的侧壁上形成遮挡侧墙108。
所述栅极侧墙107的作用是控制后续形成的外延层与沟道之间的距离。所述栅极侧墙107的材料是氮化硅的单层结构。本发明其他实施例中，所述栅极侧墙的材料还可以为氧化硅、氮氧化硅、碳化硅、碳氧化硅或碳氮氧化硅。此外，所述栅极侧墙也可以是叠层结构。
所述遮挡侧墙108的作用是在后续离子注入工艺时对鳍部的底部进行保护，由于受到所述遮挡侧墙的保护，鳍部底部受到离子掺杂的浓度较低，从而有效的防止了源漏穿通，更好的抑制了短沟道效应。
形成所述遮挡侧墙108所采用的工艺为干法刻蚀工艺，所述干法刻蚀工艺的参数为：
CF4:5SCCM～100SCCM,CH3F:8SCCM～50SCCM,O2:10SCCM～100SCCM,RF:50W～300W,DC:30V～100V,4S～50S,10mtoor～2000mtoor。
所述遮挡侧墙108的高度不宜太大也不宜过小。如果高度过大，则容易使所述鳍部101中形成的轻掺杂漏区域过小，使得轻掺杂漏区域降低短沟道效应的性能下降；如果高度过小，则容易使所述鳍部101底部的离子掺杂浓度得不到有效控制，不能有效防止源漏穿通。因此，所述遮挡侧墙的高度是100埃～350埃。
参考图7，图7是图6中未被栅极结构覆盖的鳍部沿X方向的剖面结构示意图。以所述栅极侧墙107和所述遮挡侧墙108为掩膜对所述鳍部101进行注入工艺109，在所述鳍部101中形成轻掺杂漏区域。
本实施例以所述衬底100包括N型半导体的N型区域和P型半导体的P型区域为例。首先对N型区域进行N型注入工艺，本实施例中，对所述N型区域内的所述鳍部进行轻掺杂漏注入的离子包括As，离子注入剂量在1.0E14atm/cm2～1.0E16atm/cm2然后对P型区域进行P型注入工艺，本实施例中，对所述P型区域内的所述鳍部进行轻掺杂漏注入的离子包括P，离子注入剂量在1.0E14atm/cm2～8.0E15atm/cm2需要说明的是，在其他实施例中，也可以先进行P型注入工艺，再进行N型注入工艺。
此外，在其他实施例中，所述衬底也可以仅包括N型区域或仅包括P型区域。
参考图8，在所述鳍部101中形成轻掺杂漏区域以后，所述形成方法还包括：去除所述遮挡侧墙108。
去除所述遮挡侧墙108所采用的工艺是等离子体刻蚀工艺。
参考图9，图9是图8中所示鳍部101沿Y方向的剖面结构示意图。本实施例以所述衬底100包括N型半导体的N型区域和P型半导体的P型区域为例。
参考图10，在所述栅极侧墙107两侧的鳍部101中形成源漏掺杂区。
形成所述源漏掺杂区的步骤包括：在所述栅极侧墙107两侧的鳍部101中形成应力层，并对所述应力层进行离子注入。
本实施例中，所述N型区域内的应力层为第一应力层110，所述P型区域内的应力层为第二应力层111。所述第一应力层110的材料为SiP，所述第一应力层110的形状为“U”形。所述第一应力层110通过Si和SiP之间晶格失配向所述N型区域的沟道区施加拉应力作用，以提高载流子迁移率，进而提高晶体管的性能。所述第二应力层111的材料为SiGe，且所述第二应力层111的形状为“Σ”形。所述第二应力层111通过Si和SiGe之间的晶格失配向所述P型区域的沟道区施加压应力，以提高沟道内载流子的迁移率，进而改善晶体管的性能。
对所述应力层进行离子注入之后，进行退火处理，在所述栅极侧墙107两侧的鳍部101中形成源漏掺杂区。
相应的，本发明还提供一种半导体结构。参考图10，示出了本发明半导体结构一实施例的剖面结构示意图。
所述半导体结构包括：基底，所述基底包括衬底100及位于衬底100上的多个鳍部101；位于所述衬底100上的隔离结构102，所述隔离结构102顶部低于鳍部101顶部；横跨所述鳍部101的栅极结构，所述栅极结构覆盖鳍部101的部分侧壁和部分顶部表面；位于所述栅极结构侧壁上的栅极侧墙107；位于所述栅极结构两侧的鳍部101中的源漏掺杂区；远离所述隔离结构102的所述鳍部101中的掺杂浓度高于靠近所述隔离结构102的所述鳍部101中的掺杂浓度。
以下将结合附图对本发明实施例提供的半导体结构进行详细说明。
有关所述衬底100以及所述鳍部101的描述可参考前述实施例的相应说明，在此不再赘述。
所述栅极侧墙107的材料是氮化硅；所述栅极侧墙107的厚度在60nm～200nm的范围内。
远离所述隔离结构102的所述鳍部101中的掺杂浓度比靠近所述隔离结构102的所述鳍部101中的掺杂浓度高1.3倍至2倍。
本实施例中，所述半导体结构还包括：用于形成N型晶体管的N型区域和用于形成P型晶体管的P型区域。在N型区域内，远离所述隔离结构102的所述鳍部101中的掺杂浓度为1.0E20atm/cm3～1.0E22atm/cm3，靠近所述隔离结构102的所述鳍部101中的掺杂浓度为1.8E19atm/cm3～1.5E21atm/cm3；P型区域内，远离所述隔离结构102的所述鳍部101中的掺杂浓度为1.0E20atm/cm3～1.0E22atm/cm3，靠近所述隔离结构102的所述鳍部101中的掺杂浓度为1.8E19atm/cm3～1.5E21atm/cm3。
本实施例中，所述半导体结构还包括：所述栅极结构两侧鳍部101中的应力层，所述应力层中含有掺杂区，所述掺杂区为所述源漏掺杂区的一部分。
综上，本发明方案在所述栅极结构侧壁上形成栅极侧墙的同时，在所述鳍部的侧壁上形成遮挡侧墙，所述遮挡侧墙靠近所述隔离结构并远离所述鳍部顶部表面；之后对所述鳍部进行离子注入形成轻掺杂漏区域。由于受到所述遮挡侧墙的保护，被遮挡侧墙遮挡的鳍部底部受到离子掺杂的浓度较低，从而有效的防止了源漏穿通，更好的抑制了短沟道效应。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (16)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底，所述基底包括衬底及位于衬底上的多个鳍部；
在所述鳍部之间形成隔离结构，所述隔离结构顶部低于所述鳍部顶部；
形成横跨所述鳍部的栅极结构，所述栅极结构覆盖鳍部的部分侧壁和部分顶部表面；
形成覆盖所述栅极结构和所述鳍部的侧墙层；
对所述侧墙层进行刻蚀，以在所述栅极结构的侧壁上形成栅极侧墙，并在鳍部靠近所述隔离结构的侧壁上形成遮挡侧墙；
以所述栅极侧墙和所述遮挡侧墙为掩膜对所述鳍部进行注入工艺，在所述鳍部中形成轻掺杂漏区域。
2.如权利要求1所述的形成方法，其特征在于，所述侧墙层的材料是氮化硅。
3.如权利要求1所述的形成方法，其特征在于，所述遮挡侧墙的高度是100埃～350埃。
4.如权利要求1所述的形成方法，其特征在于，所述侧墙层的厚度是15埃～80埃。
5.如权利要求1所述的形成方法，其特征在于，形成所述遮挡侧墙采用的是干法刻蚀工艺。
6.如权利要求5所述的形成方法，其特征在于，所述干法刻蚀工艺的参数为：CF4:5SCCM～100SCCM,CH3F:8SCCM～50SCCM,O2:10SCCM～100SCCM,RF:50W～300W,DC:30V～100V,4S～50S,10mtorr～2000mtorr。
7.如权利要求1所述的形成方法，其特征在于，所述衬底包括用于形成N型半导体的N型区域，对所述N型区域内的所述鳍部进行轻掺杂漏注入的离子包括AS或P，离子注入剂量在1.0E14atm/cm2～1.0E16atm/cm2。
8.如权利要求1所述的形成方法，其特征在于，所述衬底包括用于形成P型半导体的P型区域，对所述P型区域内的所述鳍部进行轻掺杂漏注入的离子包括B或BF2，离子注入剂量在1.0E14atm/cm2～8.0E15atm/cm2。
9.如权利要求1所述的形成方法，其特征在于，在所述鳍部中形成轻掺杂漏区域以后，所述形成方法还包括：去除所述遮挡侧墙；在所述栅极侧墙两侧的鳍部中形成源漏掺杂区。
10.如权利要求9所述的形成方法，其特征在于，形成所述源漏掺杂区的步骤包括：在所述栅极侧墙两侧的鳍部中形成应力层，并对所述应力层进行离子注入。
11.如权利要求10所述的形成方法，其特征在于，对所述应力层进行离子注入之后，进行退火处理，在栅极侧墙两侧的鳍部中形成源漏掺杂区。
12.一种半导体结构，其特征在于，包括基底，所述基底包括衬底及位于衬底上的多个鳍部；
位于所述衬底上的隔离结构，所述隔离结构顶部低于鳍部顶部；
横跨所述鳍部的栅极结构，所述栅极结构覆盖鳍部的部分侧壁和部分顶部表面；
位于所述栅极结构侧壁上的栅极侧墙；
位于所述栅极结构两侧的鳍部中的轻掺杂漏区域和源漏掺杂区；
在所述轻掺杂漏区域中，远离所述隔离结构的所述鳍部中的掺杂浓度高于靠近所述隔离结构的所述鳍部中的掺杂浓度；
所述衬底包括用于形成N型晶体管的N型区域，远离隔离结构的所述鳍部中的掺杂浓度为1.0E20atm/cm3～1.0E22atm/cm3，靠近隔离结构的所述鳍部中的掺杂浓度为1.8E19atm/cm3～1.5E21atm/cm3，或者，
所述衬底包括用于形成P型晶体管的P型区域，远离隔离结构的所述鳍部中的掺杂浓度为1.0E20atm/cm3～1.0E22atm/cm3，靠近隔离结构的所述鳍部中的掺杂浓度为1.8E19atm/cm3～1.5E21atm/cm3。
13.如权利要求12所述的半导体结构，其特征在于，所述栅极侧墙的材料是氮化硅。
14.如权利要求12所述的半导体结构，其特征在于，所述栅极侧墙的厚度在60nm～200nm的范围内。
15.如权利要求12所述的半导体结构，其特征在于，远离隔离结构的所述鳍部中的掺杂浓度比靠近隔离结构的所述鳍部中的掺杂浓度高1.3倍至2倍。
16.如权利要求12所述的半导体结构，其特征在于，所述半导体结构还包括：所述栅极结构两侧鳍部中的应力层，所述应力层中含有掺杂区，所述掺杂区为所述源漏掺杂区的一部分。
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