CN108630695A - 存储装置 - Google Patents

存储装置 Download PDF

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Publication number
CN108630695A
CN108630695A CN201810149169.1A CN201810149169A CN108630695A CN 108630695 A CN108630695 A CN 108630695A CN 201810149169 A CN201810149169 A CN 201810149169A CN 108630695 A CN108630695 A CN 108630695A
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layer
thickness
electrode layer
insulating layer
storage device
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CN108630695B (zh
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清水峻
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

实施方式提供一种使晶体管的动作速度提高的存储装置。实施方式的存储装置具备：多个第1电极层，在第1方向上积层；两个以上的第2电极层，在所述第1方向上积层在所述第1电极层上；信道层，在所述第1方向上贯穿所述第1电极层及所述第2电极层；以及电荷累积层，设置在所述第1电极层与所述信道层之间。所述第2电极层的所述第1方向的层厚比所述第1电极层的所述第1方向的层厚更厚。

Description

存储装置
[相关申请]
本申请享有以日本专利申请2017-49984号(申请日：2017年3月15日)作为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及一种存储装置。
背景技术
包含三维配置的存储单元的存储装置的开发不断取得进展。例如，NAND((Not-And，与非))型存储装置包含：多个电极层，积层在源极层上；信道层，将多个电极层在积层方向上贯穿；以及存储层，设置在多个电极层与信道层之间。存储单元分别配置在信道层贯穿多个电极层的部分，通过信道层与电极层之间的电位差进行动作。在这种构成的存储装置中，在沿着信道层配置的存储单元的两侧配置晶体管，控制信道层与电极层之间的电位差。然而，如果存储装置的集成度变高，那么存在晶体管的接通/断开(on/off)动作产生延迟而引起存储单元的误动作的情况。
发明内容
实施方式提供一种使晶体管的动作速度提高的存储装置。
实施方式的存储装置具备：多个第1电极层，在第1方向上积层；两个以上的第2电极层，在所述第1方向上积层在所述第1电极层上；信道层，在所述第1方向上贯穿所述第1电极层及所述第2电极层；以及电荷累积层，设置在所述第1电极层与所述信道层之间。所述第2电极层的所述第1方向的层厚比所述第1电极层的所述第1方向的层厚更厚。
附图说明
图1是示意性地表示实施方式的存储装置的立体图。
图2(a)及(b)是表示实施方式的存储装置的示意图。
图3(a)及(b)、图4(a)及(b)、图5(a)及(b)、图6(a)及(b)是表示实施方式的存储装置的制造过程的示意剖视图。
图7是表示实施方式的第1变化例的存储装置的示意剖视图。
图8是表示实施方式的第2变化例的存储装置的示意剖视图。
图9是表示实施方式的第3变化例的存储装置的示意剖视图。
图10是表示实施方式的第4变化例的存储装置的示意剖视图。
具体实施方式
以下，一边参照附图，一边对实施方式进行说明。对附图中的相同部分标注相同编号而适当省略其详细说明，并针对不同部分进行说明。此外，附图是示意性或概念性的图，各部分的厚度与宽度的关系、部分间的大小比率等未必与实物相同。另外，即便在表示相同部分的情况下，有时也根据附图而将相互的尺寸或比率不同地表示。
进而，使用各图中所示的X轴、Y轴及Z轴来说明各部分的配置及构成。X轴、Y轴及Z轴相互正交，分别表示X方向、Y方向及Z方向。另外，存在将Z方向设为上方，将Z方向的相反方向设为下方而进行说明的情况。
图1是示意性地表示实施方式的存储装置1的立体图。存储装置1例如为NAND型非易失性存储装置，包含三维配置的存储单元。
像图1所示那样，存储装置1具备导电层(以下称为源极层10)、字线20、选择栅极30a、选择栅极30b及选择栅极40。选择栅极30a及30b排列配置在字线20中的最上层20a之上。选择栅极40配置在源极层10与字线20中的最下层20b之间。
源极层10例如为设置在硅衬底(未图示)的P型阱。另外，源极层10也可为隔着层间绝缘层(未图示)设置在硅衬底(未图示)上的多晶硅层。字线20、选择栅极30a、30b及40例如为含有钨(W)的金属层。
字线20及选择栅极40分别具有平面性扩展，且积层在源极层10的表面上。以下，将字线20的积层方向设为第1方向、例如Z方向。在Z方向上相邻的字线20之间设置绝缘层13。绝缘层13例如为氧化硅层。
选择栅极30a及30b例如在X方向上排列配置在多条字线20之上。另外，选择栅极30a及选择栅极30b也可以在字线20的最上层20a之上分别积层两层以上。在最上层20a与选择栅极30a之间、及最上层20a与选择栅极30b之间也设置绝缘层13。在Z方向上相邻的选择栅极30a之间、及选择栅极30b之间设置绝缘层14。
存储装置1还具备绝缘层50及多个半导体层60。绝缘层50设置在选择栅极30a与选择栅极30b之间，且在Y方向上延伸。半导体层60贯穿字线20及选择栅极40而在Z方向上延伸。半导体层60在其下端电连接于源极层10。半导体层60例如包含：半导体层60a，贯穿选择栅极30a而在Z方向上延伸；以及半导体层60b，贯穿选择栅极30b而在Z方向上延伸。
以下，关于选择栅极30a及30b，除了个别地进行说明的情况以外，记载为选择栅极30。另外，关于半导体层60a及60b，也同样地记载为半导体层60。
存储装置1例如还具备设置在选择栅极30的上方的多条位线80、及源极线90。半导体层60a中的1个及半导体层60b中的1个电连接于共通的位线80。半导体层60经由接触插塞83而电连接于位线80。源极线90经由源极接触件70而电连接于源极层10。像图1所示那样，源极接触件70沿着多条字线20各自的侧面及选择栅极30的侧面在Y方向及Z方向上延伸。
在图1中，为了表示存储装置1的构造，省略了设置在选择栅极30与位线80之间的层间绝缘层21、及设置在源极接触件70与字线20、选择栅极30及40之间的绝缘层23(参照图2(a))。
图2(a)及2(b)是表示实施方式的存储装置1的一部分的示意图。图2(a)是表示沿X-Z平面的截面的一部分的示意图。图2(b)是表示选择栅极30a及30b的上表面的示意俯视图。以下，参照图2(a)及2(b)，对存储装置1的构造详细地进行说明。
存储装置1具有设置于在Z方向上贯穿多条字线20及选择栅极30的存储器孔MH的内部的半导体层60及绝缘层65、以及绝缘性芯67。绝缘性芯67在存储器孔MH的内部在Z方向上延伸。半导体层60以包围绝缘性芯67的侧面的方式设置，且沿着绝缘性芯67在Z方向上延伸。绝缘层65在存储器孔MH的内壁与半导体层60之间在Z方向上延伸。绝缘层65以包围半导体层60的侧面的方式设置。
在半导体层60贯穿字线20的部分，分别设置存储单元MC。在绝缘层65中，位于半导体层60与字线20之间的部分作为存储单元MC的电荷累积部而发挥功能。半导体层60作为多个存储单元MC所共有的信道而发挥功能，各字线20作为存储单元MC的控制栅极而发挥功能。
绝缘层65例如具有在存储器孔MH的内壁上积层氧化硅及氮化硅以及另一氧化硅而成的ONO(Oxide-Nitride-Oxide，氧化物-氮化物-氧化物)构造，可保持从半导体层60注入的电荷，另外，将该电荷放出到半导体层60。
另外，在半导体层60贯穿选择栅极30及40的部分，设置选择晶体管STD、STS。半导体层60也作为选择晶体管STD、STS的信道而发挥功能，选择栅极30及40分别作为选择晶体管STD、STS的栅极电极而发挥功能。位于半导体层60与选择栅极30之间、及半导体层60与选择栅极40之间的绝缘层65的一部分作为栅极绝缘膜而发挥功能。
于在X方向上相邻的字线20间、选择栅极30间及选择栅极间，设置源极接触件70。源极接触件70例如为在Y方向及Z方向上延伸的板状金属层，且将源极层10与源极线90(参照图1)电连接。源极接触件70利用绝缘层23而与字线20、选择栅极30及40电绝缘。
配置在字线20的上方的选择栅极30由绝缘层50分断。绝缘层50例如为氧化硅层，在Y方向上延伸。选择栅极30例如被分断为选择栅极30a及选择栅极30b(参照图1)。由此，将选择栅极30a作为栅极电极的选择晶体管STD能够控制贯穿字线20与选择栅极30a的半导体层60a的电位，将选择栅极30b作为栅极电极的选择晶体管STD能够控制贯穿字线20与选择栅极30b的半导体层60b的电位。由此，可将半导体层60a及60b这两者连接在1条位线80。
例如，如果不设置绝缘层50，那么只能将半导体层60a及60b中的任一者连接在1条位线80。也就是说，通过设置绝缘层50，能将位线80的条数减半，例如能缩小连接在位线80的读出放大器的电路规模。
像图2(b)所示那样，绝缘层50在Y方向上延伸，将选择栅极30分断为选择栅极30a及30b。在选择栅极30a及30b分别设置存储器孔MHA及MHB。存储器孔MHA及MHB分别包含半导体层60、绝缘层65及绝缘性芯67。进而，也可以设置将绝缘层50分断的存储器孔MHD。存储器孔MHD例如是为了增大用来形成存储器孔MH的光刻法中的曝光容限而形成。因此，设置在存储器孔MHD内的半导体层60不连接到位线80，且不使存储单元MC动作。
选择栅极30a及30b例如在Y方向的端部电连接于行解码器(未图示)。行解码器经由选择栅极30a及30b而将栅极电位供给到选择晶体管STD。选择栅极30a及30b例如在Y方向上较长地延伸，因此为了对共有各选择栅极的所有选择晶体管STD供给均匀的电位，理想的是选择栅极30a及30b的电阻值更小。
像图2(b)所示那样，因为在选择栅极30a及30b设置多个存储器孔MHA及MHB，所以各自的边缘部分30e主要有助于导电。例如，字线20因未被绝缘层50分断，所以X方向上的两侧的边缘部分有助于导电。相对于此，在选择栅极30a及30b中，分别只单侧的边缘部分30e有助于导电，因此电阻例如成为字线20的2倍。
如果选择栅极30的电阻值变大，那么例如栅极电位的上升会产生延迟。因此，在对存储单元MC写入数据时，将不包含选择单元的存储器串的选择晶体管STD断开的时序延迟，而有产生对存储单元MC的误写入的担忧。
因此，在本实施方式的存储装置1中，使选择栅极30的Z方向的层厚T2比字线20的Z方向的层厚T1更厚。例如，如果将选择栅极30的层厚T2设为字线20的层厚T1的2倍，那么选择栅极30的Y方向的电阻值变为与字线20的Y方向的电阻值大致相同，能够消除选择晶体管STD的延迟。另外，为了使下述存储器孔MH等的加工变得容易，理想的是不使选择栅极30的层厚T2厚到所需程度以上。例如，将选择栅极30的层厚T2设为字线20的层厚T1的2倍以下，优选为1.5倍以下。例如，将选择栅极30的层厚T2设为字线20的层厚T1的1.2倍。
接下来，参照图3～图6，对实施方式的存储装置1的制造方法进行说明。图3～图6是表示存储装置1的制造过程的示意剖视图。
像图3(a)所示那样，将积层体110形成在源极层10之上。积层体110例如包含绝缘层13、14、17、牺牲层101及103。绝缘层13、14及17例如为氧化硅层。牺牲层101及103例如为氮化硅层。
绝缘层13及牺牲层101交替地积层在源极层10之上。牺牲层101具有Z方向的层厚T1。牺牲层103及绝缘层14交替地积层在绝缘层13的最上层之上。牺牲层103积层两层以上。牺牲层103具有Z方向的层厚T2。绝缘层17设置在牺牲层103的最上层之上。
进而，沟槽105以从积层体110的上表面起将绝缘层14、17及牺牲层103分断的方式形成。沟槽105在Y方向上延伸。
像图3(b)所示那样，绝缘层50及存储器孔MH形成在积层体110。绝缘层50例如为氧化硅层，以将沟槽105嵌埋的方式形成。存储器孔MH例如使用各向异性RIE(Reactive IonEtching，反应性离子蚀刻)，以具有从积层体110的上表面到达源极层10的深度的方式形成。
像图4(a)所示那样，将半导体层60、绝缘层65及绝缘性芯67分别形成在存储器孔MH的内部。半导体层60例如为多晶硅层，且在其下端电连接于源极层10。
例如，以覆盖存储器孔MH的内表面的方式依次积层第1氧化硅层、氮化硅层及第2氧化硅层，而形成绝缘层65。接着，使形成在存储器孔MH的内壁上的绝缘层65的一部分残留，而选择性地去除形成在存储器孔MH的底面上的部分。然后，以覆盖存储器孔MH的内表面的方式形成半导体层60，进而，以将存储器孔MH的内部嵌埋的方式形成绝缘性芯67。
像图4(b)所示那样，在存储器孔MH中，在绝缘性芯67之上形成漏极区域69。漏极区域69例如通过对绝缘性芯67的上部进行回蚀并在该空间嵌埋非晶硅而形成。进而，在漏极区域69，例如离子注入作为N型杂质的磷(P)。另外，漏极区域69也可以形成为含有砷(As)、磷(P)、硼(B)、镓(Ga)中的至少一种以上的杂质元素。
在本实施方式中，选择栅极30的层厚T2比字线的层厚T1更厚地形成。因此，能够使选择晶体管STD的滚降(roll-off)等特性提高。其结果为，能够降低注入到漏极区域69的杂质的剂量及注入能量，从而能够削减制造成本。
像图5(a)所示那样，形成覆盖存储器孔MH及绝缘层17的上表面的绝缘层27。绝缘层27例如为氧化硅层。接着，形成从绝缘层27的上表面到达源极层10的深度的狭缝ST。狭缝ST例如在Y方向上延伸，将积层体110分割为多个部分。
像图5(b)所示那样，经由狭缝ST而选择性地去除牺牲层101及103。牺牲层101及103例如通过经由狭缝ST供给热磷酸等蚀刻液，而相对于绝缘层13、14、17及27选择性地被去除。
在通过去除牺牲层101及103而形成的空间101s及103s中，露出绝缘层65的一部分。另外，绝缘层13及14由形成在存储器孔MH的半导体层60、绝缘层65及绝缘性芯67支撑。由此，空间101s及103s得以保持。
像图6(a)所示那样，在空间101s及103s内形成字线20、选择栅极30及40。字线20、选择栅极30及40例如通过使用CVD(Chemical Vapor Deposition，化学气相沉积)在空间101s及103s的内部沉积含有钨等的金属层而形成。
例如，如果使牺牲层103的层厚T2过厚，那么空间103s的宽度会变宽，存在即便在空间101s内形成了成为字线20的部分之后，也会在空间103s残留空腔的情况。其结果为，存在形成在空间103s内的选择栅极30产生空隙的情况。因此，不能使牺牲层103的层厚T2增厚到所需程度以上。牺牲层103的层厚T2(也就是选择栅极30的层厚T2)优选为例如选择栅极30的电阻值变得与字线20大致相同的字线20的层厚T1的2倍以下。更优选为选择栅极30的层厚T2为字线20的层厚T1的1.5倍以下，例如为1.2倍。
像图6(b)所示那样，在狭缝ST的内部形成绝缘层23及源极接触件70。接着，形成覆盖绝缘层27的层间绝缘层21及位线80。位线80形成在层间绝缘层21之上，经由设置在层间绝缘层21中的接触插塞83而电连接于半导体层60。
进而，在未图示的部分，形成与选择栅极30连通的接触孔，且在接触孔的内部形成接触插塞。此时，如果预先将选择栅极30的层厚T2形成得较厚，那么能够避免接触孔的穿透。也就是说，能够使形成接触孔时的加工容限(process margin)变大。
像这样，在本实施方式中，通过使选择栅极30的层厚T2比字线20的层厚T1更厚，能够使选择晶体管STD的动作速度提高，从而抑制对存储单元MC的误写入等。
接下来，参照图7～图10，对本实施方式的变化例的存储装置2～5进行说明。图7～图10是表示存储装置2～5的一部分的示意剖视图。
图7是表示实施方式的第1变化例的存储装置2的示意剖视图。存储装置2中，在字线20之上积层3个选择栅极30。选择栅极30的层厚T2设置为比字线20的层厚T1更厚。进而，存储装置2以如下方式设置：将选择栅极30的层厚T2与绝缘层14的层厚T4相加所得的Z方向的层厚T6和将字线20的层厚T1与绝缘层13的层厚T3相加所得的Z方向的层厚T5大致相同。
由此，例如可使用和牺牲层101与牺牲层103具有相同的层厚并且绝缘层13与绝缘层14具有相同的层厚的情况相同的蚀刻条件，形成存储器孔MH及沟槽105。也就是说，存储器孔MH及沟槽105的蚀刻的难度不会改变。
在该例中，绝缘层14的层厚T4变得比绝缘层13的层厚T3更薄，虽然其绝缘耐压降低，但因为对多个选择栅极30供给相同的电位，所以不会对存储装置1的动作产生影响。
图8是表示实施方式的第2变化例的存储装置3的示意剖视图。存储装置3中，在字线20之上积层3个选择栅极30。选择栅极30的层厚T2设置为比字线20的层厚T1更厚。进而，在存储装置3中，绝缘层14以其层厚T4与绝缘层13的层厚T3大致相同的方式设置。
在该例中，3个选择栅极30及它们之间的绝缘层14的总厚度变厚，因此漏极区域19与字线20的最上层的间隔变宽。由此，能够抑制因GIDL(gate-induced drain leakage，栅致漏极泄漏)而引起的对存储单元MC的误写入。另外，选择晶体管STD的截止特性容限得以改善。例如，对于漏极区域19中的N型杂质的Z方向的深度不均的容限改善。另外，因成为层厚T6＞层厚T5，所以能够提高选择晶体管STD的滚降特性。
图9是表示实施方式的第3变化例的存储装置4的示意剖视图。存储装置4中，在字线20之上积层3个选择栅极30。选择栅极30的层厚T2设置为比字线20的层厚T1更厚。进而，在存储装置4中，绝缘层14以其层厚T4变得比绝缘层13的层厚T3更厚的方式设置。
在该例中，3个选择栅极30及它们之间的绝缘层14的总厚度也变厚，因此漏极区域19与字线20的最上层的间隔也变宽。由此，能够抑制因GIDL而引起的对存储单元MC的误写入。进而，能够改善选择晶体管STD的截止特性容限。例如，对于漏极区域19中的N型杂质的Z方向的深度不均的容限改善。另外，因成为层厚T6＞层厚T5，所以能够提高选择晶体管STD的滚降特性。另外，通过使绝缘层14的层厚T4变厚，能够在去除牺牲层103之后抑制绝缘层14的弯曲。由此，能够使通过去除牺牲层103而形成的空间103s的容限变大(参照图5(b))。
图10是表示实施方式的第4变化例的存储装置5的示意剖视图。存储装置4中，在字线20之上积层两个选择栅极30。选择栅极30的层厚T2设置为比字线20的层厚T1更厚。进而，在存储装置4中，两个选择栅极30的层厚2T2与两个绝缘层14的层厚2T4的和比两条字线20的层厚2T1与两个绝缘层13的层厚2T3的和更大(2T2+2T4＞2T1+2T3)。另外，两个选择栅极30的层厚2T2与两个绝缘层14的层厚2T4的和比3条字线20的层厚3T1与3个绝缘层13的层厚3T3的和更小(2T2+2T4＜3T1+3T3)、或者等于3条字线20的层厚3T1与3个绝缘层13的层厚3T3的和(2T2+2T4＝3T1+3T3)。
由此，与积层着3个选择栅极30的情况相比，能够降低存储器孔MH及沟槽105的蚀刻的难度。另外，能够使选择栅极30的总厚度(2T2)更厚，例如能够改善夹断特性。例如，即便为相同的总厚度，也不会使去除牺牲层103后的弯曲劣化，能够通过降低选择晶体管STD的栅极电阻来改善误写入特性。
所述实施方式是例示，并不限定于这些实施方式。例如，选择栅极30的积层数也可为4层以上。另外，字线20、选择栅极30及40并不限于钨，也可为含有钛的金属层，另外，也可为多晶硅层。进而，绝缘层13及14并不限定于氧化硅层，也可为氮化硅层、氧化铝层等。
对本发明的若干个实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意图限定发明的范围。这些新颖的实施方式能以其它各种方式实施，且能够在不脱离发明主旨的范围内进行各种省略、替换及变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1～5 存储装置
10 源极层
13、14、17、23、27、50、65 绝缘层
19 漏极区域
20 字线
21 层间绝缘层
30、30a、30b、40 选择栅极
30e 边缘部分
60、60a、60b 半导体层
67 绝缘性芯
69 漏极区域
70 源极接触件
80 位线
83 接触插塞
90 源极线
101、103 牺牲层
101s、103s 空间
105 沟槽
110 积层体
MC 存储单元
MH、MHA、MHB、MHD 存储器孔
ST 狭缝
STD、STS 选择晶体管

Claims (5)

1.一种存储装置，其特征在于，具备：
多个第1电极层，在第1方向上积层；
两个以上的第2电极层，在所述第1方向上积层在所述第1电极层上；
信道层，在所述第1方向上贯穿所述第1电极层及所述第2电极层；以及
电荷累积层，设置在所述第1电极层与所述信道层之间；且
所述第2电极层的所述第1方向的层厚比所述第1电极层的所述第1方向的层厚更厚。
2.根据权利要求1所述的存储装置，其特征在于还具备：
第1绝缘层，设置在所述第1电极层中的在所述第1方向上相邻的第1电极层之间；以及
第2绝缘层，设置在所述第2电极层中的在所述第1方向上相邻的第2电极层之间；且
所述第2绝缘层的所述第1方向的层厚与所述第1绝缘层的所述第1方向的层厚大致相同。
3.根据权利要求1所述的存储装置，其特征在于还具备：
第1绝缘层，设置在所述第1电极层中的在所述第1方向上相邻的第1电极层之间；以及
第2绝缘层，设置在所述第2电极层中的在所述第1方向上相邻的第2电极层之间；且
所述第2绝缘层的所述第1方向的层厚比所述第1绝缘层的所述第1方向的层厚更薄。
4.根据权利要求1所述的存储装置，其特征在于还具备：
第1绝缘层，设置在所述第1电极层中的在所述第1方向上相邻的第1电极层之间；以及
第2绝缘层，设置在所述第2电极层中的在所述第1方向上相邻的第2电极层之间；且
所述第2绝缘层的所述第1方向的层厚比所述第1绝缘层的所述第1方向的层厚更厚。
5.根据权利要求1至4中任一项所述的存储装置，其特征在于还具备：
两个以上的第3电极层，在所述第1方向上积层在所述第1电极层上，且相对于所述第2电极层配置在与所述第1方向正交的第2方向；以及
绝缘体，设置在所述第2电极层与所述第3电极层之间；且
所述第3电极层的所述第1方向的层厚比所述第1电极层的所述第1方向的层厚更厚。
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