TWI676274B - 記憶裝置 - Google Patents

記憶裝置 Download PDF

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TWI676274B
TWI676274B TW107101973A TW107101973A TWI676274B TW I676274 B TWI676274 B TW I676274B TW 107101973 A TW107101973 A TW 107101973A TW 107101973 A TW107101973 A TW 107101973A TW I676274 B TWI676274 B TW I676274B
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Taiwan
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layer
insulating layer
memory device
thickness
electrode
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TW107101973A
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TW201843818A (zh
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清水峻
Shun Shimizu
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日商東芝記憶體股份有限公司
Toshiba Memory Corporation
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Abstract

實施形態提供一種使電晶體之動作速度提高之記憶裝置。 實施形態之記憶裝置具備：複數個第1電極層，其等於第1方向積層；兩個以上之第2電極層，其等於上述第1方向上積層於上述第1電極層上；通道層，其於上述第1方向貫穿上述第1電極層及上述第2電極層；以及電荷累積層，其設置於上述第1電極層與上述通道層之間。上述第2電極層之上述第1方向之層厚較上述第1電極層之上述第1方向之層厚更厚。

Description

記憶裝置
實施形態係關於一種記憶裝置。
包含三維配置之記憶胞之記憶裝置之開發不斷取得進展。例如，NAND((Not-And，反及))型記憶裝置包含：複數個電極層，其等積層於源極層上；通道層，其將複數個電極層於積層方向上貫穿；以及記憶層，其設置於複數個電極層與通道層之間。記憶胞分別配置於通道層貫穿複數個電極層之部分，藉由通道層與電極層之間之電位差進行動作。於此種構成之記憶裝置中，於沿通道層配置之記憶胞之兩側配置電晶體，控制通道層與電極層之間之電位差。然而，若記憶裝置之積體度變高，則存在電晶體之接通/斷開(on/off)動作產生延遲而引起記憶胞之誤動作之情形。
實施形態提供一種使電晶體之動作速度提高之記憶裝置。 實施形態之記憶裝置具備：複數個第1電極層，其等於第1方向積層；兩個以上之第2電極層，其等於上述第1方向上積層於上述第1電極層上；通道層，其於上述第1方向貫穿上述第1電極層及上述第2電極層；以及電荷累積層，其設置於上述第1電極層與上述通道層之間。上述第2電極層之上述第1方向之層厚較上述第1電極層之上述第1方向之層厚更厚。
以下，一面參照圖式，一面對實施形態進行說明。對圖式中之相同部分標註相同編號而適當省略其詳細說明，並針對不同部分進行說明。再者，圖式係模式性或概念性之圖，各部分之厚度與寬度之關係、部分間之大小比率等未必與實物相同。又，即便於表示相同部分之情形時，有時亦根據圖式而將相互之尺寸或比率不同地表示。 進而，使用各圖中所示之X軸、Y軸及Z軸而說明各部分之配置及構成。X軸、Y軸及Z軸相互正交，分別表示X方向、Y方向及Z方向。又，存在將Z方向設為上方，將其相反方向設為下方而進行說明之情形。 圖1係模式性地表示實施形態之記憶裝置1之立體圖。記憶裝置1例如為NAND型非揮發性記憶裝置，包含三維配置之記憶胞。 如圖1所示，記憶裝置1具備導電層(以下稱為源極層10)、字元線20、選擇閘極30a、選擇閘極30b及選擇閘極40。選擇閘極30a及30b排列配置於字元線20中之最上層20a之上。選擇閘極40配置於源極層10與字元線20中之最下層20b之間。 源極層10例如為設置於矽基板(未圖示)之P型井。又，源極層10亦可為介隔層間絕緣層(未圖示)設置於矽基板(未圖示)上之多晶矽層。字元線20、選擇閘極30a、30b及40例如為含有鎢(W)之金屬層。 字元線20及選擇閘極40分別具有平面性擴展，且積層於源極層10之表面上。以下，將字元線20之積層方向設為第1方向、例如Z方向。於Z方向上相鄰之字元線20之間設置絕緣層13。絕緣層13例如為氧化矽層。 選擇閘極30a及30b例如於X方向上排列配置於複數條字元線20之上。又，選擇閘極30a及選擇閘極30b亦可於字元線20之最上層20a之上分別積層兩層以上。於最上層20a與選擇閘極30a之間、及最上層20a與選擇閘極30b之間亦設置絕緣層13。於Z方向上相鄰之選擇閘極30a之間、及選擇閘極30b之間設置絕緣層14。 記憶裝置1進而具備絕緣層50及複數個半導體層60。絕緣層50設置於選擇閘極30a與選擇閘極30b之間，且於Y方向上延伸。半導體層60貫穿字元線20及選擇閘極40而於Z方向上延伸。半導體層60於其下端電性連接於源極層10。半導體層60例如包含：半導體層60a，其貫穿選擇閘極30a而於Z方向上延伸；及半導體層60b，其貫穿選擇閘極30b而於Z方向上延伸。 以下，關於選擇閘極30a及30b，除了個別地進行說明之情形以外，記載為選擇閘極30。又，關於半導體層60a及60b，亦同樣地記載為半導體層60。 記憶裝置1例如進而具備設置於選擇閘極30之上方之複數條位元線80、及源極線90。半導體層60a中之1個及半導體層60b中之1個電性連接於共通之位元線80。半導體層60經由接觸插塞83而電性連接於位元線80。源極線90經由源極接觸件70而電性連接於源極層10。如圖1所示，源極接觸件70沿複數條字元線20之各者之側面及選擇閘極30之側面於Y方向及Z方向上延伸。 於圖1中，為了表示記憶裝置1之構造，省略設置於選擇閘極30與位元線80之間之層間絕緣層21、及設置於源極接觸件70與字元線20、選擇閘極30及40之間之絕緣層23(參照圖2(a))。 圖2(a)及2(b)係表示實施形態之記憶裝置1之一部分之模式圖。圖2(a)係表示沿X-Z平面之剖面之一部分之模式圖。圖2(b)係表示選擇閘極30a及30b之上表面之模式俯視圖。以下，參照圖2(a)及2(b)，對記憶裝置1之構造詳細地進行說明。 記憶裝置1具有設置於在Z方向上貫穿複數條字元線20及選擇閘極30之記憶體孔MH之內部之半導體層60及絕緣層65、以及絕緣性芯67。絕緣性芯67於記憶體孔MH之內部於Z方向上延伸。半導體層60以包圍絕緣性芯67之側面之方式設置，且沿絕緣性芯67於Z方向上延伸。絕緣層65於記憶體孔MH之內壁與半導體層60之間於Z方向上延伸。絕緣層65以包圍半導體層60之側面之方式設置。 於半導體層60貫穿字元線20之部分，分別設置記憶胞MC。於絕緣層65中，位於半導體層60與字元線20之間之部分作為記憶胞MC之電荷累積部而發揮功能。半導體層60作為複數個記憶胞MC所共有之通道而發揮功能，各字元線20作為記憶胞MC之控制閘極而發揮功能。 絕緣層65例如具有於記憶體孔MH之內壁上積層氧化矽及氮化矽以及另一氧化矽而成之ONO(Oxide-Nitride-Oxide，氧化物-氮化物-氧化物)構造，可保持自半導體層60注入之電荷，又，將該電荷放出至半導體層60。 又，於半導體層60貫穿選擇閘極30及40之部分，設置選擇電晶體STD、STS。半導體層60亦作為選擇電晶體STD、STS之通道而發揮功能，選擇閘極30及40分別作為選擇電晶體STD、STS之閘極電極而發揮功能。位於半導體層60與選擇閘極30之間、及半導體層60與選擇閘極40之間之絕緣層65之一部分作為閘極絕緣膜而發揮功能。 於在X方向上相鄰之字元線20間、選擇閘極30間及選擇閘極間，設置源極接觸件70。源極接觸件70例如為於Y方向及Z方向上延伸之板狀金屬層，且將源極層10與源極線90(參照圖1)電性連接。源極接觸件70利用絕緣層23而與字元線20、選擇閘極30及40電性絕緣。 配置於字元線20之上方之選擇閘極30由絕緣層50分斷。絕緣層50例如為氧化矽層，於Y方向上延伸。選擇閘極30例如被分斷為選擇閘極30a及選擇閘極30b(參照圖1)。藉此，將選擇閘極30a作為閘極電極之選擇電晶體STD能夠控制貫穿字元線20與選擇閘極30a之半導體層60a之電位，將選擇閘極30b作為閘極電極之選擇電晶體STD能夠控制貫穿字元線20與選擇閘極30b之半導體層60b之電位。藉此，可將半導體層60a及60b之兩者連接於1條位元線80。 例如，若不設置絕緣層50，則只能將半導體層60a及60b中之任一者連接於1條位元線80。即，藉由設置絕緣層50，能將位元線80之條數減半，例如能縮小連接於位元線80之感測放大器之電路規模。 如圖2(b)所示，絕緣層50於Y方向上延伸，將選擇閘極30分斷為選擇閘極30a及30b。於選擇閘極30a及30b分別設置記憶體孔MHA及MHB。記憶體孔MHA及MHB分別包含半導體層60、絕緣層65及絕緣性芯67。進而，亦可設置將絕緣層50分斷之記憶體孔MHD。記憶體孔MHD例如係為了增大用以形成記憶體孔MH之光微影法中之曝光容限而形成。因此，設置於記憶體孔MHD內之半導體層60不連接至位元線80，且不使記憶胞MC動作。 選擇閘極30a及30b例如於Y方向之端部電性連接於列解碼器(未圖示)。列解碼器經由選擇閘極30a及30b而將閘極電位供給至選擇電晶體STD。選擇閘極30a及30b例如於Y方向上較長地延伸，因此為了對共有各選擇閘極之所有選擇電晶體STD供給均勻之電位，理想為選擇閘極30a及30b之電阻值更小。 如圖2(b)所示，由於在選擇閘極30a及30b設置複數個記憶體孔MHA及MHB，故而各者之邊緣部分30e主要有助於導電。例如，字元線20因未被絕緣層50分斷，故而X方向上之兩側之邊緣部分有助於導電。相對於此，於選擇閘極30a及30b中，僅各自單側之邊緣部分30e有助於導電，因此電阻例如為字元線20之2倍。 若選擇閘極30之電阻值變大，則例如閘極電位之上升會產生延遲。因此，於對記憶胞MC寫入資料時，將不包含選擇單元之記憶體串之選擇電晶體STD斷開之時序延遲，而有產生對記憶胞MC之誤寫入之疑慮。 因此，於本實施形態之記憶裝置1中，使選擇閘極30之Z方向之層厚T2 較字元線20之Z方向之層厚T1 更厚。例如，若將選擇閘極30之層厚T2 設為字元線20之層厚T1 之2倍，則選擇閘極30之Y方向之電阻值變為與字元線20之Y方向之電阻值大致相同，能夠消除選擇電晶體STD之延遲。又，為了使下述記憶體孔MH等之加工變得容易，理想為不使選擇閘極30之層厚T2 厚達所需程度以上。例如，將選擇閘極30之層厚T2 設為字元線20之層厚T1 之2倍以下，較佳為1.5倍以下。例如，將選擇閘極30之層厚T2 設為字元線20之層厚T1 之1.2倍。 其次，參照圖3～圖6，對實施形態之記憶裝置1之製造方法進行說明。圖3～圖6係表示記憶裝置1之製造過程之模式剖視圖。 如圖3(a)所示，將積層體110形成於源極層10之上。積層體110例如包含絕緣層13、14、17、犧牲層101及103。絕緣層13、14及17例如為氧化矽層。犧牲層101及103例如為氮化矽層。 絕緣層13及犧牲層101交替地積層於源極層10之上。犧牲層101具有Z方向之層厚T1 。犧牲層103及絕緣層14交替地積層於絕緣層13之最上層之上。將犧牲層103積層兩層以上。犧牲層103具有Z方向之層厚T2 。絕緣層17設置於犧牲層103之最上層之上。 進而，溝槽105以自積層體110之上表面起將絕緣層14、17及犧牲層103分斷之方式形成。溝槽105於Y方向上延伸。 如圖3(b)所示，絕緣層50及記憶體孔MH形成於積層體110。絕緣層50例如為氧化矽層，以將溝槽105嵌埋之方式形成。記憶體孔MH例如使用各向異性RIE(Reactive Ion Etching，反應性離子蝕刻)，以具有自積層體110之上表面到達源極層10之深度之方式形成。 如圖4(a)所示，將半導體層60、絕緣層65及絕緣性芯67分別形成於記憶體孔MH之內部。半導體層60例如為多晶矽層，且於其下端電性連接於源極層10。 例如，以覆蓋記憶體孔MH之內表面之方式依次積層第1氧化矽層、氮化矽層及第2氧化矽層，而形成絕緣層65。繼而，使形成於記憶體孔MH之內壁上之絕緣層65之一部分殘留，而選擇性地去除形成於記憶體孔MH之底面上之部分。其後，以覆蓋記憶體孔MH之內表面之方式形成半導體層60，進而，以將記憶體孔MH之內部嵌埋之方式形成絕緣性芯67。 如圖4(b)所示，於記憶體孔MH中，於絕緣性芯67之上形成汲極區域69。汲極區域69例如藉由對絕緣性芯67之上部進行回蝕並於該空間嵌埋非晶矽而形成。進而，於汲極區域69，例如離子注入作為N型雜質之磷(P)。又，汲極區域69亦可形成為含有砷(As)、磷(P)、硼(B)、鎵(Ga)中之至少一種以上之雜質元素。 於本實施形態中，選擇閘極30之層厚T2 較字元線之層厚T1 更厚地形成。因此，能夠使選擇電晶體STD之滾降(roll-off)等特性提高。其結果，能夠降低注入至汲極區域69之雜質之劑量及注入能量，從而能夠削減製造成本。 如圖5(a)所示，形成覆蓋記憶體孔MH及絕緣層17之上表面之絕緣層27。絕緣層27例如為氧化矽層。繼而，形成自絕緣層27之上表面到達源極層10之深度之狹縫ST。狹縫ST例如於Y方向上延伸，將積層體110分割為複數個部分。 如圖5(b)所示，經由狹縫ST而選擇性地去除犧牲層101及103。犧牲層101及103例如藉由經由狹縫ST供給熱磷酸等蝕刻液，而相對於絕緣層13、14、17及27選擇性地被去除。 於藉由去除犧牲層101及103而形成之空間101s及103s中，露出絕緣層65之一部分。又，絕緣層13及14由形成於記憶體孔MH之半導體層60、絕緣層65及絕緣性芯67支持。藉此，空間101s及103s得以保持。 如圖6(a)所示，於空間101s及103s內形成字元線20、選擇閘極30及40。字元線20、選擇閘極30及40例如藉由使用CVD(Chemical Vapor Deposition，化學氣相沈積)於空間101s及103s之內部沈積含有鎢等之金屬層而形成。 例如，若使犧牲層103之層厚T2 過厚，則空間103s之寬度會變寬，存在即便於空間101s內形成了成為字元線20之部分之後，亦會於空間103s殘留空腔之情形。其結果，存在形成於空間103s內之選擇閘極30產生空隙之情況。因此，不能使犧牲層103之層厚T2 增厚至所需程度以上。犧牲層103之層厚T2 (即選擇閘極30之層厚T2 )較佳為例如選擇閘極30之電阻值變得與字元線20大致相同之字元線20之層厚T1 之2倍以下。更佳為選擇閘極30之層厚T2 為字元線20之層厚T1 之1.5倍以下，例如為1.2倍。 如圖6(b)所示，於狹縫ST之內部形成絕緣層23及源極接觸件70。繼而，形成覆蓋絕緣層27之層間絕緣層21及位元線80。位元線80形成於層間絕緣層21之上，經由設置於層間絕緣層21中之接觸插塞83而電性連接於半導體層60。 進而，於未圖示之部分，形成與選擇閘極30連通之接觸孔，且於接觸孔之內部形成接觸插塞。此時，若預先將選擇閘極30之層厚T2 形成得較厚，則能夠避免接觸孔之穿透。即，能夠使形成接觸孔時之加工容限(process margin)變大。 如此，於本實施形態中，藉由使選擇閘極30之層厚T2 較字元線20之層厚T1 更厚，能夠使選擇電晶體STD之動作速度提高，從而抑制對記憶胞MC之誤寫入等。 其次，參照圖7～圖10，對本實施形態之變化例之記憶裝置2～5進行說明。圖7～圖10係表示記憶裝置2～5之一部分之模式剖視圖。 圖7係表示實施形態之第1變化例之記憶裝置2之模式剖視圖。記憶裝置2中，於字元線20之上積層3個選擇閘極30。選擇閘極30之層厚T2 設置為較字元線20之層厚T1 更厚。進而，記憶裝置2設置為，將選擇閘極30之層厚T2 與絕緣層14之層厚T4 相加所得之Z方向之層厚T6 ，和將字元線20之層厚T1 與絕緣層13之層厚T3 相加所得之Z方向之層厚T5 大致相同。 藉此，例如可使用與犧牲層101及犧牲層103具有相同之層厚並且絕緣層13與絕緣層14具有相同之層厚之情形相同之蝕刻條件，形成記憶體孔MH及溝槽105。即，記憶體孔MH及溝槽105之蝕刻之難度不變。 於該例中，絕緣層14之層厚T4 變得較絕緣層13之層厚T3 更薄，雖然其絕緣耐壓降低，但由於對複數個選擇閘極30供給相同之電位，故而不會對記憶裝置1之動作產生影響。 圖8係表示實施形態之第2變化例之記憶裝置3之模式剖視圖。記憶裝置3中，於字元線20之上積層3個選擇閘極30。選擇閘極30之層厚T2 設置為較字元線20之層厚T1 更厚。進而，於記憶裝置3中，絕緣層14以其層厚T4 與絕緣層13之層厚T3 大致相同之方式設置。 於該例中，3個選擇閘極30及其等之間之絕緣層14之總厚度變厚，因此汲極區域19與字元線20之最上層之間隔變寬。藉此，能夠抑制因GIDL(gate-induced drain leakage，閘致汲極洩漏)而引起之對記憶胞MC之誤寫入。又，選擇電晶體STD之截止特性容限得以改善。例如，對於汲極區域19中之N型雜質之Z方向之深度不均之容限改善。又，因層厚T6 ＞層厚T5 ，故而能夠提高選擇電晶體STD之滾降特性。 圖9係表示實施形態之第3變化例之記憶裝置4之模式剖視圖。記憶裝置4中，於字元線20之上積層3個選擇閘極30。選擇閘極30之層厚T2 設置為較字元線20之層厚T1 更厚。進而，於記憶裝置4中，絕緣層14以其層厚T4 變得較絕緣層13之層厚T3 更厚之方式設置。 於該例中，3個選擇閘極30及其等之間之絕緣層14之總厚度亦變厚，因此汲極區域19與字元線20之最上層之間隔亦變寬。藉此，能夠抑制因GIDL而引起之對記憶胞MC之誤寫入。進而，能夠改善選擇電晶體STD之截止特性容限。例如，對於汲極區域19中之N型雜質之Z方向之深度不均之容限改善。又，因成為層厚T6 ＞層厚T5 ，故而能夠提高選擇電晶體STD之滾降特性。又，藉由使絕緣層14之層厚T4 變厚，能夠於去除犧牲層103之後抑制絕緣層14之彎曲。藉此，能夠使藉由去除犧牲層103而形成之空間103s之容限變大(參照圖5(b))。 圖10係表示實施形態之第4變化例之記憶裝置5之模式剖視圖。記憶裝置4中，於字元線20之上積層兩個選擇閘極30。選擇閘極30之層厚T2 設置為較字元線20之層厚T1 更厚。進而，於記憶裝置4中，兩個選擇閘極30之層厚2T2 與兩個絕緣層14之層厚2T4 之和較兩條字元線20之層厚2T1 與兩個絕緣層13之層厚2T3 之和更大(2T2 ＋2T4 ＞2T1 ＋2T3 )。又，兩個選擇閘極30之層厚2T2 與兩個絕緣層14之層厚2T4 之和較3條字元線20之層厚3T1 與3個絕緣層13之層厚3T3 之和更小(2T2 ＋2T4 ＜3T1 ＋3T3 )、或者等於3條字元線20之層厚3T1 與3個絕緣層13之層厚3T3 之和(2T2 ＋2T4 ＝3T1 ＋3T3 )。 藉此，與積層有3個選擇閘極30之情形相比，能夠降低記憶體孔MH及溝槽105之蝕刻之難度。又，能夠使選擇閘極30之總厚度(2T2 )更厚，例如能夠改善夾斷特性。例如，即便為相同之總厚度，亦不會使去除犧牲層103後之彎曲劣化，能夠藉由降低選擇電晶體STD之閘極電阻而改善誤寫入特性。 上述實施形態係例示，並不限定於該等實施形態。例如，選擇閘極30之積層數亦可為4層以上。又，字元線20、選擇閘極30及40並不限於鎢，亦可為含有鈦之金屬層，又，亦可為多晶矽層。進而，絕緣層13及14並不限定於氧化矽層，亦可為氮化矽層、氧化鋁層等。 對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出者，並非意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態實施，且能夠於不脫離發明主旨之範圍內進行各種省略、替換及變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。 [相關申請案] 本申請案享有以日本專利申請案2017-49984號(申請日：2017年3月15日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1‧‧‧記憶裝置
2‧‧‧記憶裝置
3‧‧‧記憶裝置
4‧‧‧記憶裝置
5‧‧‧記憶裝置
10‧‧‧源極層
13‧‧‧絕緣層
14‧‧‧絕緣層
17‧‧‧絕緣層
19‧‧‧汲極區域
20‧‧‧字元線
20a‧‧‧最上層
20b‧‧‧最下層
21‧‧‧層間絕緣層
23‧‧‧絕緣層
27‧‧‧絕緣層
30‧‧‧選擇閘極
30a‧‧‧選擇閘極
30b‧‧‧選擇閘極
30e‧‧‧邊緣部分
40‧‧‧選擇閘極
50‧‧‧絕緣層
60‧‧‧半導體層
60a‧‧‧半導體層
60b‧‧‧半導體層
65‧‧‧絕緣層
67‧‧‧絕緣性芯
69‧‧‧汲極區域
70‧‧‧源極接觸件
80‧‧‧位元線
83‧‧‧接觸插塞
90‧‧‧源極線
101‧‧‧犧牲層
101s‧‧‧空間
103‧‧‧犧牲層
103s‧‧‧空間
105‧‧‧溝槽
110‧‧‧積層體
MC‧‧‧記憶胞
MH‧‧‧記憶體孔
MHA‧‧‧記憶體孔
MHB‧‧‧記憶體孔
MHD‧‧‧記憶體孔
ST‧‧‧狹縫
STD‧‧‧選擇電晶體
STS‧‧‧選擇電晶體
T1‧‧‧層厚
T2‧‧‧層厚
T3‧‧‧層厚
T4‧‧‧層厚
T5‧‧‧層厚
T6‧‧‧層厚
X‧‧‧軸
Y‧‧‧軸
Z‧‧‧軸
圖1係模式性地表示實施形態之記憶裝置之立體圖。 圖2(a)及(b)係表示實施形態之記憶裝置之模式圖。 圖3(a)～圖6(b)係表示實施形態之記憶裝置之製造過程之模式剖視圖。 圖7係表示實施形態之第1變化例之記憶裝置之模式剖視圖。 圖8係表示實施形態之第2變化例之記憶裝置之模式剖視圖。 圖9係表示實施形態之第3變化例之記憶裝置之模式剖視圖。 圖10係表示實施形態之第4變化例之記憶裝置之模式剖視圖。

Claims (5)

  1. 一種記憶裝置，其具備： 複數個第1電極層，其等於第1方向積層； 兩個以上之第2電極層，其等於上述第1方向上積層於上述第1電極層上； 通道層，其於上述第1方向貫穿上述第1電極層及上述第2電極層；以及 電荷累積層，其設置於上述第1電極層與上述通道層之間；且 上述第2電極層之上述第1方向之層厚較上述第1電極層之上述第1方向之層厚更厚。
  2. 如請求項1之記憶裝置，其進而具備： 第1絕緣層，其設置於上述第1電極層中之於上述第1方向上相鄰之第1電極層之間；以及 第2絕緣層，其設置於上述第2電極層中之於上述第1方向上相鄰之第2電極層之間；且 上述第2絕緣層之上述第1方向之層厚與上述第1絕緣層之上述第1方向之層厚大致相同。
  3. 如請求項1之記憶裝置，其進而具備： 第1絕緣層，其設置於上述第1電極層中之於上述第1方向上相鄰之第1電極層之間；以及 第2絕緣層，其設置於上述第2電極層中之於上述第1方向上相鄰之第2電極層之間；且 上述第2絕緣層之上述第1方向之層厚較上述第1絕緣層之上述第1方向之層厚更薄。
  4. 如請求項1之記憶裝置，其進而具備： 第1絕緣層，其設置於上述第1電極層中之於上述第1方向上相鄰之第1電極層之間；以及 第2絕緣層，其設置於上述第2電極層中之於上述第1方向上相鄰之第2電極層之間；且 上述第2絕緣層之上述第1方向之層厚較上述第1絕緣層之上述第1方向之層厚更厚。
  5. 如請求項1至4中任一項之記憶裝置，其進而具備： 兩個以上之第3電極層，其等於上述第1方向上積層於上述第1電極層上，且相對於上述第2電極層配置於與上述第1方向正交之第2方向；以及 絕緣體，其設置於上述第2電極層與上述第3電極層之間；且 上述第3電極層之上述第1方向之層厚較上述第1電極層之上述第1方向之層厚更厚。
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