US9960179B2 - Semiconductor memory device and method for manufacturing same - Google Patents

Semiconductor memory device and method for manufacturing same Download PDF

Info

Publication number
US9960179B2
US9960179B2 US15/463,582 US201715463582A US9960179B2 US 9960179 B2 US9960179 B2 US 9960179B2 US 201715463582 A US201715463582 A US 201715463582A US 9960179 B2 US9960179 B2 US 9960179B2
Authority
US
United States
Prior art keywords
layer
semiconductor
electrode
insulating body
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US15/463,582
Other versions
US20180083031A1 (en
Inventor
Kenta Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Priority to US15/463,582 priority Critical patent/US9960179B2/en
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAMADA, KENTA
Assigned to TOSHIBA MEMORY CORPORATION reassignment TOSHIBA MEMORY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KABUSHIKI KAISHA TOSHIBA
Publication of US20180083031A1 publication Critical patent/US20180083031A1/en
Application granted granted Critical
Publication of US9960179B2 publication Critical patent/US9960179B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H01L27/11582—
    • H01L21/28282—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H01L27/1157—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

Definitions

  • Embodiments are generally related to a semiconductor memory device and a method for manufacturing the same.
  • a semiconductor memory device is under developing, which includes three-dimensionally disposed memory cells.
  • a NAND type flash memory device has a structure in which a semiconductor channel body extends through a plurality of word lines stacked on a source layer, and the memory cells are arranged in portions respectively where the channel body extends through the word lines.
  • the channel body becomes longer, and the on-current is reduced which flows therethrough.
  • FIG. 1 is a perspective view schematically showing a semiconductor memory device according to a first embodiment
  • FIG. 2 is a schematic cross-sectional view showing the semiconductor memory device according to the first embodiment
  • FIGS. 3A to 3L are schematic cross-sectional views showing a manufacturing process of the semiconductor memory device according to the first embodiment
  • FIG. 4 is a schematic cross-sectional view showing a semiconductor memory device according to a variation of the first embodiment
  • FIG. 5 is a schematic cross-sectional view showing a semiconductor memory device according to a second embodiment
  • FIGS. 6A to 6C are schematic cross-sectional views showing a manufacturing process of the semiconductor memory device according to the second embodiment.
  • FIG. 7 is a schematic cross-sectional view showing a semiconductor memory device according to a variation of the second embodiment.
  • a semiconductor memory device includes a conductive layer; a plurality of electrode layers stacked on the conductive layer; an insulating body extending through the plurality of electrode layers; and a semiconductor layer positioned between the insulating body and the plurality of electrode layers, the semiconductor layer extending along the insulating body.
  • the plurality of electrode layers include a first electrode layer, a second electrode layer provided between the conductive layer and the first electrode layer, and a third electrode layer provided between the conductive layer and the second electrode layer
  • the semiconductor layer has a first layer thickness in a direction from the insulating body to the first electrode layer between the insulating body and the first electrode layer, a second layer thickness in a direction from the insulating body to the second electrode layer between the insulating body and the second electrode layer and a third layer thickness in a direction from the insulating body to the third electrode layer between the insulating body and the third electrode layer.
  • the first layer thickness is thinner than the second layer thickness
  • the second layer thickness is thinner than the third layer thickness.
  • FIG. 1 is a perspective view schematically showing a memory cell array MCA of a semiconductor memory device 1 according to a first embodiment.
  • the semiconductor memory device 1 is, for example, a NAND type memory device and includes three-dimensionally disposed memory cells MC.
  • the semiconductor memory device 1 includes, for example, a source layer 10 provided on a silicon substrate (not shown), and a stacked body 100 .
  • a plurality of stacked bodies 100 are arranged, for example, in the Y direction on the source layer 10 .
  • the adjacent stacked bodies 100 in the Y direction are separated by a slit space SL.
  • the stacked body 100 includes a plurality of electrode layers (hereinafter, word lines 20 , selection gates 30 and 40 ) stacked in the Z direction.
  • the selection gate 30 is provided on the source layer 10 with an insulating layer 13 interposed.
  • the word lines 20 are stacked on the select gate 30 .
  • the interlayer insulating layers 15 are provided between the selection gate 30 and the lowermost word line 20 and between the adjacent word lines 20 in the Z direction.
  • the selection gate 40 is provided on the uppermost word line 20 via another interlayer insulating layer 15 .
  • the source layer 10 is, for example, a P-type well provided in a silicon substrate.
  • the word lines 20 , the select gates 30 and 40 are, for example, metal layers or low resistance polycrystalline silicon layers.
  • the insulating layers 13 and 15 are, for example, silicon oxide layers.
  • the stacked body 100 includes, for example, a plurality of columnar bodies CL extending through the word lines 20 and the selection gate 40 and extending in the Z direction.
  • the columnar bodies CL each include a semiconductor layer 50 (see FIG. 2 ).
  • the stacked body 100 may include, for example, a semiconductor channel body (hereinafter referred to as a channel body 60 ) located between each of the columnar bodies CL and the source layer 10 , and extending through the selection gate 30 in the Z direction.
  • the memory cell array MCA includes a plurality of stacked bodies 100 and includes a plurality of memory cells MC, selection transistors STS and STD disposed along the columnar bodies CL.
  • the memory cells MC are provided at portions respectively where the columnar bodies CL intersect the word lines 20 .
  • a selection transistor STS is provided at a portion where the channel body 60 intersects the selection gate 30
  • a selection transistor STD is provided at a portion where one of the columnar bodies CL intersects the selection gate 40 .
  • the semiconductor memory device 1 further includes bit lines BL and a source line SL.
  • the bit lines BL and the source line SL extend, for example, in the Y direction above the stacked bodies 100 .
  • a bit line BL is electrically connected to the semiconductor layer 50 in the columnar body CL via the contact plugs Cb and V 1 .
  • the source line SL is electrically connected to the source layer 10 via the conductor body LI, for example.
  • the conductor body LI is provided with a plate shape extending in the X direction and the Z direction in the slit space SL, for example, and is electrically connected to the source line SL via the contact plug Cs.
  • FIG. 2 is a schematic cross-sectional view showing the semiconductor memory device 1 according to the first embodiment.
  • FIG. 2 shows a cross section of the stacked body 100 .
  • the stacked body 100 includes a columnar body CL and a channel body 60 .
  • the columnar body CL extends through the word lines 20 and the selection gate 40 in the Z direction.
  • the channel body 60 extends through the selection gate 30 in the Z direction.
  • the columnar body CL includes, for example, a semiconductor layer 50 , a memory layer 70 and an insulating core 80 .
  • the insulating core 80 is, for example, silicon oxide and extends in the Z direction in the columnar body CL.
  • the semiconductor layer 50 surrounds the insulating core 80 and extends in the Z direction along the insulating core 80 .
  • the semiconductor layer 50 is, for example, a polycrystalline silicon layer.
  • the memory layer 70 surrounds the semiconductor layer 50 and extends in the Z direction along the semiconductor layer 50 .
  • the memory layer 70 has a structure in which the insulating layer 71 , the charge storage layer 73 , and the insulating layer 75 are stacked in the lateral direction (i.e. the X direction).
  • the insulating layer 71 is, for example, a silicon oxide layer, and acts as a blocking insulator film.
  • the charge storage layer 73 is, for example, a silicon nitride layer.
  • the insulating layer 75 is, for example, a silicon oxide layer, and acts as a tunneling insulator film.
  • the insulating layer 75 may have a structure in which silicon oxynitride (SiON) and silicon oxide are sequentially stacked from the charge storage layer 73 side.
  • the channel body 60 is, for example, a semiconductor containing silicon and is provided between the source layer 10 and the columnar body CL.
  • the channel body 60 is electrically connected to the source layer 10 .
  • the semiconductor layer 50 has a bottom end 50 e positioned in the channel body 60 , and is electrically connected to the channel body 60 .
  • the semiconductor layer 50 has a layer thickness that gradually decreases in the Z direction.
  • the semiconductor layer 50 has a layer thickness W T in a direction from the insulating core 80 to the selection gate 40 between the selection gate 40 and the insulating core 80 .
  • the semiconductor layer 50 has a layer thickness W B in a direction from the insulating core 80 to the lowermost word line 20 b between the word line 20 b and the insulating core 80 .
  • the semiconductor layer 50 has a layer thickness W C in the direction from the insulating core 80 to an intermediate word line 20 c between the word line 20 c and the insulating core 80 .
  • the semiconductor layer 50 is provided so that the layer thickness W T is thinner than the layer thickness W C , and the layer thickness W C is thinner than the layer thickness W B .
  • W T is, for example, about 6 nanometers
  • W B is, for example, 12 to 16 nanometers.
  • the semiconductor layer 50 has a connecting portion 50 j between the channel body 60 and the insulating core 80 .
  • the connecting portion 50 j has a layer thickness W J in the direction from the insulating core 80 to the channel body 60 (i.e. the Z direction). Then, the semiconductor layer 50 is provided so that the layer thickness W J is thicker than the layer thickness W T , for example.
  • FIGS. 3A to 3L are schematic cross-sectional views showing a manufacturing process of the semiconductor memory device 1 according to the first embodiment.
  • a stacked body 110 is formed on a source layer 10 , and a memory hole MH is formed from the top surface thereof with a depth capable of reaching the source layer 10 .
  • the stacked body 110 includes an insulating layer 13 , interlayer insulating layers 15 , and sacrificial layers 17 stacked on the front surface 10 a of the source layer 10 .
  • the interlayer insulating layers 15 and the sacrificial layers 17 are alternately stacked on the insulating layer 13 .
  • a bottom surface of the memory hole MH is positioned at a level below the front surface 10 a of the source layer 10 .
  • the insulating layer 13 and the interlayer insulating layers 15 are silicon oxide layers formed, for example, using PCVD (Plasma enhanced Chemical Vapor Deposition).
  • the sacrificial layers 17 are, for example, silicon nitride layers formed using PCVD.
  • a channel body 60 is formed at a bottom portion of the memory hole MH.
  • the channel body 60 is, for example, a semiconductor containing silicon which is epitaxially grown on the source layer 10 .
  • the channel body 60 is formed such that a top surface 60 f thereof is positioned at a level between the lowermost layer 17 B of the sacrificial layers 17 and the sacrificial layer 17 C adjacent thereto.
  • a memory layer 70 is formed so as to cover an inner surface of the memory hole MH and the top surface 60 f of the channel body 60 .
  • the memory layer 70 has a stacked structure including an insulating layer 71 , a charge storage layer 73 and an insulating layer 75 (see FIG. 2 ), which are sequentially stacked, for example, using ALD (Atomic Layer Deposition).
  • ALD Atomic Layer Deposition
  • a semiconductor layer 50 a is formed so as to cover the inner surface of the memory hole MH.
  • the semiconductor layer 50 a is, for example, an amorphous silicon layer formed using CVD.
  • the semiconductor layer 50 a is formed on the memory layer 70 .
  • a part of the semiconductor layer 50 a and a part of the memory layer 70 formed on the top surface 60 f of the channel body 60 are selectively removed.
  • the semiconductor layer 50 a and the memory layer 70 are selectively etched while leaving parts formed on the inner wall of the memory hole MH. At this time, the semiconductor layer 50 a protects the memory layer 70 formed on the inner wall of the memory hole MH.
  • anisotropic RIE Reactive Ion Etching
  • a semiconductor layer 50 b is formed to cover the inner surface of the memory hole MH.
  • the semiconductor layer 50 b is, for example, an amorphous silicon layer formed using CVD, and covers the semiconductor layer 50 a and the top surface 60 f of the channel body 60 .
  • the semiconductor layers 50 a and 50 b formed on the inner surface of the memory hole MH are thermally treated to form the semiconductor layer 50 .
  • the semiconductor layer 50 is, for example, a polycrystalline silicon layer obtained by crystallizing the amorphous silicon layers.
  • a part of the semiconductor layer 50 is oxidized to form an insulating layer 23 .
  • the insulating layer 23 is formed, for example, using an oxidation method, ISSG (In-situ Steam Generation).
  • ISSG In-situ Steam Generation
  • the insulating layer 23 is formed to be thicker on an opening side of the memory hole MH than a thickness on the bottom of the memory hole MH. That is, the oxidation of the semiconductor layer 50 is performed under the conditions that suppress an oxidation in a part covering the top surface 60 f of the channel body 60 , and facilitate an oxidation in a part covering the inner wall of the memory hole MH.
  • the insulating layer 23 is removed, for example, by wet etching.
  • the semiconductor layer 50 is formed so that the layer thickness thereof (i.e. the thickness in the X direction) gradually decreases in a direction from the bottom surface to the opening in the memory hole MH. Then, the layer thickness of the part, which is formed on the channel body 60 at the bottom surface of the memory hole MH, is preferably maintained at the initially formed thickness.
  • an insulating core 80 is formed so as to fill the inside of the memory hole MH to complete the columnar body CL.
  • the insulating core 80 is formed, for example, by depositing silicon oxide using CVD to fill the inside of the memory hole MH.
  • the insulating core 80 may be formed without removing the insulating layer 23 shown in FIG. 3G .
  • the sacrifice layers 17 are selectively removed.
  • the sacrificial layers 17 can be etched, for example, by supplying hot phosphoric acid through the slit spaces ST (see FIG. 1 ).
  • the lateral surface of the columnar body CL and the lateral surface of the channel body 60 are exposed in the spaces 17 s after the removal of the sacrifice layers 17 .
  • an insulating layer 25 is formed by thermally oxidizing the side surface of the channel body 60 exposed in the space 17 s .
  • the insulating layer 25 acts as a gate insulating layer in the source side selection transistor STS.
  • word lines 20 , selection gates 30 and 40 are formed in the spaces 17 s to complete the memory cell array MCA.
  • the word lines 20 , selection gates 30 and 40 are formed by depositing a metal layer, for example, using CVD.
  • the source gases of CVD are supplied, for example, through the slit spaces ST (see FIG. 1 ).
  • the semiconductor layer 50 which act as the channel body of the memory cell MC, is formed to be thicker than a predetermined thickness, and then, thinned by thermal oxidization.
  • a polycrystalline silicon layer is formed, for example, by crystallizing an amorphous silicon layer using thermal treatment, a size of crystal grains in the polycrystalline silicon layer may be enlarged as the layer thickness of the amorphous silicon layer is increased.
  • connection portion 50 j formed on the channel body 60 has a layer thickness obtained by crystallizing the semiconductor layer 50 b , and is formed to be thinner than a portion in which the semiconductor layer 50 a and the semiconductor layer 50 b stacked on the inner wall are crystallized.
  • the connection portion 50 j becomes thinner, and a connection failure is caused between the semiconductor layer 50 and the channel body 60 , when the layer thickness of the semiconductor layer 50 is wholly reduced.
  • the semiconductor layer 50 formed on the inner wall of the memory hole MH is thinned by thermal oxidization of the semiconductor layer 50 under the conditions where the oxidization is facilitated in the portion formed on the inner wall of the memory hole MH, and is suppressed in the connection portion 50 j .
  • the semiconductor layer 50 is formed so that the layer thickness thereof gradually decreases in the direction from the bottom surface to the opening of the memory hole MH.
  • FIG. 4 is a schematic cross-sectional view showing a semiconductor memory device 2 according to a variation of the first embodiment.
  • the channel body 60 is not provided, and the columnar body CL is directly connected to the source layer 10 .
  • the columnar body CL extends in the Z direction through a selection gate 30 , word lines 20 , and a selection gate 40 .
  • the bottom end of the columnar body CL is connected to the source layer 10 .
  • a bottom end 50 e of the semiconductor layer 50 is positioned at a level below the front surface 10 a of the source layer 10 .
  • the semiconductor layer is electrically connected to the source layer 10 via a connection portion 50 j.
  • a part of the semiconductor layer 50 formed on an inner wall of the memory hole MH is thinned, and the layer thickness (the thickness in the X direction) thereof becomes gradually thinner in the direction from the source layer 10 toward the select gate 40 (i.e. in the Z direction).
  • the layer thickness W T between the selection gate 40 and the insulating core 80 , the layer thickness W B between the selection gate 30 and the insulating core 80 , and the layer thickness W C between the word line 20 and the insulating core 80 positioned in the middle has a relationship of W T ⁇ W C ⁇ W B .
  • the layer thickness W 3 of the connecting portion 50 j is kept at a thickness that makes it possible to prevent connection failure between the source layer 10 and the semiconductor layer 50 .
  • FIG. 5 is a schematic cross-sectional view showing a semiconductor memory device 3 according to a second embodiment.
  • the semiconductor memory device 3 includes a channel body 60 between the source layer 10 and the columnar body CL.
  • the columnar body CL extends in the Z direction through the word line 20 and the selection gate 40 .
  • the channel body 60 is provided so as to extend through the selection gate 30 .
  • the columnar body CL includes an insulating core 80 having a first portion 80 a and a second portion 80 b .
  • the second portion 80 b is located between the channel body 60 and the first portion 80 a .
  • a bottom surface of the first portion 80 a has a width Wa in the X direction and the top surface of the second portion 80 b has a width Wb in the X direction.
  • the first portion 80 a is provided so that Wa is wider than Wb.
  • the columnar body CL further includes a semiconductor layer 50 and a memory layer 70 .
  • the memory layer 70 has a structure in which an insulating layer 71 , a charge storage layer 73 , and an insulating layer 75 are stacked, and the insulating layer 75 is provided between the semiconductor layer 50 and the charge storage layer 73 .
  • the semiconductor layer 50 has a layer thickness W 1 in the X direction between the word line 20 and the insulating core 80 and between the selection gate 40 and the insulating core 80 , and has a layer thickness W 2 in the X direction between the insulating layer 75 and the second portion 80 b of the insulating core 80 .
  • the semiconductor layer 50 is provided so that W 1 is thinner than W 2 .
  • the connection portion 50 j of the semiconductor layer 50 has a layer thickness W J in a direction from the second portion 80 b toward the channel body 60 (i.e. Z direction), and is provided, for example, so that W 1 is thinner than W 2 .
  • FIGS. 6A to 6C are schematic cross-sectional views showing a manufacturing process of the semiconductor memory device 3 according to the second embodiment.
  • FIG. 6A shows a step following FIG. 3F
  • the steps after FIG. 3I are carried out following a step shown in FIG. 6C .
  • an insulating body 83 is embedded in the bottom of the memory hole MH after the formation of the semiconductor layer 50 .
  • the insulator 83 can be formed, for example, by etching back the silicon nitride layer deposited using CVD so as to fill the inside of the memory hole MH.
  • the insulating body 83 is not limited to silicon nitride, but may be silicon oxide, for example.
  • a part of the semiconductor layer 50 is thermally oxidized to form an insulating layer 27 on the inner surface of the memory hole MH.
  • the insulating body 83 has a thickness capable of being oxidized such that a bottom part thereof remains. Thus, it is possible to prevent the connection portion 50 j of the semiconductor layer 50 from the oxidation.
  • the insulating layer 27 is removed, for example, using wet etching.
  • the semiconductor layer 50 formed on the inner wall of the memory hole MH is thinned, and the connection portion 50 j can maintain the layer thickness thereof.
  • the inside of the memory hole MH is filled with an insulating body to form an insulating core 80 .
  • the insulator 83 shown in FIG. 6C becomes the second portion 80 b of the insulating core 80 .
  • the insulating body is removed together with the insulating layer 27 .
  • the insulating layer that is newly embedded in the memory hole MH forms the first portion 80 a and the second portion 80 b .
  • the insulating core 80 may be formed by embedding an insulating body in the memory hole MH without removing the insulating layer 27 .
  • FIG. 7 is a schematic cross-sectional view showing a semiconductor memory device 4 according to a variation of the second embodiment.
  • the channel body 60 is not provided, and the columnar body CL is directly connected to the source layer 10 .
  • the columnar body CL extends in the Z direction through the selection gate 30 , the word line 20 , and the selection gate 40 .
  • the columnar body CL includes an insulating core 80 having a first portion 80 a and a second portion 80 b .
  • the first portion 80 a is provided so as to extend in the Z direction through the word line 20 and the select gate 40 .
  • the second portion 80 b is provided so as to extend through the selection gate 30 , for example.
  • the semiconductor layer 50 has a layer thickness W 1 in the X direction between the word line 20 and the first portion 80 a and between the selection gate 40 and the first portion 80 a , and has a layer thickness W 2 in the X direction between the insulating layer 75 and the second portion 80 b . Then, the semiconductor layer 50 is provided so that W 1 is thinner than W 2 .
  • the connecting portion 50 j of the semiconductor layer 50 has a layer thickness W J in the Z direction, and is provided so that W 1 is thinner than W J , for example.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A semiconductor memory device includes a conductive layer; electrode layers stacked on the conductive layer; an insulating body extending through the electrode layers; and a semiconductor layer positioned between the insulating body and the electrode layers. The plurality of electrode layers include a first electrode layer, a second electrode layer provided between the conductive layer and the first electrode layer, and a third electrode layer provided between the conductive layer and the second electrode layer, and the semiconductor layer has a first layer thickness between the insulating body and the first electrode layer, a second layer thickness between the insulating body and the second electrode layer and a third layer thickness between the insulating body and the third electrode layer. The first layer thickness is thinner than the second layer thickness, and the second layer thickness is thinner than the third layer thickness.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from U.S. Provisional Patent Application 62/395,710 filed on Sep. 16, 2016; the entire contents of which are incorporated herein by reference.
FIELD
Embodiments are generally related to a semiconductor memory device and a method for manufacturing the same.
BACKGROUND
A semiconductor memory device is under developing, which includes three-dimensionally disposed memory cells. For example, a NAND type flash memory device has a structure in which a semiconductor channel body extends through a plurality of word lines stacked on a source layer, and the memory cells are arranged in portions respectively where the channel body extends through the word lines. In such a structure, when the number of word lines stacked is increased in order to advance the integration degree of the memory cells, the channel body becomes longer, and the on-current is reduced which flows therethrough.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view schematically showing a semiconductor memory device according to a first embodiment;
FIG. 2 is a schematic cross-sectional view showing the semiconductor memory device according to the first embodiment;
FIGS. 3A to 3L are schematic cross-sectional views showing a manufacturing process of the semiconductor memory device according to the first embodiment;
FIG. 4 is a schematic cross-sectional view showing a semiconductor memory device according to a variation of the first embodiment;
FIG. 5 is a schematic cross-sectional view showing a semiconductor memory device according to a second embodiment;
FIGS. 6A to 6C are schematic cross-sectional views showing a manufacturing process of the semiconductor memory device according to the second embodiment; and
FIG. 7 is a schematic cross-sectional view showing a semiconductor memory device according to a variation of the second embodiment.
 DETAILED DESCRIPTION
According to one embodiment, a semiconductor memory device includes a conductive layer; a plurality of electrode layers stacked on the conductive layer; an insulating body extending through the plurality of electrode layers; and a semiconductor layer positioned between the insulating body and the plurality of electrode layers, the semiconductor layer extending along the insulating body. The plurality of electrode layers include a first electrode layer, a second electrode layer provided between the conductive layer and the first electrode layer, and a third electrode layer provided between the conductive layer and the second electrode layer, and the semiconductor layer has a first layer thickness in a direction from the insulating body to the first electrode layer between the insulating body and the first electrode layer, a second layer thickness in a direction from the insulating body to the second electrode layer between the insulating body and the second electrode layer and a third layer thickness in a direction from the insulating body to the third electrode layer between the insulating body and the third electrode layer. The first layer thickness is thinner than the second layer thickness, and the second layer thickness is thinner than the third layer thickness.
Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.
There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.
First Embodiment
FIG. 1 is a perspective view schematically showing a memory cell array MCA of a semiconductor memory device 1 according to a first embodiment. The semiconductor memory device 1 is, for example, a NAND type memory device and includes three-dimensionally disposed memory cells MC.
As shown in FIG. 1, the semiconductor memory device 1 includes, for example, a source layer 10 provided on a silicon substrate (not shown), and a stacked body 100. A plurality of stacked bodies 100 are arranged, for example, in the Y direction on the source layer 10. The adjacent stacked bodies 100 in the Y direction are separated by a slit space SL. The stacked body 100 includes a plurality of electrode layers (hereinafter, word lines 20, selection gates 30 and 40) stacked in the Z direction.
The selection gate 30 is provided on the source layer 10 with an insulating layer 13 interposed. The word lines 20 are stacked on the select gate 30. The interlayer insulating layers 15 are provided between the selection gate 30 and the lowermost word line 20 and between the adjacent word lines 20 in the Z direction. The selection gate 40 is provided on the uppermost word line 20 via another interlayer insulating layer 15.
The source layer 10 is, for example, a P-type well provided in a silicon substrate. The word lines 20, the select gates 30 and 40 are, for example, metal layers or low resistance polycrystalline silicon layers. The insulating layers 13 and 15 are, for example, silicon oxide layers.
The stacked body 100 includes, for example, a plurality of columnar bodies CL extending through the word lines 20 and the selection gate 40 and extending in the Z direction. The columnar bodies CL each include a semiconductor layer 50 (see FIG. 2). In addition, the stacked body 100 may include, for example, a semiconductor channel body (hereinafter referred to as a channel body 60) located between each of the columnar bodies CL and the source layer 10, and extending through the selection gate 30 in the Z direction.
The memory cell array MCA includes a plurality of stacked bodies 100 and includes a plurality of memory cells MC, selection transistors STS and STD disposed along the columnar bodies CL. The memory cells MC are provided at portions respectively where the columnar bodies CL intersect the word lines 20. A selection transistor STS is provided at a portion where the channel body 60 intersects the selection gate 30, and a selection transistor STD is provided at a portion where one of the columnar bodies CL intersects the selection gate 40.
The semiconductor memory device 1 further includes bit lines BL and a source line SL. The bit lines BL and the source line SL extend, for example, in the Y direction above the stacked bodies 100. A bit line BL is electrically connected to the semiconductor layer 50 in the columnar body CL via the contact plugs Cb and V1. The source line SL is electrically connected to the source layer 10 via the conductor body LI, for example. The conductor body LI is provided with a plate shape extending in the X direction and the Z direction in the slit space SL, for example, and is electrically connected to the source line SL via the contact plug Cs.
FIG. 2 is a schematic cross-sectional view showing the semiconductor memory device 1 according to the first embodiment. FIG. 2 shows a cross section of the stacked body 100.
As shown in FIG. 2, the stacked body 100 includes a columnar body CL and a channel body 60. The columnar body CL extends through the word lines 20 and the selection gate 40 in the Z direction. The channel body 60 extends through the selection gate 30 in the Z direction.
The columnar body CL includes, for example, a semiconductor layer 50, a memory layer 70 and an insulating core 80. The insulating core 80 is, for example, silicon oxide and extends in the Z direction in the columnar body CL. The semiconductor layer 50 surrounds the insulating core 80 and extends in the Z direction along the insulating core 80. The semiconductor layer 50 is, for example, a polycrystalline silicon layer. The memory layer 70 surrounds the semiconductor layer 50 and extends in the Z direction along the semiconductor layer 50.
The memory layer 70 has a structure in which the insulating layer 71, the charge storage layer 73, and the insulating layer 75 are stacked in the lateral direction (i.e. the X direction). The insulating layer 71 is, for example, a silicon oxide layer, and acts as a blocking insulator film. The charge storage layer 73 is, for example, a silicon nitride layer. The insulating layer 75 is, for example, a silicon oxide layer, and acts as a tunneling insulator film. In addition, the insulating layer 75 may have a structure in which silicon oxynitride (SiON) and silicon oxide are sequentially stacked from the charge storage layer 73 side.
The channel body 60 is, for example, a semiconductor containing silicon and is provided between the source layer 10 and the columnar body CL. The channel body 60 is electrically connected to the source layer 10. Further, the semiconductor layer 50 has a bottom end 50 e positioned in the channel body 60, and is electrically connected to the channel body 60.
In the embodiment, the semiconductor layer 50 has a layer thickness that gradually decreases in the Z direction. For example, the semiconductor layer 50 has a layer thickness WT in a direction from the insulating core 80 to the selection gate 40 between the selection gate 40 and the insulating core 80. The semiconductor layer 50 has a layer thickness WB in a direction from the insulating core 80 to the lowermost word line 20 b between the word line 20 b and the insulating core 80. Moreover, the semiconductor layer 50 has a layer thickness WC in the direction from the insulating core 80 to an intermediate word line 20 c between the word line 20 c and the insulating core 80. The semiconductor layer 50 is provided so that the layer thickness WT is thinner than the layer thickness WC, and the layer thickness WC is thinner than the layer thickness WB. WT is, for example, about 6 nanometers, and WB is, for example, 12 to 16 nanometers.
Furthermore, the semiconductor layer 50 has a connecting portion 50 j between the channel body 60 and the insulating core 80. The connecting portion 50 j has a layer thickness WJ in the direction from the insulating core 80 to the channel body 60 (i.e. the Z direction). Then, the semiconductor layer 50 is provided so that the layer thickness WJ is thicker than the layer thickness WT, for example.
A method of manufacturing the semiconductor memory device 1 will be described below with reference to FIGS. 3A to 3L. FIGS. 3A to 3L are schematic cross-sectional views showing a manufacturing process of the semiconductor memory device 1 according to the first embodiment.
As shown in FIG. 3A, a stacked body 110 is formed on a source layer 10, and a memory hole MH is formed from the top surface thereof with a depth capable of reaching the source layer 10. The stacked body 110 includes an insulating layer 13, interlayer insulating layers 15, and sacrificial layers 17 stacked on the front surface 10 a of the source layer 10. The interlayer insulating layers 15 and the sacrificial layers 17 are alternately stacked on the insulating layer 13. A bottom surface of the memory hole MH is positioned at a level below the front surface 10 a of the source layer 10.
The insulating layer 13 and the interlayer insulating layers 15 are silicon oxide layers formed, for example, using PCVD (Plasma enhanced Chemical Vapor Deposition). The sacrificial layers 17 are, for example, silicon nitride layers formed using PCVD.
As shown in FIG. 3B, a channel body 60 is formed at a bottom portion of the memory hole MH. The channel body 60 is, for example, a semiconductor containing silicon which is epitaxially grown on the source layer 10. For example, the channel body 60 is formed such that a top surface 60 f thereof is positioned at a level between the lowermost layer 17B of the sacrificial layers 17 and the sacrificial layer 17C adjacent thereto.
As shown in FIG. 3C, a memory layer 70 is formed so as to cover an inner surface of the memory hole MH and the top surface 60 f of the channel body 60. The memory layer 70 has a stacked structure including an insulating layer 71, a charge storage layer 73 and an insulating layer 75 (see FIG. 2), which are sequentially stacked, for example, using ALD (Atomic Layer Deposition).
Further, a semiconductor layer 50 a is formed so as to cover the inner surface of the memory hole MH. The semiconductor layer 50 a is, for example, an amorphous silicon layer formed using CVD. The semiconductor layer 50 a is formed on the memory layer 70.
As shown in FIG. 3D, a part of the semiconductor layer 50 a and a part of the memory layer 70 formed on the top surface 60 f of the channel body 60 are selectively removed.
For example, by using anisotropic RIE (Reactive Ion Etching), the semiconductor layer 50 a and the memory layer 70 are selectively etched while leaving parts formed on the inner wall of the memory hole MH. At this time, the semiconductor layer 50 a protects the memory layer 70 formed on the inner wall of the memory hole MH.
As shown in FIG. 3E, a semiconductor layer 50 b is formed to cover the inner surface of the memory hole MH. The semiconductor layer 50 b is, for example, an amorphous silicon layer formed using CVD, and covers the semiconductor layer 50 a and the top surface 60 f of the channel body 60.
As shown in FIG. 3F, the semiconductor layers 50 a and 50 b formed on the inner surface of the memory hole MH are thermally treated to form the semiconductor layer 50. The semiconductor layer 50 is, for example, a polycrystalline silicon layer obtained by crystallizing the amorphous silicon layers.
As shown in FIG. 3G, a part of the semiconductor layer 50 is oxidized to form an insulating layer 23. The insulating layer 23 is formed, for example, using an oxidation method, ISSG (In-situ Steam Generation). For example, by using the conditions under which an oxidation rate is limited by a supplied amount of oxidizing agent, the insulating layer 23 is formed to be thicker on an opening side of the memory hole MH than a thickness on the bottom of the memory hole MH. That is, the oxidation of the semiconductor layer 50 is performed under the conditions that suppress an oxidation in a part covering the top surface 60 f of the channel body 60, and facilitate an oxidation in a part covering the inner wall of the memory hole MH.
As shown in FIG. 3H, the insulating layer 23 is removed, for example, by wet etching. The semiconductor layer 50 is formed so that the layer thickness thereof (i.e. the thickness in the X direction) gradually decreases in a direction from the bottom surface to the opening in the memory hole MH. Then, the layer thickness of the part, which is formed on the channel body 60 at the bottom surface of the memory hole MH, is preferably maintained at the initially formed thickness.
As shown in FIG. 3I, an insulating core 80 is formed so as to fill the inside of the memory hole MH to complete the columnar body CL. The insulating core 80 is formed, for example, by depositing silicon oxide using CVD to fill the inside of the memory hole MH. Alternatively, the insulating core 80 may be formed without removing the insulating layer 23 shown in FIG. 3G.
As shown in FIG. 3J, the sacrifice layers 17 are selectively removed. The sacrificial layers 17 can be etched, for example, by supplying hot phosphoric acid through the slit spaces ST (see FIG. 1). The lateral surface of the columnar body CL and the lateral surface of the channel body 60 are exposed in the spaces 17 s after the removal of the sacrifice layers 17.
As shown in FIG. 3K, an insulating layer 25 is formed by thermally oxidizing the side surface of the channel body 60 exposed in the space 17 s. The insulating layer 25 acts as a gate insulating layer in the source side selection transistor STS.
As shown in FIG. 3L, word lines 20, selection gates 30 and 40 are formed in the spaces 17 s to complete the memory cell array MCA. The word lines 20, selection gates 30 and 40 are formed by depositing a metal layer, for example, using CVD. The source gases of CVD are supplied, for example, through the slit spaces ST (see FIG. 1).
In the embodiment, the semiconductor layer 50, which act as the channel body of the memory cell MC, is formed to be thicker than a predetermined thickness, and then, thinned by thermal oxidization. When a polycrystalline silicon layer is formed, for example, by crystallizing an amorphous silicon layer using thermal treatment, a size of crystal grains in the polycrystalline silicon layer may be enlarged as the layer thickness of the amorphous silicon layer is increased. Thereby, it is possible to increase the carrier mobility in the polycrystalline silicon and to increase the ON-current of memory cell MC. Further, it is also possible to improve the S-factor of memory cell transistor and to suppress the variation of threshold voltage.
However, as shown in FIG. 3E, the connection portion 50 j formed on the channel body 60 has a layer thickness obtained by crystallizing the semiconductor layer 50 b, and is formed to be thinner than a portion in which the semiconductor layer 50 a and the semiconductor layer 50 b stacked on the inner wall are crystallized. Thus, there may be a case where the connection portion 50 j (see FIG. 2) becomes thinner, and a connection failure is caused between the semiconductor layer 50 and the channel body 60, when the layer thickness of the semiconductor layer 50 is wholly reduced. In the embodiment, while maintaining the layer thickness of the connection portion 50 j, the semiconductor layer 50 formed on the inner wall of the memory hole MH is thinned by thermal oxidization of the semiconductor layer 50 under the conditions where the oxidization is facilitated in the portion formed on the inner wall of the memory hole MH, and is suppressed in the connection portion 50 j. As a result, the semiconductor layer 50 is formed so that the layer thickness thereof gradually decreases in the direction from the bottom surface to the opening of the memory hole MH.
It should be noted that it is possible to increase the carrier mobility, for example, in the thinning process of the semiconductor layer 50 using the thermal oxidization comparing with an etching method such as RIE. This may be because of electrical inactivation of defects existing at the grain boundary of polycrystalline silicon due to the termination thereof with the oxidizing agent.
FIG. 4 is a schematic cross-sectional view showing a semiconductor memory device 2 according to a variation of the first embodiment. In the semiconductor memory device 2, the channel body 60 is not provided, and the columnar body CL is directly connected to the source layer 10.
As shown in FIG. 4, the columnar body CL extends in the Z direction through a selection gate 30, word lines 20, and a selection gate 40. The bottom end of the columnar body CL is connected to the source layer 10. A bottom end 50 e of the semiconductor layer 50 is positioned at a level below the front surface 10 a of the source layer 10. The semiconductor layer is electrically connected to the source layer 10 via a connection portion 50 j.
Also in this example, a part of the semiconductor layer 50 formed on an inner wall of the memory hole MH is thinned, and the layer thickness (the thickness in the X direction) thereof becomes gradually thinner in the direction from the source layer 10 toward the select gate 40 (i.e. in the Z direction). The layer thickness WT between the selection gate 40 and the insulating core 80, the layer thickness WB between the selection gate 30 and the insulating core 80, and the layer thickness WC between the word line 20 and the insulating core 80 positioned in the middle has a relationship of WT<WC<WB. Further, the layer thickness W3 of the connecting portion 50 j is kept at a thickness that makes it possible to prevent connection failure between the source layer 10 and the semiconductor layer 50.
Second Embodiment
FIG. 5 is a schematic cross-sectional view showing a semiconductor memory device 3 according to a second embodiment. The semiconductor memory device 3 includes a channel body 60 between the source layer 10 and the columnar body CL. The columnar body CL extends in the Z direction through the word line 20 and the selection gate 40. The channel body 60 is provided so as to extend through the selection gate 30.
As shown in FIG. 5, the columnar body CL includes an insulating core 80 having a first portion 80 a and a second portion 80 b. The second portion 80 b is located between the channel body 60 and the first portion 80 a. A bottom surface of the first portion 80 a has a width Wa in the X direction and the top surface of the second portion 80 b has a width Wb in the X direction. The first portion 80 a is provided so that Wa is wider than Wb.
The columnar body CL further includes a semiconductor layer 50 and a memory layer 70. The memory layer 70 has a structure in which an insulating layer 71, a charge storage layer 73, and an insulating layer 75 are stacked, and the insulating layer 75 is provided between the semiconductor layer 50 and the charge storage layer 73.
In the embodiment, the semiconductor layer 50 has a layer thickness W1 in the X direction between the word line 20 and the insulating core 80 and between the selection gate 40 and the insulating core 80, and has a layer thickness W2 in the X direction between the insulating layer 75 and the second portion 80 b of the insulating core 80. The semiconductor layer 50 is provided so that W1 is thinner than W2. The connection portion 50 j of the semiconductor layer 50 has a layer thickness WJ in a direction from the second portion 80 b toward the channel body 60 (i.e. Z direction), and is provided, for example, so that W1 is thinner than W2.
FIGS. 6A to 6C are schematic cross-sectional views showing a manufacturing process of the semiconductor memory device 3 according to the second embodiment. For example, FIG. 6A shows a step following FIG. 3F, and the steps after FIG. 3I are carried out following a step shown in FIG. 6C.
As shown in FIG. 6A, an insulating body 83 is embedded in the bottom of the memory hole MH after the formation of the semiconductor layer 50. The insulator 83 can be formed, for example, by etching back the silicon nitride layer deposited using CVD so as to fill the inside of the memory hole MH. The insulating body 83 is not limited to silicon nitride, but may be silicon oxide, for example.
As shown in FIG. 6B, a part of the semiconductor layer 50 is thermally oxidized to form an insulating layer 27 on the inner surface of the memory hole MH. The insulating body 83 has a thickness capable of being oxidized such that a bottom part thereof remains. Thus, it is possible to prevent the connection portion 50 j of the semiconductor layer 50 from the oxidation.
As shown in FIG. 6C, the insulating layer 27 is removed, for example, using wet etching. As a result, the semiconductor layer 50 formed on the inner wall of the memory hole MH is thinned, and the connection portion 50 j can maintain the layer thickness thereof.
Subsequently, as shown in FIG. 3I, the inside of the memory hole MH is filled with an insulating body to form an insulating core 80. The insulator 83 shown in FIG. 6C becomes the second portion 80 b of the insulating core 80. For example, when silicon oxide is used for the insulating body 83, the insulating body is removed together with the insulating layer 27. However, the insulating layer that is newly embedded in the memory hole MH forms the first portion 80 a and the second portion 80 b. Alternatively, the insulating core 80 may be formed by embedding an insulating body in the memory hole MH without removing the insulating layer 27.
FIG. 7 is a schematic cross-sectional view showing a semiconductor memory device 4 according to a variation of the second embodiment. In the semiconductor memory device 4, the channel body 60 is not provided, and the columnar body CL is directly connected to the source layer 10.
As shown in FIG. 7, the columnar body CL extends in the Z direction through the selection gate 30, the word line 20, and the selection gate 40. The columnar body CL includes an insulating core 80 having a first portion 80 a and a second portion 80 b. For example, the first portion 80 a is provided so as to extend in the Z direction through the word line 20 and the select gate 40. The second portion 80 b is provided so as to extend through the selection gate 30, for example.
Also in this example, the semiconductor layer 50 has a layer thickness W1 in the X direction between the word line 20 and the first portion 80 a and between the selection gate 40 and the first portion 80 a, and has a layer thickness W2 in the X direction between the insulating layer 75 and the second portion 80 b. Then, the semiconductor layer 50 is provided so that W1 is thinner than W2. The connecting portion 50 j of the semiconductor layer 50 has a layer thickness WJ in the Z direction, and is provided so that W1 is thinner than WJ, for example.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.

Claims (15)

What is claimed is:
1. A semiconductor memory device comprising:
a conductive layer;
a plurality of electrode layers stacked on the conductive layer;
an insulating body extending through the plurality of electrode layers; and
a semiconductor layer positioned between the insulating body and the plurality of electrode layers, the semiconductor layer extending along the insulating body, the plurality of electrode layers including a first electrode layer, a second electrode layer provided between the conductive layer and the first electrode layer, and a third electrode layer provided between the conductive layer and the second electrode layer, and
the semiconductor layer having a first layer thickness in a direction from the insulating body to the first electrode layer between the insulating body and the first electrode layer, a second layer thickness in a direction from the insulating body to the second electrode layer between the insulating body and the second electrode layer and a third layer thickness in a direction from the insulating body to the third electrode layer between the insulating body and the third electrode layer,
the first layer thickness being thinner than the second layer thickness, and
the second layer thickness being thinner than the third layer thickness.
2. The semiconductor memory device according to claim 1, wherein the semiconductor layer is a polycrystalline silicon layer.
3. The semiconductor memory device according to claim 1, wherein the third electrode layer is a lowermost layer of the plurality of electrode layers.
4. The semiconductor memory device according to claim 1, wherein the first electrode layer is an uppermost layer of the plurality of electrode layers.
5. The semiconductor memory device according to claim 4, further comprising:
a semiconductor channel body provided between the conductive layer and the insulating body, and extending through a fourth electrode layer positioned between the conductive layer and the third electrode layer,
the semiconductor layer including a connecting portion positioned between the insulating body and the semiconductor channel body, and
a layer thickness, in a direction from the insulating body to the semiconductor channel body, of the connecting portion is thicker than the first layer thickness.
6. The semiconductor memory device according to claim 4, wherein
the semiconductor layer includes a connecting portion positioned between the conductive layer and the insulating body, and
a layer thickness, in a direction from the insulating body to the conductive layer, of the connecting portion is thicker than the first layer thickness.
7. The semiconductor memory device according to claim 1, wherein the semiconductor layer has a layer thickness gradually decreasing in a direction from the third electrode layer to the first electrode layer.
8. The semiconductor memory device according to claim 1, further comprising:
memory cells including charge storage portions positioned between the semiconductor layer and the plurality of electrode layers.
9. The semiconductor memory device according to claim 1, wherein the conductive layer is a source layer provided on a substrate.
10. A semiconductor memory device comprising:
a conductive layer;
a plurality of electrode layers stacked on a front surface of the conductive layer;
an insulating body extending through the plurality of electrode layers;
a semiconductor layer positioned between the insulating body and the plurality of electrode layers, the semiconductor layer extending along the insulating body; and
an insulating layer positioned between the semiconductor layer and the plurality of electrode layers, the insulating layer extending along the semiconductor layer,
the insulating body including a first portion extending through the plurality of electrode layers and a second portion positioned between the conductive layer and the first portion, the second portion having a width along the front surface of the conductive layer narrower than a width of the first portion in a same direction, and
the semiconductor layer having a first layer thickness in a direction from the first portion to one of the plurality of electrode layers between the first portion and the one of the plurality of electrode layers, and a second layer thickness in a direction from the second portion to the insulating layer between the second portion and the insulating layer, the first layer thickness being thinner than the second layer thickness.
11. The semiconductor memory device according to claim 10, further comprising:
another electrode layer positioned between the conductive layer and the plurality of electrode layers; and
a semiconductor channel body provided between the conductive layer and the insulating body and extending through the another electrode layer,
the semiconductor layer including a connecting portion located between the insulating body and the semiconductor channel body, and
a layer thickness of the connecting portion in a direction from the insulating body to the semiconductor channel body is thicker than the first layer thickness.
12. The semiconductor memory device according to claim 10, wherein
the semiconductor layer includes a connection portion positioned between the conductive layer and the insulating body, and
a layer thickness of the connecting portion in a direction from the insulating body to the conductive layer is thicker than the first layer thickness.
13. The semiconductor memory device according to claim 10, further comprising:
another electrode layer positioned between the conductive layer and the plurality of electrode layers,
the second portion extending through the another electrode layer.
14. The semiconductor memory device according to claim 10, wherein the insulating body includes silicon oxide.
15. The semiconductor memory device according to claim 10, wherein the first portion includes silicon oxide, and the second portion includes silicon nitride.
US15/463,582 2016-09-16 2017-03-20 Semiconductor memory device and method for manufacturing same Expired - Fee Related US9960179B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/463,582 US9960179B2 (en) 2016-09-16 2017-03-20 Semiconductor memory device and method for manufacturing same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662395710P 2016-09-16 2016-09-16
US15/463,582 US9960179B2 (en) 2016-09-16 2017-03-20 Semiconductor memory device and method for manufacturing same

Publications (2)

Publication Number Publication Date
US20180083031A1 US20180083031A1 (en) 2018-03-22
US9960179B2 true US9960179B2 (en) 2018-05-01

Family

ID=61620581

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/463,582 Expired - Fee Related US9960179B2 (en) 2016-09-16 2017-03-20 Semiconductor memory device and method for manufacturing same

Country Status (1)

Country Link
US (1) US9960179B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11282853B2 (en) 2019-03-15 2022-03-22 Kioxia Corporation Semiconductor memory device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3503185B1 (en) * 2017-12-22 2022-03-30 IMEC vzw Method for manufacturing a 3d semiconductor memory device
JP2019220534A (en) * 2018-06-18 2019-12-26 キオクシア株式会社 Semiconductor storage device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732891B2 (en) 2008-06-03 2010-06-08 Kabushiki Kaisha Toshiba Semiconductor device
US7936004B2 (en) 2006-03-27 2011-05-03 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and manufacturing method thereof
US9634022B2 (en) * 2014-07-02 2017-04-25 SK Hynix Inc. Three dimensional semiconductor device
US9761601B2 (en) * 2015-01-30 2017-09-12 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7936004B2 (en) 2006-03-27 2011-05-03 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and manufacturing method thereof
US7732891B2 (en) 2008-06-03 2010-06-08 Kabushiki Kaisha Toshiba Semiconductor device
US9634022B2 (en) * 2014-07-02 2017-04-25 SK Hynix Inc. Three dimensional semiconductor device
US9761601B2 (en) * 2015-01-30 2017-09-12 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11282853B2 (en) 2019-03-15 2022-03-22 Kioxia Corporation Semiconductor memory device

Also Published As

Publication number Publication date
US20180083031A1 (en) 2018-03-22

Similar Documents

Publication Publication Date Title
US9166032B1 (en) Non-volatile memory device
US9748268B1 (en) Semiconductor memory device
US11024646B2 (en) Memory device
US9929178B1 (en) Semiconductor device and method for manufacturing the same
US9887273B2 (en) Semiconductor memory device
US10593696B2 (en) Semiconductor memory device and method for manufacturing same
US10483277B2 (en) Semiconductor memory device and method for manufacturing the same
KR101949375B1 (en) Method for fabricating nonvolatile memory device
US20170040340A1 (en) Semiconductor memory device and method for manufacturing the same
US20220115403A1 (en) Semiconductor memory device for suppressing variations of impurity concentrations
KR20130102893A (en) Nonvolatile memory device and method for fabricating the same
US9892930B1 (en) Semiconductor memory device and method for manufacturing same
US10269825B2 (en) Semiconductor device and method for manufacturing same
US9997536B2 (en) Semiconductor memory device
US9960179B2 (en) Semiconductor memory device and method for manufacturing same
US10840262B2 (en) Memory device and manufacturing methods thereof
US10332905B2 (en) Semiconductor memory device
US10115731B2 (en) Semiconductor memory device
US9842849B1 (en) Semiconductor memory device and method for manufacturing the same
US9953998B2 (en) Semiconductor memory device and method for manufacturing same
US20180076293A1 (en) Semiconductor memory device and method for manufacturing the same
TW202123437A (en) Semiconductor device and manufacturing method thereof
US20170243817A1 (en) Semiconductor memory device
US10109578B2 (en) Semiconductor memory device
US9831125B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YAMADA, KENTA;REEL/FRAME:042133/0141

Effective date: 20170410

AS Assignment

Owner name: TOSHIBA MEMORY CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KABUSHIKI KAISHA TOSHIBA;REEL/FRAME:043355/0058

Effective date: 20170713

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20220501