CN108461546B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN108461546B
CN108461546B CN201710700472.1A CN201710700472A CN108461546B CN 108461546 B CN108461546 B CN 108461546B CN 201710700472 A CN201710700472 A CN 201710700472A CN 108461546 B CN108461546 B CN 108461546B
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China
Prior art keywords
region
insulating film
semiconductor layer
electrode
thickness
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CN201710700472.1A
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English (en)
Chinese (zh)
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CN108461546A (zh
Inventor
新田峻介
松冈长
加藤俊亮
新井雅俊
小泽慎也
田中文悟
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal
    • H10W20/4446—Refractory-metal alloys

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  • Electrodes Of Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
CN201710700472.1A 2017-02-21 2017-08-16 半导体装置 Active CN108461546B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017030339A JP6739372B2 (ja) 2017-02-21 2017-02-21 半導体装置
JP2017-030339 2017-02-21

Publications (2)

Publication Number Publication Date
CN108461546A CN108461546A (zh) 2018-08-28
CN108461546B true CN108461546B (zh) 2024-03-12

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CN201710700472.1A Active CN108461546B (zh) 2017-02-21 2017-08-16 半导体装置

Country Status (3)

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US (1) US11004931B2 (enExample)
JP (1) JP6739372B2 (enExample)
CN (1) CN108461546B (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019145646A (ja) * 2018-02-20 2019-08-29 株式会社東芝 半導体装置
JP6970632B2 (ja) * 2018-03-16 2021-11-24 株式会社東芝 半導体装置
JP7193371B2 (ja) * 2019-02-19 2022-12-20 株式会社東芝 半導体装置
JP7224979B2 (ja) 2019-03-15 2023-02-20 株式会社東芝 半導体装置
JP7252860B2 (ja) * 2019-08-20 2023-04-05 株式会社東芝 半導体装置
JP7248541B2 (ja) * 2019-08-23 2023-03-29 株式会社東芝 半導体装置
JP7392612B2 (ja) 2020-08-26 2023-12-06 株式会社デンソー 半導体装置
JP7610492B2 (ja) * 2021-09-08 2025-01-08 株式会社東芝 半導体装置
CN113990921B (zh) * 2021-10-18 2023-12-08 深圳市威兆半导体股份有限公司 半导体纵向器件及其生产方法
EP4270487A1 (en) * 2022-04-28 2023-11-01 Infineon Technologies Austria AG Power transistor device and method of fabricating a transistor device
JP7719758B2 (ja) * 2022-09-08 2025-08-06 株式会社東芝 半導体装置
CN122423319A (zh) * 2023-12-19 2026-07-17 三菱电机株式会社 半导体装置以及半导体装置的制造方法
WO2025154684A1 (ja) * 2024-01-19 2025-07-24 ローム株式会社 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190868A (ja) * 1986-02-18 1987-08-21 Matsushita Electronics Corp 半導体記憶装置
US9048214B2 (en) * 2012-08-21 2015-06-02 Semiconductor Components Industries, Llc Bidirectional field effect transistor and method
CN105990426A (zh) * 2014-09-30 2016-10-05 株式会社东芝 半导体装置及其制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5330301B2 (enExample) 1972-12-13 1978-08-25
JP2001358338A (ja) 2000-06-14 2001-12-26 Fuji Electric Co Ltd トレンチゲート型半導体装置
JP2006202931A (ja) 2005-01-20 2006-08-03 Renesas Technology Corp 半導体装置およびその製造方法
JP5315638B2 (ja) 2007-07-24 2013-10-16 サンケン電気株式会社 半導体装置
JP5395309B2 (ja) * 2011-03-23 2014-01-22 パナソニック株式会社 半導体装置およびその製造方法
JP2013026488A (ja) * 2011-07-22 2013-02-04 Semiconductor Components Industries Llc 絶縁ゲート型半導体装置およびその製造方法
US9029215B2 (en) * 2012-05-14 2015-05-12 Semiconductor Components Industries, Llc Method of making an insulated gate semiconductor device having a shield electrode structure
JP2014120656A (ja) * 2012-12-18 2014-06-30 Toshiba Corp 半導体装置
JP6062269B2 (ja) 2013-01-31 2017-01-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2016062981A (ja) * 2014-09-16 2016-04-25 株式会社東芝 半導体装置及びその製造方法
DE102014119466A1 (de) * 2014-12-22 2016-06-23 Infineon Technologies Ag Halbleitervorrichtung mit streifenförmigen trenchgatestrukturen und gateverbinderstruktur
KR102271239B1 (ko) * 2015-03-23 2021-06-29 삼성전자주식회사 반도체 장치 및 이의 제조 방법
JP6317727B2 (ja) * 2015-12-28 2018-04-25 株式会社東芝 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190868A (ja) * 1986-02-18 1987-08-21 Matsushita Electronics Corp 半導体記憶装置
US9048214B2 (en) * 2012-08-21 2015-06-02 Semiconductor Components Industries, Llc Bidirectional field effect transistor and method
CN105990426A (zh) * 2014-09-30 2016-10-05 株式会社东芝 半导体装置及其制造方法

Also Published As

Publication number Publication date
US11004931B2 (en) 2021-05-11
CN108461546A (zh) 2018-08-28
US20180240867A1 (en) 2018-08-23
JP2018137324A (ja) 2018-08-30
JP6739372B2 (ja) 2020-08-12

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