CN108461445A - 半导体设备及其制造方法 - Google Patents

半导体设备及其制造方法 Download PDF

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CN108461445A
CN108461445A CN201711209691.6A CN201711209691A CN108461445A CN 108461445 A CN108461445 A CN 108461445A CN 201711209691 A CN201711209691 A CN 201711209691A CN 108461445 A CN108461445 A CN 108461445A
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silicide
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silication
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季彦良
林振华
邱志钟
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MediaTek Inc
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Abstract

本发明提供了一种半导体设备及其制造方法，半导体设备包括：半导体基板；以及形成在所述半导体基板上的无源元件，上述无源元件包括：第一多晶硅层、硅化物阻止层和第一自对准硅化物层，所述硅化物阻止层形成于所述第一多晶硅层上并覆盖所述第一多晶硅层的上表面的至少一部分，所述第一自对准硅化物层覆盖所述硅化物阻止层的上表面。本发明通过在硅化物阻止层的上表面形成第一自对准硅化物层，从而可以减小无源组件产生的寄生电信号。因此可以减小无源组件产生的干扰。

Description

半导体设备及其制造方法
技术领域
本发明涉及一种半导体设备及其制造方法，特别是涉及一种具有自对准硅化物(salicide)层的半导体设备及其制造方法。
背景技术
常见的电子设备包括无源组件和电路。无源组件通常会产生寄生电信号(Parasitic electricity)，例如寄生电阻、寄生电容和/或寄生电感。然而，此类寄生电信号或者寄生元件会对电路产生干扰。因此，减少由无源组件产生的干扰十分重要。
发明内容
本发明提供一种半导体设备及其制造方法，以解决上述问题。
本发明提供了一种半导体设备，包括：半导体基板；以及形成在所述半导体基板上的无源元件，上述无源元件包括：第一多晶硅层、硅化物阻止层和第一自对准硅化物层，所述硅化物阻止层形成于所述第一多晶硅层上并覆盖所述第一多晶硅层的上表面的至少一部分，所述第一自对准硅化物层覆盖所述硅化物阻止层的上表面。
本发明提供了一种半导体设备制造方法，包括：提供半导体基板；在所述半导体基板的绝缘部上形成第一多晶硅层，在所述第一多晶硅层上形成硅化物阻止层，在所述硅化物阻止层上形成第二多晶硅层，所述硅化物阻止层覆盖所述第一多晶硅层的上表面的至少一部分；形成反应层，所述反应层覆盖所述第二多晶硅层；通过所述第二多晶硅层与所述反应层反应，形成第一自对准硅化物层。
本发明通过在半导体基板上的无源组件中形成覆盖第一多晶硅层的硅化物阻止层，且在硅化物阻止层的上表面形成第一自对准硅化物层，从而可以减小无源组件产生的寄生电信号。因此，本发明可以减小无源组件产生的干扰。
在结合附图阅读本发明的实施例的以下详细描述之后，本发明的各种目的、特征和优点将是显而易见的。然而，这里使用的附图仅以解释说明为目的，而不应被视为本发明的限制。
附图说明
在浏览了下文的具体实施方式和相应的附图后，本领域技术人员将更容易理解上述本发明的目的和优点。
图1A是本发明半导体设备一实施例的结构示意图。
图1B是图1A中半导体设备沿1B-1B’方向的剖视图。
图1C是图1A中半导体设备沿1C-1C’方向的剖视图。
图2A至图2F是图1B中的半导体设备的制造过程示意图。
具体实施方式
图1A根据本发明的实施例例示了半导体设备100的示意图，图1B是图1A中半导体设备100沿1B-1B’方向的剖视图，而图1C是图1A中半导体设备100沿1C-1C’方向的剖视图。
例如，半导体设备100可以是存储设备，比如金属氧化物半导体(metal-oxide-semiconductor，MOS)设备等。半导体设备100包括半导体基板110、第一绝缘部112、第二绝缘部114、至少一个MOS 120、无源组件130、第一触点140、控制器145、第二触点150、第三触点150’以及层结构160。
例如，半导体基板110可以是硅片(silicon wafer)。半导体基板110具有上表面110u。第一绝缘部112和第二绝缘部114嵌于半导体基板110中且在上表面110u露出。例如，在一实施例中，第一绝缘部112和第二绝缘部114是由SiOx或SiNx制成的浅槽隔离(shallowtrench isolation，STI)。
MOS 120形成在半导体基板110的上表面110u上。MOS 120包括栅极绝缘层121、侧壁层(spacer)122和多晶硅层(poly layer)123，其中，栅极绝缘层121将多晶硅层123与半导体基板110分离。栅极绝缘层121可以由例如氧化物(oxide)制成，或者栅极绝缘层121可以由SiNx制成。
如图1B所示，无源组件130形成在第一绝缘部112的上表面112u之上。无源组件130包括第一多晶硅层131、硅化物阻止(salicide block,SAB)层132和第一自对准硅化物层(salicide layer)133。SAB层132形成于位于上表面112u之上的第一多晶硅层131上，而第一自对准硅化物层133形成在SAB层132上。
此外，第一自对准硅化物层133通过使第二多晶硅层与由钛、镍、铜或者它们的组合物构成的反应层进行反应而形成。半导体基板110还包括第二自对准硅化物层115，MOS120还包括第三自对准硅化物层124，其中第一自对准硅化物层133、第二自对准硅化物层115和第三自对准硅化物层124是在同样的处理工序形成的相同的层结构。
如图1A和图1B所示，第一多晶硅层131具有第二上表面131u、第一侧表面131s1和与第一侧表面131s1相对的第二侧表面131s2。SAB层132覆盖第二上表面131u的一部分、第一侧表面131s1的一部分以及第二侧表面131s2的一部分。第一自对准硅化物层133形成在SAB层132的第三上表面132u上。
如图1C所示，第一多晶硅层131还具有第三侧表面131s3和与第三侧表面131s3相对的第四侧表面131s4。在此剖视图中，SAB层132覆盖第二上表面131u的第一部分131u1，但是使第二上表面131u的第二部分131u2、第三侧表面131s3及第四侧表面131s4露出。另外，第一自对准硅化物层133形成在SAB层132的第三上表面132u及第二上表面131u的第二部分131u2上。
如图1C所示，第一自对准硅化物层133包括形成于SAB层132上的第一硅化部1331、形成于第一多晶硅层131上的第二硅化部1332和形成于第一多晶硅层131上的第三硅化部1333。第一硅化部1331通过SAB层132的第五侧表面132s1与第二硅化部1332分离，且通过SAB层132的第六侧表面132s2与第三硅化部1333分离，其中，第五侧表面132s1与第六侧表面132s2相对。
如图1B所示，第一触点140形成在覆盖SAB层132的第一自对准硅化物层133的第一上表面133u上，且通过第一导线146与控制器145电连接。控制器145可向无源组件130提供恒定电压或者可控电压。第一自对准硅化物层133可使无源组件130与形成在层结构160之上的电路(图未示)隔离，以防止无源组件130的寄生电信号(例如寄生电阻、寄生电容、和/或寄生电感)干扰该电路。根据仿真结果，由于第一自对准硅化物层133的隔离，总谐波失真(total harmonic distortion，THD)可减少10dB。
按照可控电压方式，控制器145可以通过第一触点控制施加在第一自对准硅化物层133上的电压，以使其改变。按照恒定电压方式，控制器145可通过第一触点140控制施加在第一自对准硅化物层133上的电压，以保持第一自对准硅化物层133与第一多晶硅层131之间稳定的电压差值。例如，施加到第一多晶硅层131上的电压越大，施加到第一自对准硅化物层133上的电压也越大。这样一来，第一自对准硅化物层133与第一多晶硅层131之间的电压差就可以保持一个恒定的电压差值，因此，可以避免由电压差改变而引起的任何不利或者意外影响。
类似地，如图1C所示，第二触点150形成在第一自对准硅化物层133的覆盖第一多晶硅层131的第二部分131u2的第二硅化部1332上，且通过第二导线147与控制器145电连接。第三触点150’形成在第一自对准硅化物层133的覆盖第一多晶硅层131的第三部分131u2’的第三硅化部1333上，且通过第三导线147’与控制器145电连接。第二部分131u2和第三部分131u2’位于SAB层132的相对两侧且通过SAB层132相互隔离。
如图1C所示，控制器145可以通过第二触点150和/或第三触点150’控制施加到第一自对准硅化物层133的电压，以使其改变或者保持第一自对准硅化物层133和第一多晶硅层131之间稳定的电压差。
在另一实施例中，第一触点140和第二触点150其中之一可被省去。在其他实施例中，第一触点140和第二触点150都可以被省去，这样无源组件130与控制器145电分离。即使第一自对准硅化物层133可与控制器145电分离，第一自对准硅化物层133仍可以使无源组件130与形成在层结构160之上的电路隔离，以防止无源组件130的寄生电信号干扰该电路。
图2A至图2F例示了图1B中的半导体设备100的制造过程。
请参阅图2A，提供半导体基板110，其中，第一绝缘部112和第二绝缘部114嵌入半导体基板110中，第一多晶硅层131形成在半导体基板110上，SAB层132形成在第一多晶硅层131上，第二多晶硅层133’形成在SAB层132上，MOS 120形成在半导体基板110的上表面110u之上。
请参阅图2B，通过例如溅镀(sputtering)的方式形成覆盖第二多晶硅层133’、SAB层132、MOS 120、半导体基板110的上表面110u、第一多晶硅层131的上表面中未被SAB层132覆盖的部分、第一绝缘部112和第二绝缘部114的反应层10。例如，反应层10可以是钛、镍、铜、钴或者它们的组合为主要成分的反应物。
请参阅图2C，第二多晶硅层133’通过加热与反应层10反应，以形成具有低电阻的第一自对准硅化物层133，半导体基板110的上表面110u除绝缘部以外的部分与反应层10反应形成第二自对准硅化物层115，MOS 120中多晶硅层与反应层10反应形成第三自对准硅化物层124。此外，通过加热，反应层10与第一多晶硅层131的上表面中未被SAB层132覆盖的部分反应，形成自对准硅化物层。第一多晶硅层131、SAB层132和第一自对准硅化物层133组成无源组件130。在加热后，被反应层10覆盖的硅材料发生反应，从而形成多个自对准硅化物层。例如，第二多晶硅层133’、半导体基板110的上部及MOS 120的多晶硅层123的上部与反应层10发生反应，从而在同一加热过程中分别形成第一自对准硅化物层133、第二自对准硅化物层115和第三自对准硅化物层124。
请参阅图2D，通过例如蚀刻等操作移除反应层10。在反应层10被移除后，第一自对准硅化物层133、第二自对准硅化物层115和第三自对准硅化物层124显露出来。
请参阅图2E，形成覆盖MOS 120和无源组件130的层结构160。在一实施例中，例如，层结构160可以是层间介电层(interlayer dielectric layer)，并且例如可以覆盖整个半导体基板。
请参阅图2F，形成穿过层结构160的第一开口160a1、第二开口160a2(如图1C所示)及第三开口160a2’(如图1C所示)。
而后，第一开口160a1中填入图1B所示的第一触点140，第二开口160a2(如图1C所示)中填入如图1C所示的第二触点150，且第三开口160a2’(如图1C所示)中填入如图1C所示的第三触点150’。第一触点140、第二触点150和第三触点150’由相同材料制成，例如金属。
接着，形成用于连接第一触点140和控制器145的第一导线146以及用于连接第二触点150和控制器145的第二导线147和用于连接第三触点150’和控制器145的第三导线147’。控制器145用于向无源组件130提供恒定电压或可控电压。
本发明根据当前实用的、优选的实施例进行了描述，然而，应当理解，本发明的范围不受所公开的实施例限制。相反地，本发明的保护范围应被认为覆盖所附权利要求的精神和范围内的多种变形和类似的设置，且与权利要求最宽的解释范围相符以包括这些修改和类似的结构。

Claims (16)

1.一种半导体设备，包括：
半导体基板；以及
形成在所述半导体基板上的无源元件，包括：第一多晶硅层、硅化物阻止层和第一自对准硅化物层，所述硅化物阻止层形成于所述第一多晶硅层上并覆盖所述第一多晶硅层的上表面的至少一部分，所述第一自对准硅化物层覆盖所述硅化物阻止层的上表面。
2.如权利要求1所述的半导体设备，其特征在于，所述第一自对准硅化物层还覆盖所述第一多晶硅层的上表面中未被所述硅化物阻止层覆盖的部分。
3.如权利要求2所述的半导体设备，其特征在于，所述第一自对准硅化物层包括第一硅化部、第二硅化部和第三硅化部，其中所述第一硅化部覆盖所述硅化物阻止层的上表面，所述第二硅化部和所述第三硅化部覆盖所述第一多晶硅层的上表面中未被所述硅化物阻止层覆盖的部分。
4.如权利要求3所述的半导体设备，其特征在于，所述第二硅化部和所述第三硅化部位于所述硅化物阻止层的相对两侧并通过所述硅化物阻止层相隔离。
5.如权利要求3所述的半导体设备，其特征在于，所述第一硅化部通过所述硅化物阻止层的一个侧表面与所述第二硅化部分离，所述第一硅化部通过所述硅化物阻止层的另一个侧表面与所述第三硅化部分离。
6.如权利要求1所述的半导体设备，其特征在于，还包括第一触点，所述第一触点形成于所述第一自对准硅化物层，与控制器电连接以向所述无源元件提供恒定或可控电压。
7.如权利要求3所述的半导体设备，其特征在于，还包括第二触点和/或第三触点，所述第二触点形成于所述第二硅化部和/或所述第三触点形成于所述第三硅化部上，所述第二触点和/或所述所述第三触点与控制器电连接以向所述无源元件提供恒定或可控电压。
8.如权利要求1所述的半导体设备，其特征在于，还包括：
金属氧化物半导体，形成于所述半导体基板上；
第二自对准硅化物层，形成于所述金属氧化物半导体上的多晶硅层的上表面。
9.如权利要求8所述的半导体设备，其特征在于，所述半导体基板还包括嵌入所述半导体基板的上表面的绝缘部，所述无源器件形成于所述绝缘部上；其中，所述半导体设备还包括第三自对准硅化物层，所述第三自对准硅化物层覆盖所述半导体基板的上表面上除所述绝缘部和所述金属氧化物半导体以外的部分。
10.一种半导体设备制造方法，包括：
提供半导体基板；
在所述半导体基板的绝缘部上形成第一多晶硅层，在所述第一多晶硅层上形成硅化物阻止层，在所述硅化物阻止层上形成第二多晶硅层，所述硅化物阻止层覆盖所述第一多晶硅层的上表面的至少一部分；
形成反应层，所述反应层覆盖所述第二多晶硅层；以及
通过所述第二多晶硅层与所述反应层反应，形成第一自对准硅化物层。
11.如权利要求10所述的半导体设备制造方法，其特征在于，所述反应层进一步覆盖所述第一多晶硅层的上表面中未被所述硅化物阻止层覆盖的部分。
12.如权利要求10所述的半导体设备制造方法，其特征在于，所述反应层还覆盖所述半导体基板的上表面以及形成于所述半导体基板上的金属氧化物半导体，其中通过所述半导体基板的上表面和所述金属氧化物半导体与所述反应层反应，分别形成第二自对准硅化物层和第三自对准硅化物层。
13.如权利要求10所述的半导体设备制造方法，其特征在于，进一步包括：在形成所述第一自对准硅化物层后移除所述反应层。
14.如权利要求13所述的半导体设备制造方法，其特征在于，进一步包括：形成覆盖所述第一自对准硅化物层、所述第一多晶硅层和所述硅化物阻止层的层结构。
15.如权利要求10所述的半导体设备制造方法，其特征在于，在所述第一自对准硅化物层的第一硅化部上形成第一触点，其中所述第一硅化部通过所述反应层与所述第二多晶硅层反应形成。
16.如权利要求11所述的半导体设备制造方法，其特征在于，在所述第一自对准硅化物层的第二硅化部上形成第二触点，其中所述第二硅化部通过所述反应层与所述第一多晶硅层的上表面中未被所述硅化物阻止层覆盖的部分发生反应形成。
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