CN108352400B - 包封的纳米结构及其制造方法 - Google Patents
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- CN108352400B CN108352400B CN201680063745.XA CN201680063745A CN108352400B CN 108352400 B CN108352400 B CN 108352400B CN 201680063745 A CN201680063745 A CN 201680063745A CN 108352400 B CN108352400 B CN 108352400B
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
- H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
- H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
- H10D62/8164—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation comprising only semiconductor materials
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- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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- H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
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- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
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- H10D30/00—Field-effect transistors [FET]
- H10D30/501—FETs having stacked nanowire, nanosheet or nanoribbon channels
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
- H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6744—Monocrystalline silicon
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
- H10D62/118—Nanostructure semiconductor bodies
- H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
- H10D62/118—Nanostructure semiconductor bodies
- H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
- H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
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- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3451—Structure
- H10P14/3452—Microstructure
- H10P14/3462—Nanowires
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
- H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
- H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/90—Thermal treatments, e.g. annealing or sintering
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Nanotechnology (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562248561P | 2015-10-30 | 2015-10-30 | |
| US62/248,561 | 2015-10-30 | ||
| PCT/US2016/059037 WO2017075165A1 (en) | 2015-10-30 | 2016-10-27 | Encapsulated nanosturctures and method for fabricating |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108352400A CN108352400A (zh) | 2018-07-31 |
| CN108352400B true CN108352400B (zh) | 2021-09-10 |
Family
ID=58630816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680063745.XA Active CN108352400B (zh) | 2015-10-30 | 2016-10-27 | 包封的纳米结构及其制造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US9985101B2 (enExample) |
| JP (1) | JP6773795B2 (enExample) |
| KR (1) | KR102557215B1 (enExample) |
| CN (1) | CN108352400B (enExample) |
| TW (1) | TWI705499B (enExample) |
| WO (1) | WO2017075165A1 (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3046243B1 (fr) * | 2015-12-24 | 2017-12-22 | Commissariat Energie Atomique | Capteur nw-fet comportant au moins deux detecteurs distincts a nanofil de semi-conducteur |
| KR102429611B1 (ko) * | 2016-06-10 | 2022-08-04 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
| EP3382761A1 (en) | 2017-03-29 | 2018-10-03 | IMEC vzw | Integration of silicon-germanium semiconductor structures |
| EP3425673A1 (en) * | 2017-07-04 | 2019-01-09 | IMEC vzw | Germanium nanowire fabrication |
| US10680063B2 (en) * | 2018-09-07 | 2020-06-09 | International Business Machines Corporation | Method of manufacturing stacked SiGe nanotubes |
| WO2020219372A1 (en) * | 2019-04-24 | 2020-10-29 | National Technology & Engineering Solutions Of Sandia, Llc | Method for fabricating embedded nanostructures with arbitrary shape |
| JP7256708B2 (ja) | 2019-07-09 | 2023-04-12 | 株式会社荏原製作所 | めっき装置 |
| TWI805947B (zh) * | 2019-10-21 | 2023-06-21 | 美商應用材料股份有限公司 | 水平gaa奈米線及奈米平板電晶體 |
| US11094699B1 (en) | 2020-05-28 | 2021-08-17 | Micron Technology, Inc. | Apparatuses including stacked horizontal capacitor structures and related methods, memory devices, and electronic systems |
| KR102932718B1 (ko) | 2021-02-03 | 2026-03-04 | 삼성전자주식회사 | 반도체 소자 |
| WO2023039307A2 (en) * | 2021-05-28 | 2023-03-16 | University Of Florida Research Foundation, Inc. | Self-amplified resonators with embedded piezoresistive elements for high performance, ultra-low swap microwave and millimeter-wave applications |
| US12262559B2 (en) * | 2022-04-07 | 2025-03-25 | Applied Materials, Inc. | Monolithic complementary field-effect transistors having carbon-doped release layers |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010129974A (ja) * | 2008-12-01 | 2010-06-10 | Toshiba Corp | 相補型半導体装置とその製造方法 |
| CN104137237A (zh) * | 2011-12-23 | 2014-11-05 | 英特尔公司 | 具有非分立的源极区和漏极区的纳米线结构 |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2003290510A1 (en) * | 2002-06-26 | 2004-04-19 | Cornell Research Foundation, Inc. | Small scale wires with microelectromechanical devices |
| KR100481209B1 (ko) * | 2002-10-01 | 2005-04-08 | 삼성전자주식회사 | 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법 |
| TWI283066B (en) * | 2004-09-07 | 2007-06-21 | Samsung Electronics Co Ltd | Field effect transistor (FET) having wire channels and method of fabricating the same |
| US7405465B2 (en) * | 2004-09-29 | 2008-07-29 | Sandisk 3D Llc | Deposited semiconductor structure to minimize n-type dopant diffusion and method of making |
| WO2006101659A2 (en) | 2005-03-17 | 2006-09-28 | The George Washington University | Method of making nanoparticle wires |
| US20080135949A1 (en) * | 2006-12-08 | 2008-06-12 | Agency For Science, Technology And Research | Stacked silicon-germanium nanowire structure and method of forming the same |
| JP4310399B2 (ja) * | 2006-12-08 | 2009-08-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US7821061B2 (en) | 2007-03-29 | 2010-10-26 | Intel Corporation | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications |
| FR2924108B1 (fr) * | 2007-11-28 | 2010-02-12 | Commissariat Energie Atomique | Procede d'elaboration, sur un materiau dielectrique, de nanofils en materiaux semi-conducteur connectant deux electrodes |
| US8273591B2 (en) | 2008-03-25 | 2012-09-25 | International Business Machines Corporation | Super lattice/quantum well nanowires |
| US7851790B2 (en) * | 2008-12-30 | 2010-12-14 | Intel Corporation | Isolated Germanium nanowire on Silicon fin |
| JP2011199105A (ja) * | 2010-03-23 | 2011-10-06 | Toshiba Corp | 半導体装置の製造方法 |
| US8753942B2 (en) * | 2010-12-01 | 2014-06-17 | Intel Corporation | Silicon and silicon germanium nanowire structures |
| US8859389B2 (en) * | 2011-01-28 | 2014-10-14 | Kabushiki Kaisha Toshiba | Methods of making fins and fin field effect transistors (FinFETs) |
| JP5271372B2 (ja) * | 2011-03-18 | 2013-08-21 | 株式会社東芝 | 半導体装置の製造方法 |
| CN104126222B (zh) * | 2011-12-23 | 2017-06-13 | 英特尔公司 | 单轴应变纳米线结构 |
| US8927405B2 (en) * | 2012-12-18 | 2015-01-06 | International Business Machines Corporation | Accurate control of distance between suspended semiconductor nanowires and substrate surface |
| US9064942B2 (en) * | 2013-01-28 | 2015-06-23 | International Business Machines Corporation | Nanowire capacitor for bidirectional operation |
| US9184269B2 (en) | 2013-08-20 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
| US8872161B1 (en) * | 2013-08-26 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrate circuit with nanowires |
| US9263520B2 (en) * | 2013-10-10 | 2016-02-16 | Globalfoundries Inc. | Facilitating fabricating gate-all-around nanowire field-effect transistors |
| US9660035B2 (en) | 2014-01-29 | 2017-05-23 | International Business Machines Corporation | Semiconductor device including superlattice SiGe/Si fin structure |
| US9985030B2 (en) | 2014-04-07 | 2018-05-29 | International Business Machines Corporation | FinFET semiconductor device having integrated SiGe fin |
| WO2015171699A1 (en) * | 2014-05-07 | 2015-11-12 | President And Fellows Of Harvard College | Controlled growth of nanoscale wires |
| US9431483B1 (en) * | 2015-03-16 | 2016-08-30 | United Microelectronics Corp. | Nanowire and method of fabricating the same |
-
2016
- 2016-10-27 CN CN201680063745.XA patent/CN108352400B/zh active Active
- 2016-10-27 JP JP2018542684A patent/JP6773795B2/ja active Active
- 2016-10-27 KR KR1020187015224A patent/KR102557215B1/ko active Active
- 2016-10-27 WO PCT/US2016/059037 patent/WO2017075165A1/en not_active Ceased
- 2016-10-27 US US15/335,605 patent/US9985101B2/en active Active
- 2016-10-28 TW TW105134945A patent/TWI705499B/zh active
-
2018
- 2018-04-30 US US15/966,482 patent/US10411096B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010129974A (ja) * | 2008-12-01 | 2010-06-10 | Toshiba Corp | 相補型半導体装置とその製造方法 |
| CN104137237A (zh) * | 2011-12-23 | 2014-11-05 | 英特尔公司 | 具有非分立的源极区和漏极区的纳米线结构 |
Non-Patent Citations (1)
| Title |
|---|
| Investigation of silicon-germanium fins fabricated using germanium condensation on vertical compliant structures;Tsung-Yang Liow, et al;《Applied Physics Letters》;20051219;第87卷(第26期);第262104-1~62104-3 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6773795B2 (ja) | 2020-10-21 |
| WO2017075165A1 (en) | 2017-05-04 |
| KR20180079388A (ko) | 2018-07-10 |
| TWI705499B (zh) | 2020-09-21 |
| KR102557215B1 (ko) | 2023-07-18 |
| JP2018537867A (ja) | 2018-12-20 |
| US10411096B2 (en) | 2019-09-10 |
| US20170125526A1 (en) | 2017-05-04 |
| US9985101B2 (en) | 2018-05-29 |
| CN108352400A (zh) | 2018-07-31 |
| TW201724268A (zh) | 2017-07-01 |
| US20180248007A1 (en) | 2018-08-30 |
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