CN1082296A - 测量时滞误差的装置 - Google Patents

测量时滞误差的装置 Download PDF

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CN1082296A
CN1082296A CN93107665A CN93107665A CN1082296A CN 1082296 A CN1082296 A CN 1082296A CN 93107665 A CN93107665 A CN 93107665A CN 93107665 A CN93107665 A CN 93107665A CN 1082296 A CN1082296 A CN 1082296A
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D·L·麦克尼利
G·A·克兰纳韦特
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Abstract

用于处理视频信号的时钟信号的时滞测量装置 包括施加时钟信号的级联模拟延迟元件。延迟元件 各输出连至加有表示行同步信号的信号的各存储元 件之数据输入端，以同时将信号存入其内而在其内截 获取样时钟信号的一个代表性循环。解码电路与存 储元件相连，以测定紧接行脉冲后沿之前的取样时钟 脉冲前沿的相对位置，计算表示时滞误差的比值，这 个比值对应于以延迟单位数表示的第一跃变的位置 除以以延迟单位数表示的取样时钟周期宽度。

Description

本发明涉及测量视频信号处理系统中定时误差的装置，尤其涉及测量在行同步脉冲跃变和信号处理时钟脉冲的特定跃变之间的时间宽度或时滞的装置。
以取样数据格式处理信号的视频信号处理装置一般按取样时钟信号所定的时刻对视频信号取样，最好取样时钟信号与行同步信号有一个固定的关系。此外，为简化信号处理，最好时钟信号的频率为色度副载波频率的整数倍。假如对标准信号的倍数为，例如，4的偶数，那末每个行间隔中有整数个时钟周期。假如在取样时钟和行同步信号之间保持固定的关系，在依次行上相应的取样点在垂直方向上是对准的。反之，假如这个关系被改变，在依次行上相应的取样间隔在垂直方向上就不对准。假如取样信号在显示之前被存储和处理，取样间隔（因此象素）的垂直方向不对准在重现的图象上表现为锯齿的垂直边缘。例如当视频信号来自录相机和影碟机时就会发生这种情况，该信号以取样数据格式被处理，以提供例如静止帧面或画中画的特殊效果。这问题和相应的介决方法已在题为“具有对非标准信号校准的逐行扫描显示系统”的美国专利No.4630098中详细讨论。然而为计算取样误差或时滞而展示的装置相对复杂化，并需要较长时间周期来计算各自的时滞误差。
本发明包括测量作为时钟周期几分之一的时滞的装置，对于器件的参数较不敏感。取样时钟信号加在级联的数量上足以包含一个完整时钟周期的若干个模拟延迟元件上。每个模拟延迟元件的输出连接至各自存储元件的数据输入端。表示行同步信号的信号加在存储元件上，并同时将信号锁入各自存储元件，因而在存储元件中截获取样时钟信号的典型周期。解码电路连接至存储元件，以检测（例如）在行脉冲的后沿之前紧邻的取样时钟脉冲的前沿的相对位置。对应于以延迟单元表示的第一跃变的位置除以以延迟单元表示的取样时钟周期的宽度的算得的比值表示时滞误差。
图1、3和5是几个可供选择的时滞测量电路的实施例的方块图;
图2是可以实现图1装置的元件22的示范电路的方块图;
图4是用于说明本发明操作的时序图。
本文中时滞定义为对预定时钟信号脉冲的预定跃变和计时数据的预定跃变之间的时间宽度的度量。在本文讨论的例子中计时数据对应于表示行同步的信号，而跃变是例如行同步脉冲的后沿。最好时钟信号的预定跃变是尾随行同步脉冲后沿之后的第一个时钟脉冲的前沿。然而，这种第一个时钟脉冲在行同步脉冲的后沿出现时不可用于时间测量。因此该测量是相对于时间上最靠近的时钟脉冲，例如在行同步的后沿之前的最后那个时钟脉冲进行的。
先参阅图4。图中时间相对于时序波形是从右至左消逝的。标有“取样时钟”的波形加在模拟抽头式的延迟线200上。在元件200中每个小方块表示一个与其相邻延迟元件串联的各个模拟延迟元件。名义上模拟延迟线应该包括足以容纳取样时钟信号的两个前沿的元件。来自各个模拟延迟元件的输出，连接至若干个存储元件202的各个数据输入端。行同步信号或由此导出的信号（此后称Hsync）加在各个存储元件的控制输入端。一旦行同步脉冲的后沿到来，驻留在延迟线200的各个模拟延迟元件中的信号被截获，并被锁定在各自的存储元件内。
通过计算在级联连接的延迟元件的输入端和在行同步的后沿之前发生的最后时钟脉冲的负向跃变之间的延迟元件数目就可以测定时滞。（注意沿着存储元件从左至右，取样时钟脉冲的前沿被反相）这个计数值与等于一个取样周期减去时滞（以延迟间隔为单位表示）的值相对应。为了测定时滞，人们只需测量延迟元件中的一个取样周期，然后再减去该计数值。最后为了将时滞值归一为时钟周期的百分数，此差值要除以取样周期。例如，假定在Hsync信号的后沿之前的最后时钟脉冲的正向跃变是从延迟线开始起的A个延迟周期，还假定次后（secondlastmost）脉冲的正跃变是从延迟线开始的B个延迟周期。时钟脉冲周期以延迟周期为单位等于B-A。换句话说时滞以延迟单位数表示为：
时滞＝（B-A）-A    （1）
经归一化后表示为等于一个时钟周期的一部分的分数：
时滞＝ (（B-A）-A)/(（B-A）) （2）
假如时钟信号是方波，那末延迟线不必为足以容纳二个先前的时钟脉冲正跃变的那样长。可以将例如A和C的任何二个相邻跃变之间的间隔乘以2测得时钟周期。在使用时滞值处理视频信号的大多数应用场合，既需要时滞值也需要它的补数。因此一般说可以测量或者时滞值或者它的补数，另一值直接从测量值计算求得。
图1表示依照本发明的时滞测量电路的第一个实施例。易发生时滞误差的时钟输入信号加在延迟元件（11、12、23）的级联连接件10上。这些延迟元件可以是具有例如为4毫微秒或更小的固有处理延迟时间的缓冲放大器。该级联连接件的总延迟时间至少等于一个时钟周期，每个延迟元件的输出连接至“D”型锁存器（13、14、24）序列20的各自一个上。Hsync信号加在所有锁存器20的时钟或控制输入端上，一旦Hsync信号的相应跃变（在时间tO）到来，则支配锁存器存入在各个延迟元件10的输出端上呈现的信号值。
一系列与门30连接至依次成对的锁存器上。每个与门的第一输入端连接至第一锁存器的Q输出端，而第二输入端连接至下一个依次相邻的锁存器的 Q输出端。这样与门被安排为跃变检测器，以检测负向跃变，即，存储在锁存器中的时钟脉冲的前沿或正向跃变。
与门30的输出端连接至时滞发生器22和各个输入端。与门30的各个输出端又连接至或门40的允许菊花链的输入端和第二系列双输入与门50的各个输入端。菊花链的输出接线连接至各个与门50的第二输入端。起初所有与门50被或门的菊花链所禁止。检测到跃变并最靠近延迟线输入（最靠近该图的上部）的其中一个与门30将逻辑“1”值加在与之相连的或门上，该或门本身又产生逻辑“1”，加在所有依次相连的或门上。产生逻辑“1”值的或门启动分别与之相连的与门系列50，从而通过来自与门30系列的逻辑值。与门50的输出接线连接至时滞发生器22。
各个与门30中任何一个可以检测跃变，至少二个与门30会同时检测到这种跃变。所有这种检测值直接馈送至发生器22。为对这些检测值作出响应，发生器22决定在Hsync出现之前最后时钟脉冲的前沿位置（例如等式1的A值）。
由或门的菊花链启动/禁止的与门50会传递除了检测到最接近延迟线输入的跃变的与门30之外的所有与门30的检测信号。发生器22响应由第二与门系列50提供的逻辑电平，确定次后时钟脉冲的前沿位置（例如等式1的B值）。
一旦这两个时钟脉冲的前沿跃变的相对位置被测定，时滞发生器22根据例如等式1或2计算时滞值。发生器22可以是将与输入到地址总线Ai和Bi的值的恰当组合相对应的时滞值按地址位置编程的存储器。然而要注意假如有20个延迟级，那末在图1例中有40个地址线，意味要有240个存储单元的存储器。然而在40个地址线Ai和Bi上产生的逻辑值不会有240不同的组合。这样使用存储器解码时滞值是可能的，但不实际。回想Ai地址线包括在时间tO以前的第一和第二时钟脉冲的两个跃变的检测。这就是为计算或者方程1，或者方程2所必须的全部信息，这样，发生器22可以用具有20个地址线和只要220地址单元的存储器来实现。然而这仍然是不很实际的解决方案，因为可发生在地址输入线上的有效输入组合数是很有限的。
图2示出时滞发生器22的更具体有效元件。在图2中，来自与门30的输出值Ai连接至第一解码器61，而来自与门50的输出值Bi送至第二解码器60。在第一和第二解码器中的逻辑可类似于在闪光模数解码器中所使用的逻辑，它将互不相容的值赋予一系列分级安排的逻辑输出值中之一，以表示一个状态与其他状态之不同。在本例中，互不相容值对应于在延迟单元中所检测的跃变的单元（数目）。解码器61和60提供A值和B值，因为它们与等式1和2有关。
来自解码器61和60的值A和B被送至产生它们幅度之差｜B-A｜的减法器的各自输入端。差值和A值被送至产生商数A/｜A-B｜的除法器65。此商值又被加到减法电路66上，以产生输出值（1-A/｜A-B｜），该值等效于等式2的时滞值。注意这些时滞值是从取样时钟周期的几分之一的形式被测得，其精度取决于为获得一个时钟周期的总延迟所使用的延迟元件的数量。这种形式的时滞值对某些应用场合可能是无用的，但一般说可以简便地通过对减法电路66的输出加以定标而转化为其他形式。
应当知道，图2的全部元件可以归结入诸如状态机之类的单一处理元件中。
图3说明本发明的另一个例子，其包括抽头式模拟延迟线100，易发生时滞误差的取样时钟信号便加在该延迟线上。延迟线100的各个抽头连接至并行输入串行输出的移位寄存器102的并行输入端。移位寄存器102有与Hsync信号相连的JAM输入端并响应Hsync信号的相应跃变，将延迟线100的现行内容装入移位寄存器102。在装入移位寄存器后，时钟信号通过与门104加到移位寄存器的时钟输入端，以串行地读出存在寄存器内的数据。加在移位寄存器上的时钟信号也加在时钟脉冲计数的二进制计数器105。计数器105提供的计数值加在第一个“D型”锁存器107的数据输入端。锁存器107的输出又与第二“D型”锁存器108的数据输入端相连。该“D型”锁存器108的时钟或控制输入端与跃变检测器103相连。跃变检测器103对寄存器102的数据读出作出响应。一旦第一次发生从寄存器读出的与取样时钟信号的前沿跃变对应的跃变时，锁存器107被支配，以存储由计数器105呈现的现行计数值。这个计数值对应于等式1或2所定义的A值。当第二次发生与从寄存器102读出的取样时钟信号的前沿相对应的跃变时，锁存器108受支配，以存储锁存器107中所存储的计数值A，而锁存器107又受支配，以存储在计数器105输出端呈现的现行计数值。这后一个计数值对应于等式1或2所定义的B的值。存储在锁存器107和108中的A和B值被送至按照（例如）等式2求出时滞的计算电路106。
在图1-3中所示的例子倾向于采用类似的算法来计算时滞值。人们可以使用对在存储元件（寄存器）中截获的取样时钟跃变的不同算法，而达到类似的结果。
Wolfgang    Gollinger等人在美国专利No.4489342中已阐明了在模拟延迟器件的级联上例如：100）上加以偏压，以得到精确等于所加时钟信号的一个周期的总延迟量的方法。由于已知在级联连接中所使用的模拟延迟级数，故唯一需要知道的是在存储元件（20或102）中截获的取样时钟信号的一个跃变的位置（A）。延迟级的总数对应于B-A。假定这个数等于16，它可以用一个四位二进制数表示。因此取样时钟信号的前沿跃变位置A可以用一个四位二进制数表示，考虑到上述情况，图3的电路可以改为如图5所示，取消了锁存器108，而用一个简单编程的只有16个存储单元的只读存储器（ROM）代替计算器106。每个存储单元被编程为时滞值1-A/N，此处N是级联连接的延迟线中延迟级的数目，在本例中假定为16，而A值与各个地址相对应。锁存器107截获所截获时钟信号的跃变前沿处计数值，并将此数值作为地址加到ROM120上。ROM响应该地址值而输出时滞值。（注意，除了图5的延迟线100是被安排为具有等于一个取样时钟周期的总延迟量的类型以外，图5中标注有与图3中元件相同数字的元件是类似的，并执行相同功能）。
进一步的简化包括反转寄存器102被读出的方向。假如按虚线122所示，跃变检测器103与寄存器102的相对端相连，所截获的取样时钟脉冲的跃变前沿位置（计数值）将等于以延迟单元表示的时滞测量值。可通过将该计数值除以N，将该值归一化。在本例中ROM120的各个地址单元用等于A/N的时滞值编程。
图1实施例最好用于必须在极少量时钟取样周期内算得时滞值的应用场合。图3或图5实施例适用于时滞计算时间不严格的场合，因为这些实施例一般使用不太复杂的硬件。

Claims (10)

1、测量在时钟信号的预定跃变和另一种信号的预定跃变之间的时滞的装置，它包括：
一个所述时钟信号源和一个所述另一信号的源，其特征在于：
与所述时钟信号源相连，并具有一系列抽头的模拟延迟线，以提供延迟几乎相等增量的一系列经延迟的所述时钟复制信号；
响应所述另一信号的所述预定跃变，用以将在所述抽头的每一个上产生的信号同时进行存储的装置；
与所述存储装置相连的用以测定在所述存储装置中所述时钟信号的所述预定跃变以延迟单元数表示的位置；和
对所述位置作出反应，用以产生所述时滞值的装置。
2、如权利要求1所述的装置，其特征在于：对所述位置作出反应产生所述时滞值的所述装置作为所述位置除以所述时钟信号的一个循环周期的函数而产生所述时滞值;
3、如权利要求2所述的装置，其特征在于：测定所述时钟信号的所述预定跃变的位置的所述装置包括以延迟单元数为单位测量所述周期的装置;
4、如权利要求2所述的装置、其特征在于：用于同时存储在每一个所述抽头上产生的信号的所述装置包括一系列按序编号的锁存器，这些锁存器具有分别与对应序号的所述抽头中一个相连的各个数据输入端和与解码装置相连的各个输出端，所述解码装置产生表示所述时钟信号的至少一个所述预定跃变的相对位置的值，计算装置对表示所述位置的所述值作出响应，产生所述时滞值。
5、如权利要求4所述的装置，具特征还在于：所述解码装置被安排为提供指示所述时钟信号的所述预定跃变的所述位置的第一值A和指示以延迟单元为单位的第二个跃变位置的第二值B，而所述计算装置产生作为A除以A和B之差值的函数的所述时滞值。
6、如权利要求1所述的装置，其特征在于：用于同时存储在每一个所述抽头上产生的信号的所述装置包括并行输入串行输出移位寄存器，该移位寄存器的并行输入端与所述抽头的各自一个相连，其输出端与跃变检测器相连，其控制输入端与所述另一信号的所述源相连，从而响应所述另一信号的所述预定跃变对所述移位寄存器进行并行装入。
7、如权利要求6中所述的装置，其特征还在于：从延迟单元数为单位测定所述时钟信号的所述预定跃变位置的所述装置包括：
将时钟信号加到所述移位寄存器上的装置，用以将数据从所述移位寄存器串行读出，送入所述跃变检测器;
对加到所述移位寄存器上的所述时钟信号的脉冲进行计数，并提供各个计数值的计数装置;
对所述跃变检测器作出响应，存贮所述计数值的锁存装置。
8、如权利要求7所述的装置，其特征还在于：响应存入所述锁存装置的计数值用于产生作为对应于所述时钟信号的所述预定跃变的计数值除以所述时钟信号的一个循环周期的函数的时滞值装置。
9、如权利要求7所述的装置，其特征还在于：所述锁存装置包括用于存储与所述时钟信号的第一个跃变在所述移位寄存器中位置相对应的第一个值A和与所述时钟信号的第二个跃变在所述移位寄存器中位置相对应的第二个值B的装置;和
产生所述时滞值的所述装置产生作为A/（B-A）的函数的这个值。
10、如权利要求7的所述装置，其特征还在于：有与所述锁存器相连的地址输入端口的存储器，用以施加作为存储器地址的所述计数值，其各个地址单元按程序具有所述时滞值。
CN93107665A 1992-06-26 1993-06-25 测量时滞误差的装置 Expired - Fee Related CN1045146C (zh)

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