CN108172507A - Mps-frd器件的加工方法 - Google Patents
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Abstract
本发明涉及一种制备方法,尤其是一种MPS‑FRD器件的加工方法,属于微电子的技术领域。本发明利用了肖特基区场氧阻挡阳极P型杂质离子注入,保护肖特基区场氧下方的半导体基板,通过孔刻蚀一次性刻蚀去除ILD介质层和肖特基区场氧,从而形成MPS‑FRD阳极P‑i‑N和schottky交错的形貌结构,在设置阳极金属层后能与P阱欧姆接触,而与元胞区的半导体基板为肖特基接触,工艺步骤简单,与现有工艺兼容,缩短加工周期,能减少光刻工艺,降低加工成本,提高MPS‑FRD产品品质。
Description
技术领域
本发明涉及一种制备方法,尤其是一种MPS-FRD器件的加工方法,属于微电子的技术领域。
背景技术
MPS(Merged P-i-N/Schottky)二极管称为PIN/肖特基混合的快恢复二极管,是一种把PIN快恢复二极管和肖特基二极管的功能组合在一起的新型器件,主流加工通过光刻注入,高温推进形成阳极P型区域,ILD介质层淀积,光刻刻蚀接触孔,然后正面金属工艺形成P-i-N与schottky交错的阳极。在具体过程中,需要对光刻注入形成阳极P型区域,增加了一道光刻成本,增长生产周期;同时,肖特基的N-区域在前段工艺中暴露,经过前段高温工艺过程会产生自掺杂现象,影响产品品质。
发明内容
本发明的目的是克服现有技术中存在的不足,提供一种MPS-FRD器件的加工方法,其工艺步骤简单,与现有工艺兼容,缩短加工周期,降低加工成本,提高MPS-FRD产品品质。
按照本发明提供的技术方案,所述MPS-FRD器件的加工方法,所述加工方法包括如下步骤:
步骤1、提供N导电类型的半导体基板,并在所述半导体基板的正面生长场氧层;
步骤2、对覆盖在半导体基板元胞区的场氧层进行刻蚀,以得到半导体基板元胞区上的肖特基区场氧;
步骤3、在上述半导体基板正面的上方进行P型杂质离子的注入,推阱后,以得到位于元胞区的半导体基板内的P阱;
步骤4、在上述半导体基板的上表面进行ILD介质淀积,以得到覆盖在半导体基板正面以及肖特基区场氧上的ILD介质层;
步骤5、对上述ILD介质层进行刻蚀,以同时去除半导体基板元胞区上的ILD介质层以及肖特基区场氧;
步骤6、在上述元胞区的半导体基板上设置阳极金属层,所述阳极金属层与半导体基板内的P阱欧姆接触,且阳极金属层与元胞区的半导体基板肖特基接触;
步骤7、对上述半导体基板的背面进行所需的背面工艺,以得到所需的阴极金属层。
在进行背面工艺后,阴极金属层与N+衬底后面接触,N+衬底通过N型缓冲层与N型漂移层连接,P阱位于N型漂移层内。
本发明的优点:利用了肖特基区场氧阻挡阳极P型杂质离子注入,保护肖特基区场氧下方的半导体基板,通过孔刻蚀一次性刻蚀去除ILD介质层和肖特基区场氧,从而形成MPS-FRD阳极P-i-N和schottky交错的形貌结构,在设置阳极金属层后能与P阱欧姆接触,而与元胞区的半导体基板为肖特基接触,工艺步骤简单,与现有工艺兼容,缩短加工周期,能减少光刻工艺,降低加工成本,提高MPS-FRD(Fast Recovery Diode,快恢复二极管)产品品质。
附图说明
图1~图3为本发明具体实施工艺过程剖视图,其中
图1为本发明进行P型杂质离子注入的示意图。
图2为本发明ILD介质层覆盖在肖特基区场氧上的示意图。
图3为本发明得到阴极金属层后的剖视图。
附图标记说明:1-N型漂移区、2-N型缓冲层、3-N+衬底、4-阴极金属层、5-阳极金属层、6-P阱、7-半导体基板、8-场氧层、9-注入孔、10-ILD介质层。
具体实施方式
下面结合具体附图和实施例对本发明作进一步说明。
为了缩短加工周期,降低加工成本,提高MPS-FRD产品品质,本发明的MPS-FRD器件的加工方法包括如下步骤:
步骤1、提供N导电类型的半导体基板7,并在所述半导体基板7的正面生长场氧层8;
具体地,半导体基板7可以采用常用的半导体材料制成,如硅等,半导体基板7为N导电类型,采用本技术领域常用的技术手段能在半导体基板7的正面生长场氧层8,所述场氧层8覆盖在半导体基板7的正面。
一般地,半导体基板7包括N型漂移区1、位于所述N型漂移区1下方的N型缓冲层2以及位于所述N型缓冲层2下方的N+衬底3;N型漂移区1的掺杂浓度小于N型缓冲层2、N+衬底3的掺杂浓度,N型漂移区1的厚度大于N型缓冲层2、N+衬底3的厚度,N型缓冲层2位于N型漂移区1与N+衬底3之间,且N型缓冲层2分别邻接N型漂移区1以及N+衬底3。当然,在具体实施时,半导体基板7还可以采用其他构成形式,具体可以根据需要进行选择,此处不再赘述。场氧层8生长在N型漂移区1上表面。
步骤2、对覆盖在半导体基板7元胞区的场氧层8进行刻蚀,以得到半导体基板7元胞区上的肖特基区场氧;
具体地,器件包括位于半导体基板7中心区的元胞区以及位于所述元胞区外圈的终端结构,利用终端结构能提高元胞区的耐压,元胞区、终端结构的具体配合等均为本技术领域人员所熟知,此处不再赘述。
对场氧层8进行刻蚀时,采用本技术领域常用的技术手段对元胞区的场氧层8进行掩蔽与刻蚀,以得到位于元胞区上的肖特基区场氧,肖特基区场氧外的场氧层8被刻蚀掉,从而通过肖特基区场氧能在半导体基板7的正面形成注入孔9,通过注入孔9能使得半导体基板7相应的正面露出,如图1所示。
步骤3、在上述半导体基板7正面的上方进行P型杂质离子的注入,推阱后,以得到位于元胞区的半导体基板7内的P阱6;
本发明实施例中,注入P型杂质离子的类型可以根据需要进行选择,在注入后,采用本技术领域常用的高温推阱方式,在元胞区的半导体基板7内得到P阱6,即P阱6位于N型漂移层1内,P阱6的深度小于N型漂移层1的厚度。
步骤4、在上述半导体基板7的上表面进行ILD介质淀积,以得到覆盖在半导体基板7正面以及肖特基区场氧上的ILD介质层10;
本发明实施例中,采用本技术领域常用的技术手段,在半导体基板7的正面设置ILD介质层10,ILD介质层10覆盖在肖特基区场氧上,ILD介质层10填充在注入孔9后,覆盖在半导体基板7相应的正面上,如图2所示。
步骤5、对上述ILD介质层10进行刻蚀,以同时去除半导体基板7元胞区上的ILD介质层10以及肖特基区场氧;
本发明实施例中,采用本技术领域常用的技术手段对ILD介质层10进行刻蚀,同时去除ILD(Inter layer dielectric,中间层介质)介质层10以及肖特基区场氧,即使得元胞区的半导体基板7的正面全裸露。
步骤6、在上述元胞区的半导体基板7上设置阳极金属层5,所述阳极金属层5与半导体基板7内的P阱6欧姆接触,且阳极金属层5与元胞区的半导体基板7肖特基接触;
本发明实施例中,阳极金属层5可以采用溅射等方式设置在半导体基板7的正面,一般地,阳极金属层5均位于元胞区,具体制备阳极金属层5的具体工艺过程为本技术领域人员所熟知,此处不再赘述。阳极金属层5覆盖在N型漂移层1上后,阳极金属层5与P阱6欧姆接触,而与元胞区的半导体基板7为肖特基接触。此外,在制备得到阳极金属层5后,还需要在阳极金属层5上设置钝化层等,具体制备钝化层的工艺过程为本技术领域人员所熟知,此处不再赘述。
步骤7、对上述半导体基板7的背面进行所需的背面工艺,以得到所需的阴极金属层4。
本发明实施例中,进行的背面工艺包括减薄,N型离子注入与激活,具体减薄、离子注入与激活的工艺过程为本技术领域人员所熟知。具体地,在减薄后,采用N型离子注入与激活后,能得到N型缓冲层2以及N+衬底3。在进行背面工艺后,阴极金属层4与N+衬底3后面接触,N+衬底3通过N型缓冲层2与N型漂移层1连接,P阱6位于N型漂移层1内。通过阴极金属层4与N+衬底3的欧姆接触,能形成二极管的阴极端。
Claims (2)
1.一种MPS-FRD器件的加工方法,其特征是,所述加工方法包括如下步骤:
步骤1、提供N导电类型的半导体基板(7),并在所述半导体基板(7)的正面生长场氧层(8);
步骤2、对覆盖在半导体基板(7)元胞区的场氧层(8)进行刻蚀,以得到半导体基板(7)元胞区上的肖特基区场氧;
步骤3、在上述半导体基板(7)正面的上方进行P型杂质离子的注入,推阱后,以得到位于元胞区的半导体基板(7)内的P阱(6);
步骤4、在上述半导体基板(7)的上表面进行ILD介质淀积,以得到覆盖在半导体基板(7)正面以及肖特基区场氧上的ILD介质层(10);
步骤5、对上述ILD介质层(10)进行刻蚀,以同时去除半导体基板(7)元胞区上的ILD介质层(10)以及肖特基区场氧;
步骤6、在上述元胞区的半导体基板(7)上设置阳极金属层(5),所述阳极金属层(5)与半导体基板(7)内的P阱(6)欧姆接触,且阳极金属层(5)与元胞区的半导体基板(7)肖特基接触;
步骤7、对上述半导体基板(7)的背面进行所需的背面工艺,以得到所需的阴极金属层(4)。
2.根据权利要求1所述的MPS-FRD器件的加工方法,其特征是:在进行背面工艺后,阴极金属层(4)与N+衬底(3)后面接触,N+衬底(3)通过N型缓冲层(2)与N型漂移层(1)连接,P阱(6)位于N型漂移层(1)内。
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Cited By (2)
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CN109004022A (zh) * | 2018-08-13 | 2018-12-14 | 深圳市天佑照明有限公司 | 一种二极管及其制造方法 |
CN110416319A (zh) * | 2019-08-21 | 2019-11-05 | 江苏中科君芯科技有限公司 | 双面肖特基控制的快恢复二极管器件及制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004055586A (ja) * | 2002-07-16 | 2004-02-19 | Nippon Inter Electronics Corp | 半導体装置及びその製造方法 |
US20050161759A1 (en) * | 2004-01-27 | 2005-07-28 | Davide Chiola | Merged P-i-N schottky structure |
TW201513229A (zh) * | 2013-09-17 | 2015-04-01 | Motion Semiconductor Corp | 接面位障蕭特基二極體的製造方法及其結構 |
CN106298774A (zh) * | 2015-06-10 | 2017-01-04 | 北大方正集团有限公司 | 一种mps二极管及其制造方法 |
-
2017
- 2017-12-27 CN CN201711442696.3A patent/CN108172507A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004055586A (ja) * | 2002-07-16 | 2004-02-19 | Nippon Inter Electronics Corp | 半導体装置及びその製造方法 |
US20050161759A1 (en) * | 2004-01-27 | 2005-07-28 | Davide Chiola | Merged P-i-N schottky structure |
TW201513229A (zh) * | 2013-09-17 | 2015-04-01 | Motion Semiconductor Corp | 接面位障蕭特基二極體的製造方法及其結構 |
CN106298774A (zh) * | 2015-06-10 | 2017-01-04 | 北大方正集团有限公司 | 一种mps二极管及其制造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109004022A (zh) * | 2018-08-13 | 2018-12-14 | 深圳市天佑照明有限公司 | 一种二极管及其制造方法 |
CN110416319A (zh) * | 2019-08-21 | 2019-11-05 | 江苏中科君芯科技有限公司 | 双面肖特基控制的快恢复二极管器件及制备方法 |
CN110416319B (zh) * | 2019-08-21 | 2023-05-05 | 江苏中科君芯科技有限公司 | 双面肖特基控制的快恢复二极管器件及制备方法 |
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