CN103762265B - 基于标准cmos工艺的新型光互连结构及其制备方法 - Google Patents
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Abstract
本发明公开了一种基于标准CMOS工艺的新型光互连结构及其制备方法，包括单晶硅LED、栅极氧化SiO2层（2）、多晶硅PIN探测器（3）以及P型衬底（12），所述单晶硅LED包括单晶硅LED阳极及其接触区（5）、单晶硅LED阴极及其接触区（6）；设置在P型衬底（12）中的N阱（1）中；所述栅极氧化SiO2层（2）采用两层CMOSFET的SiO2层结构，作为该互连结构的光波导，其厚度为或；以及所述多晶硅PIN探测器设置于所述栅极氧化SiO2层（2）之上，分成了三个区域。本发明可为基于标准CMOS工艺的光互连系统提供一些新的、有益的参考。
Description
技术领域
本发明涉及硅基发光及接收领域，涉及一种基于标准CMOS工艺的单晶硅LED及多晶硅PIN探测器组成的新型光互连结构及其制备方法。
背景技术
21世纪信息科学技术迅猛发展，集成电路的特征尺寸正在变得越来越小，芯片的集成度也在摩尔定律的引导下变得越来越高，微电子产品正在向着小而精的方向发展。由于大量信息需要快速处理，因此人们对集成电路的工作速度也提出了更高的要求。然而在现在的工艺条件下，微电子技术信息的载体、电子已经成为除了电路的结构、器件的尺寸之外制约微电子电路工作速度提高的重要瓶颈。如果将微电子技术与光电子技术相结合，用标准CMOS工艺在硅基衬底上制备全硅光电集成电路（OEIC），则在维持制作工艺成本基本不变的前提下，将会使电路处理信息的速度有很大的提高。
高效的硅基发光器件（Si-LED）及光探测器是实现OEIC的基础和核心。为此近些年研究人员对Si-LED及相应的探测器进行了大量的研究，设计了各种类型的Si-LED及探测器。虽然在OEIC的研究中不断有新的理论被提出，单个器件的某些性能也有相当的提高，然而用标准CMOS工艺制作OEIC的技术依然还不成熟，还有待于进一步的研究。根据目前已知的报道，多晶硅的探测器还没有被研究探索，如果利用MOSFET多晶硅层制备光探测器，则可以将其直接制备在单晶硅LED之上，减小了光传输路程，从而降低光传输损耗。
发明内容
为了克服现有技术存在的问题，本发明提出了一种基于标准CMOS工艺的新型光互连结构及其制备方法，实现了基于标准CMOS工艺的单晶硅LED及多晶硅PIN探测器组成的新型光互连结构及制备方法，以获得一种新型的光互连结构；本发明提供的光互连结构，能够将输入的电信号通过高效的单晶硅LED发光转化成光信号，然后光信号被多晶硅PIN探测器转换成电信号输出。
本发明通过如下技术方案予以实现。
本发明提出的基于标准CMOS工艺的新型光互连结构包括单晶硅LED、栅极氧化SiO2层2、多晶硅PIN探测器以及P型衬底12，其中：
所述单晶硅LED包括单晶硅LED阳极及其接触区5、单晶硅LED阴极及其接触区6、；设置在P型衬底12中的N阱1中；
所述栅极氧化SiO2层2采用两层CMOSFET的SiO2层结构，作为该互连结构的光波导，其厚度为（或）；
所述多晶硅PIN探测器设置于所述栅极氧化SiO2层2之上，分成了三个区域，包括多晶硅探测器的阳极及其接触区7；多晶硅探测器的阴极及其接触区8、多晶硅探测器的i区9以及设置于多晶硅探测器的阳极及其接触区7和多晶硅探测器的阴极及其接触区8上的多晶硅探测器的电极通孔10；
本发明还提出一种基于标准CMOS工艺的新型光互连结构的制备方法，该方法包括以下步骤：
步骤一、将轻掺杂的P型硅片进行热氧化形成缓冲层，并淀积SiN4，将光刻胶涂在晶圆上之后，利用光刻技术将所要形成的N阱区的图形定义出来，并进行该区的N型轻掺杂，去除SiN4，形成N阱注入窗口即得到N阱1；掺杂结束后将P注入所定义的窗口中，接着烧除法将光刻胶去除；并采用热磷酸湿式刻蚀方法将SiN4去除掉；
步骤二、进行热退火处理，修复离子注入造成的Si表面晶体损伤，恢复晶格的完整性；
步骤三、利用热氧化方法在晶圆上成栅极氧化SiO2层2；
步骤四、在晶圆表面沉积多晶硅层3，并刻蚀出所需要的形状；
步骤五、进行多晶硅氧化，在多晶硅表面生长薄氧化层。然后分别进行单晶硅LED和多晶硅PIN探测器的P+区及N+区的掺杂；P+区及N+区的掺杂分两步，先进行低能量、浅深度、低掺杂的离子注入，即衔接注入，用于削弱多晶硅层与N阱临界区的热载流子效应，再进行浅深度、重掺杂的离子注入，形成了重掺杂的P+区及N+区；掺杂完毕后除去步骤三生成的表面氧化物。然后利用热退火技术，对经离子注入过的N+区及P+区，进行电性活化及扩散处理。
步骤五、利用溅射工艺在整个晶圆表面进行Ti淀积，然后利用自对准硅化物工艺形成TiSi2，接着进行湿法刻蚀除去多余的Ti并保留TiSi2，形成Si和金属之间的欧姆接触。
步骤六、利用溅射工艺在整个晶圆表面进行Ti淀积，然后利用自对准硅化物工艺形成TiSi2，接着进行湿法刻蚀除去多余的Ti并保留TiSi2，形成Si和金属之间的欧姆接触；利用溅射工艺在整个晶圆表面进行硼磷硅玻璃（BPSG）淀积并对晶圆表面进行化学机械平坦化；然后利用光刻技术定义接触孔并进行接触孔刻蚀；接着利用溅射工艺，在接触孔表面溅射一层TiN，并用W填充接触孔；利用光刻技术定义出第一层金属的屏蔽层；再将铝金属利用活性离子刻蚀技术刻蚀出金属导线的结构及金属屏蔽层11；
步骤七、再进行电镀压焊点、划片、引线键合，最后封装在管壳上，制成单晶硅LED及多晶硅PIN探测器组成的光互连结构。
与现有技术相比，本发明具有如下积极效果：
硅基单片光电集成电路是一种电输入、光传输、电输出的光互连结构，本发明通过设计由高效率的单晶硅LED和新型的多晶硅PIN探测器组成的光互连系统，是解决目前传统的硅集成电路芯片在速度和集成度方面继续发展出现不可避免的“瓶颈”的有效方案之一，该发明可为基于标准CMOS工艺的光互连系统提供一些新的、有益的参考。
附图说明
图1是本发明的单晶硅LED与多晶硅PIN探测器组成的光互连结构的剖面结构示意图；
图2是本发明的单晶硅LED与多晶硅PIN探测器组成的光互连结构的平面图。
图3是多晶硅探测器的多晶硅层的平面视图。
图4是需要进行有源区掺杂的区域。
附图标记如下：
1、N阱；2、栅极氧化SiO2层；3、多晶硅层；4、单晶LED电极通孔；5、单晶硅LED阳极及其接触区；6、单晶硅LED阴极及其接触区（P区）；7、多晶硅探测器的阳极及其接触区（N区）；8、多晶硅探测器的阴极及其接触区（P区）；9、多晶硅探测器的i区；10、多晶硅探测器的电极通孔；11、电极及金属屏蔽层；12、衬底；13、需要进行P掺杂的区域；14、需要进行N掺杂的区域
具体实施方式
下面结合附图和实施例，进一步详细说明本发明的具体实施方式。
（1）采用轻掺杂的P型硅片，晶向为<100>，进行热氧化形成缓冲层。从而减少下一步淀积SiN4在硅表面造成的应力，随后低压化学汽相淀积（LPVCD）SiN4，用来作为离子注入的mask及后续工艺中定义N阱的区域，即图2中的1区。
（2）将光刻胶涂在晶圆上之后，利用光刻技术将所要形成的N阱区的图形定义出来。并用干法刻蚀的方法将上述定义的区域的SiN4去掉，形成N阱注入窗口，即图2中的1区。
（3）利用离子注入的技术，将P注入（3）步中所定义的窗口中，接着利用无机溶液，如硫酸或干式臭氧（O3）烧除法将光刻胶去除；并采用热磷酸湿式刻蚀方法将SiN4去除掉。
（4）离子注入之后会严重的破坏晶格的周期性，所以离子注入后必须经过退火处理，以恢复晶格的完整性。
（5）利用热氧化方法在晶圆上形成高品质的二氧化硅，作为为电极氧化层-单晶硅LED，即图1中层2。这是工艺中最关键的一步，要求非常洁净、厚度精确
单晶硅LED的结构特征：在5区做P+（掺杂浓度约为1×1019cm-3）注入作为LED的阳极，与金属作欧姆接触后引出，作为电极使用；在6区做N+（掺杂浓度约为5×1019cm-3）注入作为LED的阴极，与金属做欧姆接触后引出，作为电极使用。
（6）利用低压化学气相沉积（LPCVD）技术在晶圆表面沉积多晶硅层，来作为多晶硅PD层，即图1中层3。
（7）将光刻胶涂布在晶圆上，再利用光刻技术将所需要的多晶硅探测器的区域定义出来。然后利用活性离子刻蚀技术刻蚀出多晶硅PD层的结构，即图3，再将表面的光刻胶去除。
（8）利用氧化技术，在晶圆表面形成一层氧化层，保护器件表面，免于受后续工艺的影响。涂布光刻胶后，利用光刻技术刻蚀出单晶硅LED与多晶硅PD的P+区即图4中的5区，与此同时形成单晶硅LED与多晶硅PD的N+区域即图4中的6区的屏蔽，再利用离子注入技术将硼元素注入该区域。
（9）利用光刻技术刻蚀出单晶硅LED与多晶硅PD的N+区，即图4中的6区，与此同时形成单晶硅LED与多晶硅PD的P+区域即图4中的5区的屏蔽，再利用离子注入技术将砷元素注入该区域，然后除去晶圆表面的光刻胶。
（10）去除（8）步中生成的表面氧化物。之后利用退火技术，将经离子注入过的N+区即图4中的6区，及P+区即图4中的5区进行电性活化及扩散处理。
（12）利用溅射工艺在整个晶圆表面进行Ti淀积，然后利用自对准硅化物工艺形成TiSi2，接着进行湿法刻蚀除去多余的Ti并保留TiSi2，形成Si和金属之间的欧姆接触。利用溅射工艺在整个晶圆表面进行硼磷硅玻璃(BPSG)淀积并对晶圆表面进行化学机械平坦化。然后进行利用光刻技术定义接触孔，再利用活性离子刻蚀技术刻蚀出接触孔，即图1中的层4、层10。接着利用溅射工艺，在接触孔表面溅射一层TiN，并用W填充接触孔。利用光刻技术定义出第一层金属的屏蔽层。再将铝金属利用活性离子刻蚀技术刻蚀出金属导线的结构及金属屏蔽层。
（13）然后再进行电镀压焊点、划片、引线键合，最后封装在管壳上，制成单晶硅LED及多晶硅PIN探测器互连结构。
Claims (2)
1.一种基于标准CMOS工艺的新型光互连结构，其特征在于，该结构包括单晶硅LED、栅极氧化SiO2层（2）、多晶硅PIN探测器（3）以及P型衬底（12），其中：
所述单晶硅LED包括单晶硅LED阳极及其接触区（5）、单晶硅LED阴极及其接触区（6）；设置在P型衬底（12）中的N阱（1）中；
所述栅极氧化SiO2层（2）采用两层CMOSFET的SiO2层结构，作为该互连结构的光波导，其厚度为或；
所述多晶硅PIN探测器设置于所述栅极氧化SiO2层（2）之上，分成了三个区域，包括多晶硅探测器的阳极及其接触区（7）；多晶硅探测器的阴极及其接触区（8）、多晶硅探测器的i区（9）以及设置于多晶硅探测器的阳极及其接触区（7）和多晶硅探测器的阴极及其接触区（8）上的多晶硅探测器的电极通孔（10）。
2.一种基于标准CMOS工艺的新型光互连结构的制备方法，该方法包括以下步骤：
步骤一、将轻掺杂的P型硅片进行热氧化形成缓冲层，并淀积SiN4，将光刻胶涂在晶圆上之后，利用光刻技术将所要形成的N阱区的图形定义出来，并进行该区的N型轻掺杂，去除SiN4，形成N阱注入窗口即得到N阱1；掺杂结束后将P注入所定义的窗口中，接着烧除法将光刻胶去除；并采用热磷酸湿式刻蚀方法将SiN4去除掉；
步骤二、进行热退火处理，修复离子注入造成的Si表面晶体损伤，恢复晶格的完整性；
步骤三、利用热氧化方法在晶圆上成栅极氧化SiO2层（2）；
步骤四、在晶圆表面沉积多晶硅层3，并刻蚀出所需要的形状；
步骤五、进行多晶硅氧化，在多晶硅表面生长薄氧化层。然后分别进行单晶硅LED和多晶硅PIN探测器的P+区及N+区的掺杂；P+区及N+区的掺杂分两步，先进行低能量、浅深度、低掺杂的离子注入，即衔接注入，用于削弱多晶硅层与N阱临界区的热载流子效应，再进行浅深度、重掺杂的离子注入，形成了重掺杂的P+区及N+区；掺杂完毕后除去步骤三生成的表面氧化物。然后利用热退火技术，对经离子注入过的N+区及P+区，进行电性活化及扩散处理。
步骤六、利用溅射工艺在整个晶圆表面进行Ti淀积，然后利用自对准硅化物工艺形成TiSi2，接着进行湿法刻蚀除去多余的Ti并保留TiSi2，形成Si和金属之间的欧姆接触。
步骤七、利用溅射工艺在整个晶圆表面进行Ti淀积，然后利用自对准硅化物工艺形成TiSi2，接着进行湿法刻蚀除去多余的Ti并保留TiSi2，形成Si和金属之间的欧姆接触；利用溅射工艺在整个晶圆表面进行硼磷硅玻璃（BPSG）淀积并对晶圆表面进行化学机械平坦化；然后利用光刻技术定义接触孔并进行接触孔刻蚀；接着利用溅射工艺，在接触孔表面溅射一层TiN，并用W填充接触孔；利用光刻技术定义出第一层金属的屏蔽层；再将铝金属利用活性离子刻蚀技术刻蚀出金属导线的结构及金属屏蔽层（11）；
步骤八、再进行电镀压焊点、划片、引线键合，最后封装在管壳上，制成单晶硅LED及多晶硅PIN探测器组成的光互连结构。
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