CN205645825U - 有宽面积肖特基结的宽带隙半导体开关器件 - Google Patents

有宽面积肖特基结的宽带隙半导体开关器件 Download PDF

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CN205645825U
CN205645825U CN201620144222.5U CN201620144222U CN205645825U CN 205645825 U CN205645825 U CN 205645825U CN 201620144222 U CN201620144222 U CN 201620144222U CN 205645825 U CN205645825 U CN 205645825U
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switching device
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M·萨焦
S·拉斯库纳
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STMicroelectronics SRL
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Abstract

本公开提供具有宽面积肖特基结的宽带隙半导体开关器件，以增加欧姆接触和肖特基接触的面积。开关器件包括：半导体材料的本体(2)，其具有第一导电性类型并且由前表面(Sa)界定；第一导电材料的接触层(12)，其与前表面接触地延伸；以及多个掩埋区域(20)，其具有第二导电性类型并且被设置在半导体本体内，与接触层相距一定距离。本开关器件具有比在平面JBS结构中建立的电场值更低的电场值，但是具有更宽的肖特基接触面积并且因此具有用于电流通过的更宽的有用面积。

Description

有宽面积肖特基结的宽带隙半导体开关器件
技术领域
本实用新型涉及宽带隙半导体开关器件，其具有宽面积肖特基结；此外，本实用新型涉及用于制造上述开关器件的方法。
背景技术
众所周知，如今有可用的所谓的“结势垒肖特基”(JBS)功率二极管，还称为“融合PiN肖特基”(MPS)二极管。根据这一技术，二极管形成两种不同的接触：欧姆接触和肖特基接触。
通常，JBS二极管是碳化硅的。具体而言，如例如以本申请人的名义在2014年6月20日提交的意大利专利申请No.TO2014A000494中描述的那样，JBS二极管包括N型的碳化硅的半导体本体，其在顶部由前表面界定，由例如钛形成的导电层在该前表面之上延伸。存在于导电层内并且与前表面接触的是由例如硅化镍制成的多个导电区域。此外，在半导体本体内形成的是P型的阱，其从半导体本体的前表面延伸，使得每个阱接触对应的导电区域。以这一方式，在每个导电区域和对应的阱之间创建了欧姆接触。此外，在导电层和半导体本体的设置在阱之间的部分之间形成了对应的肖特基接触。
JBS二极管的结构保证了后者在工作电流下基本上具有与肖特基二极管相同的电压降。此外，在反偏置并且在接近击穿时，JBS二极管呈现与双极二极管的漏电流可比拟的漏电流。此外，欧姆接触的存在使得JBS二极管在正向偏置下能够耐受高电流，这是由于双极结被激活的事实。
实用新型内容
然而，欧姆接触的存在涉及需要将导电区域和对应的阱精确对准。此外，欧姆接触的总面积受对准的质量限制。这一限制反映在增加阱密度的可能性上。此外，阱的存在使得用于创建肖特基接触的有用面积减少，结果减少了降低工作电流下二极管两端的电压降的可能性。
本实用新型的目的是提供将至少部分地克服已知技术的缺点的器件和制造方法。
根据本实用新型，提供了宽带隙半导体开关器件和对应的制造方法。
根据本公开的第一方面，提供开关器件，其包括：半导体材料的本体，其具有第一导电性类型并且由前表面界定；第一导电材料的接触层，其与前表面接触地延伸；以及多个掩埋区域，其具有第二导电性类型，并且被设置在半导体本体内，与接触层相距一定距离。
根据本公开的第一方面的实施例，开关器件进一步包括不同于第一导电材料的第二导电材料的多个连接区域，每个连接区域在半导体本体中从前表面开始延伸，直到每个连接区域接触对应的掩埋区域。
根据本公开的第一方面的实施例，每个连接区域至少部分地延伸到对应的掩埋区域中。
根据本公开的第一方面的实施例，其中半导体本体和接触层形成肖特基接触；并且其中每个连接区域与对应的掩埋区域形成欧姆接触。
根据本公开的第一方面的实施例，第二材料是过渡金属的硅化物。
根据本公开的第一方面的实施例，第一材料是过渡金属。
根据本公开的第一方面的实施例，本体是碳化硅的。
根据本公开的第一方面的实施例，第一导电性为N型并且第二导电性为P型。
根据本公开的第一方面的实施例，开关器件进一步包括导电材料的顶部层，顶部层覆在接触层上面，直接接触接触层，并且具有比接触层更大的厚度。
根据本公开的第一方面的实施例，开关器件形成结势垒肖特基二极管。
根据本公开的第二方面，提供用于开关器件的制造方法，其包括以下步骤：在具有第一导电性类型并且由前表面界定的半导体材料的本体内形成第二导电性类型的多个掩埋区域，掩埋区域被设置为与前表面相距一定距离；以及形成与前表面接触的第一导电材料的接触层。
根据本公开的第二方面的实施例，制造方法进一步包括形成不同于第一导电材料的第二导电材料的多个连接区域的步骤，使得每个连接区域将在半导体本体中从前表面开始延伸，直到每个连接区域接触对应的掩埋区域。
根据本公开的第二方面的实施例，执行形成多个连接区域的步骤，使得每个连接区域至少部分地在对应的掩埋区域内延伸。
根据本公开的第二方面的实施例，形成多个掩埋区域的步骤包括：执行离子注入，以用于在半导体本体中形成掩埋类型的多个预备区域；以及然后执行激活预备区域中注入的离子的热处理。
根据本公开的第二方面的实施例，形成多个掩埋区域的步骤包括：执行离子注入，以用于在半导体本体中形成多个预备区域，多个预备区域散布到临时界定半导体本体的临时表面上；以及然后在临时表面上生长外延层；方法进一步包括执行激活在预备区域中注入的离子的热处理的步骤。
根据本公开的第二方面的实施例，制造方法进一步包括以下步骤：在前表面的顶部上形成介电材料的掩模层；形成多个沟槽，使得每个沟槽贯穿掩模层、半导体本体的一部分、以及对应的掩埋区域的至少一部分；使用第三导电材料的填充区域填充沟槽；使得填充区域的部分与半导体本体的半导体材料热反应以形成硅化物；以及然后移除填充区域的未反应的部分。
本开关器件呈现与所谓的JBS沟槽二极管基本上相同的电场；即，其具有比在平面JBS结构中建立的电场值更低的电场值，但是具有更宽的肖特基接触面积并且因此具有用于电流通过的更宽的有用面积。此外，本开关器件的特征在于更低的漏电流，以及比例如在平面JBS结构中出现的正向偏置电压降更低的正向偏置电压降。
附图说明
为了更好地理解本实用新型，现在单纯地借助于非限制性示例，参照附图描述本实用新型的优选实施例，其中：
-图1至图4是本开关器件的实施例的示意性横截面图；
-图5A至图5E是在制造方法的连续步骤期间图1中所图示的实施例的示意性横截面图；
-图6A至图6E是在制造方法的连续步骤期间图2中所图示的实施例的示意性横截面图；
-图7A至图7E是在制造方法的连续步骤期间图3中所图示的实施例的示意性横截面图；并且
-图8A至图8E是在制造方法的连续步骤期间图4中所图示的实施例的示意性横截面图。
具体实施方式
图1是JBS二极管(在下文中称为二极管1)的结构的示意性图示。
详细地，二极管1包括二极管本体2，其由例如宽带隙半导体制成，诸如例如从碳化硅(SiC)、砷化镓(GaAs)、以及氮化镓(GaN)中选择的材料。在下文中，在这不暗示一般性的任何损失的情况下，假设半导体本体2是碳化硅的。
半导体本体2包括N+型的基板4和N型的第一外延层6。第一外延层6被设置在基板4上，第一外延层6与基板4直接接触，并且具有比基板4的掺杂水平更低的掺杂水平。此外，半导体本体2在顶部和底部分别由第一表面Sa和第二表面Sb界定，第一表面Sa和第二表面Sb分别由第一外延层6和基板4形成。
二极管1进一步包括底部接触层10，其由例如硅化镍制成并且在第二表面Sb下延伸，与基板4直接接触。
二极管进一步包括导电层12和顶部金属化14。
导电层12在第一表面Sa之上延伸，与第一外延层6直接接触，并且是金属的，诸如例如从镍、钛、以及钼、或者任何过渡金属中选择的材料。
顶部金属化14在导电层12之上延伸并且与后者直接接触。此外，顶部金属化14是金属材料(诸如例如铝)的，并且具有比导电层12的厚度更大的厚度。为了实际用途，顶部金属化14被设计为接触导电元件(诸如例如所谓的“引线”)，以便使得可能将电流注入到二极管1中或者将电流从二极管1抽走。因此，顶部金属化14被设计为耐受由与导电元件的接触感应的机械应力。
二极管1进一步包括多个掩埋区域20，多个掩埋区域20是与半导体本体2的半导体材料相同的半导体材料的，被定位在与第一表面Sa相距一定距离处并且因此不接触导电层12。
在这不暗示一般性的任何损失的情况下，在图1所图示的实施例中，掩埋区域20为P型的并且基本上彼此相同。此外，掩埋区域20延伸到与半导体本体2近似相同的深度。
更详细地，掩埋区域20彼此分离。此外，在顶视平面图中，掩埋区域20可以例如具有细长形状(例如，在平行于第一表面Sa的方向上)，或者，再次通过示例的方式，从圆形和多边形之间选择的形状。通常，在顶视平面图中，掩埋区域20可以因此限定条形或者细胞形设置。
甚至更详细地，导电层12和第一外延层6使得在其之间形成所谓的肖特基接触。在掩埋区域20和第一外延层6之间的接触区域中，代之有PN结形成。换句话说，第一外延层6和掩埋区域20分别形成双极二极管的阴极区域和阳极区域，而第一导电层12和第一外延层6分别形成肖特基二极管的阳极区域和阴极区域。在使用中，肖特基接触针对二极管1的低偏置电压而被激活，而PN接触在更高电压处被激活。此外，由于掩埋区域20与导电层12分离，肖特基接触在特别广阔的面积之上发展。
如图2所图示的，还可能的是如下实施例，其中半导体本体2包括被设置在第一外延层6上的第二外延层24。
例如，第二外延层24可以具有与第一外延层6近似相同的掺杂水平。代之在其中第一和第二外延层6、24具有不同掺杂水平的情形下，两个自由度可用于在设计阶段优化正向偏置电压降和反向偏置漏电流之间的折衷。此外，第二外延层24形成上述第一表面Sa和第三表面Sc。具体而言，第二外延层24覆在掩埋区域20上面(直接接触掩埋区域20)，掩埋区域20从第三表面Sc开始延伸到第一外延层6中。实际上，第三表面Sc在顶部界定第一外延层6。
图3示出了附加的实施例，其中二极管1进一步包括多个区域28(在下文中称为连接区域28)。
详细地，连接区域28是导电材料的，诸如例如硅化镍、硅化钛、硅化钼、或者过渡金属的硅化物。此外，每个连接区域28从第一表面Sa开始延伸到第一外延层6中，直到其接触对应的掩埋区域20。此外，如图3精确图示的，每个连接区域28都可以至少部分地延伸到对应的掩埋区域20中，并且特别地，延伸到这一掩埋区域20的顶部部分中。
更详细地，连接区域28和掩埋区域20使得每个连接区域28和对应的掩埋区域20之间的接触区域形成对应的欧姆接触。以这一方式，二极管1的特征在于正向偏置的特定强度。
如图4所图示的，还可能的是如下实施例，凭借该实施例，二极管1包括连接区域28和第二外延层24两者。在这一情形下，连接区域28延伸穿过第二外延层24。具体而言，在这不暗示一般性的任何损失的情况下，每个顶部区域28包括：顶部部分，该顶部部分从第一表面Sa延伸穿过第二外延层24；以及底部部分，该底部部分延伸到对应的掩埋区域20中。
在图1中图示的二极管1可以例如如图5A至图5E所示并且如此后详细描述的那样获得。
首先，如图5A所图示的，提供了由基板4和第一外延层6形成的半导体本体2。
接着，如图5B所示，在第一表面Sa上形成的是硬掩模32，其限定多个窗口34。此外，使用窗口34，执行P型注入(由箭头36示意性地表示)，例如铝离子注入。注入在高能量(例如，高于200keV)下执行并且使用例如范围在1·1013和2·1015原子/cm2之间的剂量。此外，这一注入导致掩埋类型(即远离第一表面Sa)的区域40的形成。这些区域40(在下文中称为预备区域40)将形成掩埋区域20。
接着，如图5C所示，硬掩模32被移除。此外，执行激活所注入的离子的热处理。这一处理在高于1500℃的温度下执行。在热激活处理之后，每个预备区域40形成对应的掩埋区域20。
接着，如图5D所示，在第一表面Sa上沉积的是掩模层42，其例如由TEOS氧化物制成。此外，底部接触层10形成在第二表面Sb下并且与其直接接触(以本身已知的方法并且因此没有图示)。例如，金属材料(例如镍)的底部层形成在第二表面Sb下并且与其直接接触，并且然后执行热处理，其引起上述金属材料的底部层的硅化，结果形成底部接触层10。
接着，如图5E所示，掩模层42被移除。此外，导电层12例如通过溅射或者蒸发形成在第一表面Sa上。
最终，以未图示的方式，顶部金属化14例如通过溅射或者蒸发形成在导电层12上。
至于图2中所图示的实施例，其可以例如以此后描述的方式来获得。
在执行了图5A中所图示的操作之后，形成硬掩模32，并且执行P型注入(由箭头46示意性地表示)，如图6A所示。注入在低能量(例如，小于200keV)下执行，例如使用铝离子，并且使用例如范围在1·1013和2·1015原子/cm2之间的剂量。此外，这一注入导致预备区域40的形成，预备区域40散布到第一外延层6的顶部表面上。
接着，如图6B所示，硬掩模32被移除，并且然后执行外延生长处理，以用于形成第二外延层24。
接着，如图6C所示，执行激活所注入的离子的热处理。这一处理在高于1500℃的温度下执行。在热激活处理之后，每个预备区域40形成对应的掩埋区域20。
接着，如图6D所示，沉积在第二外延层24上的并且因此与半导体本体2的第一表面Sa接触的掩模层42。此外，底部接触层10形成在第二表面Sb下并且与其直接接触(例如以之前描述的方式)。
接着，如图6E所示，掩模层42被移除。此外，导电层12例如通过溅射或者蒸发形成在第二外延层24上。接着，如之前描述的那样，形成顶部金属化14。
至于图3中所示的实施例，其可以以此后描述的方式来获得。
首先，执行图5A至图5D中图示操作。
接着，如图7A所示，多个沟槽50例如通过干法各向异性刻蚀而形成。具体而言，沟槽50通过挖掘操作形成，该挖掘操作需要选择性地移除掩模层42和第一外延层6的部分。
更详细地，每个沟槽50从掩模层42的顶部表面(由Sd指定)延伸，并且超过掩模层42而贯穿第一外延层6的被设置在掩模层42和对应的掩埋区域20之间的对应部分，直到其部分地延伸到所述对应的掩埋区域20中。具体而言，每个沟槽50的底部部分延伸穿过对应的掩埋区域20的顶部部分。因此，每个沟槽50的底部延伸到对应的掩埋区域20中。
接着，如图7B所示，形成在掩模层42上并且在沟槽50内的是金属材料(例如镍、钛、或者钼)的层54(在下文中称为填充层54)。填充层54例如通过溅射或者蒸发而获得，并且完全填充沟槽50。
接着，如图7C所示，在被包括在600℃和1100℃之间的温度下执行热处理，并且执行被包括在10分钟和300分钟之间的持续时间，在此期间，填充层54的被设置为与半导体材料接触的部分经历硅化处理，该处理结束时，它们形成对应的连接区域28。填充层54的未经历任何反应的部分代之在图7C中由55指定。
如图7D所示，填充层54的未反应部分55然后被移除。
接着，如图7E所示，掩模层42被移除；进一步地，导电层12形成在第一外延层6上。接着，以未图示的方式，形成顶部金属化14。
至于图4所图示的实施例，其可以例如以此后描述的方式获得。
首先，执行图6A至图6D所图示的操作。
接着，如图8A所示，形成沟槽50(例如再次通过干法各向异性刻蚀)。具体而言，沟槽50通过挖掘操作形成，该挖掘操作包含选择性地移除掩模层42和第二外延层24的部分。
更详细地，每个沟槽50从掩模层42的顶部表面(由Sd指定)延伸，并且超过掩模层42而贯穿第二外延层24的被设置在掩模层42和对应的掩埋区域20之间的对应部分，直到其部分地延伸到所述对应的掩埋区域20中。具体而言，每个沟槽50的底部部分延伸穿过对应的掩埋区域20的顶部部分。因此，每个沟槽50的底部延伸到对应的掩埋区域20中。
接着，如图8B所示，填充层54形成在掩模层42上并且在沟槽50内。
接着，如图8C所示，在被包括在600℃和1100℃之间的温度下执行热处理，并且执行被包括在10分钟和300分钟之间的持续时间，在此期间，填充层54的被设置为与半导体材料接触的部分经历硅化处理，该处理结束时，它们形成对应的连接区域28。填充层54的未经历任何反应的部分代之在图8C中由55指定。
如图8D所示，填充层54的未反应部分55随后被移除。
接着，如图8E所示，掩模层42被移除。进一步地，导电层12形成在第二外延层24上。接着，以未图示的方式，形成顶部金属化14。
所描述的开关器件呈现众多优势。具体而言，可以示出的是，本开关器件呈现与所谓的JBS沟槽二极管基本上相同的电场；即，其具有比在平面JBS结构中建立的电场值更低的电场值，但是具有更宽的肖特基接触面积并且因此具有用于电流通过的更宽的有用面积。此外，本开关器件的特征在于更低的漏电流，以及比例如在平面JBS结构中出现的正向偏置电压降更低的正向偏置电压降。
最后，清楚的是，在不因而脱离如在所附权利要求中限定的本实用新型的范围的情况下，可以对本文中描述和图示的器件和制造方法做出修改和变化。
例如，关于已经在本文中描述的，掺杂的类型可以相反。
至于制造方法，步骤的顺序可以与已经在本文中描述的不同。此外，制造方法可以包括所描述的步骤之外的其它步骤。例如，制造方法可以包括(以本身已知的方式)所谓的限定有源区的步骤，其设想场氧化区域(未图示)的形成，该场氧化区域界定将在其中获得JBS二极管的区域。

Claims (10)

1.一种开关器件，其特征在于，包括：
-半导体材料的本体(2)，其具有第一导电性类型并且由前表面(Sa)界定；
-第一导电材料的接触层(12)，其与所述前表面接触地延伸；以及
-多个掩埋区域(20)，其具有第二导电性类型，并且被设置在半导体本体内，与所述接触层相距一定距离。
2.根据权利要求1所述的开关器件，其特征在于，进一步包括不同于所述第一导电材料的第二导电材料的多个连接区域(28)，每个连接区域在所述半导体本体(2)中从所述前表面(Sa)开始延伸，直到所述每个连接区域接触对应的掩埋区域(20)。
3.根据权利要求2所述的开关器件，其特征在于，其中每个连接区域(28)至少部分地延伸到所述对应的掩埋区域(20)中。
4.根据权利要求2或者3所述的开关器件，其特征在于，其中所述半导体本体(2)和所述接触层(12)形成肖特基接触；并且其中每个连接区域(28)与所述对应的掩埋区域(20)形成欧姆接触。
5.根据权利要求4所述的开关器件，其特征在于，其中所述第二导电材料是过渡金属的硅化物。
6.根据权利要求1-3中的任一项所述的开关器件，其特征在于，其中所述第一导电材料是过渡金属。
7.根据权利要求1-3中的任一项所述的开关器件，其特征在于，其中所述本体(2)是碳化硅的。
8.根据权利要求1-3中的任一项所述的开关器件，其特征在于，其中所述第一导电性为N型并且所述第二导电性为P型。
9.根据权利要求1-3中的任一项所述的开关器件，其特征在于，进一步包括导电材料的顶部层(14)，所述顶部层覆在所述接触层(12)上面，直接接触所述接触层(12)，并且具有比所述接触层大的厚度。
10.根据权利要求1-3中的任一项所述的开关器件，其特征在于，所述开关器件形成结势垒肖特基二极管(1)。
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