CN109872974A - 具有集成pn二极管温度传感器的半导体器件 - Google Patents

具有集成pn二极管温度传感器的半导体器件 Download PDF

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CN109872974A
CN109872974A CN201811480537.7A CN201811480537A CN109872974A CN 109872974 A CN109872974 A CN 109872974A CN 201811480537 A CN201811480537 A CN 201811480537A CN 109872974 A CN109872974 A CN 109872974A
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dielectric material
diode
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semiconductor substrate
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M.哈里逊
G.辛纳
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Infineon Technologies Austria AG
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Abstract

一种半导体器件包括：半导体衬底，其具有带有一个或多个晶体管单元的第一区和没有晶体管单元的第二区；半导体衬底的第一区和第二区上的第一介电材料；第一介电材料上面的第二介电材料；在半导体衬底的第二区上的第一介电材料中形成的pn二极管；多个第一接触，其从pn二极管上延伸并且延伸到pn二极管的p型区中以使得该p型区毗连每个第一接触的侧壁；以及多个第二接触，其从pn二极管上延伸并且延伸到pn二极管的n型区中以使得该n型区毗连每个第二接触的侧壁。

Description

具有集成PN二极管温度传感器的半导体器件
背景技术
微图案沟槽（MPT）单元设计技术提供亚微米台面（mesa）并且被用来实施绝缘栅双极型晶体管（IGBT）以及其他类型的功率晶体管，以实现具有降低的总功率损耗的高电压（例如1200V）器件。温度传感器常常集成在功率晶体管管芯（芯片）中以提供准确的温度信息。需要一种用于MPT功率晶体管技术的集成温度传感器。
发明内容
根据半导体器件的实施例，该半导体器件包括：半导体衬底，其具有带有一个或多个晶体管单元的第一区和没有晶体管单元的第二区；半导体衬底的第一区和第二区上面的第一介电材料；第一介电材料上面的第二介电材料；在半导体衬底的第二区上面的第一介电材料中形成的pn二极管；多个第一接触，其从pn二极管上延伸并且延伸到pn二极管的p型区中以使得该p型区毗连（abut）每个第一接触的侧壁；以及多个第二接触，其从pn二极管上延伸并且延伸到pn二极管的n型区中以使得该n型区毗连每个第二接触的侧壁。
根据制造半导体器件的方法的实施例，该方法包括：在半导体衬底的第一区中形成一个或多个晶体管单元，该半导体衬底具有没有晶体管单元的第二区；在半导体衬底的第一区和第二区上面形成第一介电材料；在第一介电材料上面形成第二介电材料；在半导体衬底的第二区上面的第一介电材料中形成pn二极管；形成从pn二极管上延伸并且延伸到pn二极管的p型区中以使得该p型区毗连每个第一接触的侧壁的多个第一接触；以及形成从pn二极管上延伸并且延伸到pn二极管的n型区中以使得该n型区毗连每个第二接触的侧壁的多个第二接触。
在阅读下面的详细描述时以及在查看附图时，本领域技术人员将会认识到附加的特征和优点。
附图说明
绘图的元件不一定相对于彼此按照比例。相似的参考数字指定对应的类似部分。各种图示实施例的特征可以组合，除非它们彼此排斥。在绘图中描绘实施例并且在下面的描述中详述该实施例。
图1A图示集成pn二极管温度传感器的实施例的局部截面图。
图1B图示集成pn二极管温度传感器的局部俯视图。
图2A到2E图示制造包括集成pn二极管温度传感器的半导体器件的实施例。
图3A到3H图示制造集成pn二极管温度传感器的另一实施例。
图4图示替代实施例的局部截面图，其中在形成二极管接触凹槽之后且在共用本体接触注入工艺之前将掩模形成在pn二极管结构上。
图5图示替代实施例的局部截面图，其中在将第二介电材料形成在二极管结构上面之后形成pn二极管的阴极区。
图6图示利用集成pn二极管中的四个实施的温度传感器电路的实施例的混合电路示意图。
图7A到7C图示对于半导体管芯中的集成pn二极管温度传感器的不同放置实施例的相应俯视图。
具体实施方式
本文中描述的实施例提供一种具有集成pn二极管温度传感器的半导体器件以及对应的制造方法。在作为器件的一部分提供的标准介电材料内部形成pn二极管温度传感器，其可以被实施为多晶或非晶硅pn二极管。在MPT技术的情况下，所得到的IGBT或功率MOSFET在对基本技术或性能没有任何改变的情况下获得温度感测能力。
图1A图示在半导体衬底的没有晶体管单元的区上面形成的集成pn二极管温度传感器的实施例的截面图。隔离电介质100（诸如LOCOS（硅的局部氧化））覆盖衬底的没有晶体管单元的该区，以为包含一个或多个晶体管单元（诸如IGBT或功率MOSFET单元）的邻近区提供隔离。为了容易说明，没有在图1A中示出该半导体衬底。
图2B图示在图1A中示出的集成pn二极管温度传感器的局部自顶向下的平面图。
在半导体衬底的没有晶体管单元的区上面的第一层间介电材料102中形成pn二极管101。该第一层间介电材料102包括下层104以及该下层104上面的上层106。该上层106在半导体衬底的包含一个或多个晶体管单元的区上面直接接触下层104。在半导体衬底的没有晶体管单元的区上面，在第一层间介电材料102的下层104和上层106之间形成pn二极管101。在一个实施例中，该第一层间介电材料102的下层104比上层106更厚。例如，在USG（未掺杂的硅酸盐玻璃）作为第一层间介电材料102的情况下，下层104可以具有大约50至60nm的厚度并且上层106可以具有大约90至100nm的厚度。其他的层厚度是可能的，并且作为替代上层106可以比下层104更厚。
在第一层间介电材料102上面、在半导体衬底的包含一个或多个晶体管单元的区以及半导体衬底的没有晶体管单元的区两者上面形成第二层间介电材料108。在一个实施例中，该第一层间介电材料102包括USG，该第二层间介电材料108包括硼磷硅酸盐玻璃（BPSG），并且pn二极管101包括多晶或非晶硅。在多晶或非晶硅的情况下，pn二极管101可以具有在200nm和950nm之间的厚度。其他pn二极管厚度是可能的。
多个第一接触110从pn二极管101上延伸并且延伸到pn二极管101的p型区112中以使得该p型区112毗连每个第一接触110的侧壁114。多个第二接触116从pn二极管101上延伸并且延伸到pn二极管101的n型区118中以使得该n型区118毗连每个第二接触116的侧壁120。在一个实施例中，该多个第一接触110延伸通过pn二极管101的p型区112并且延伸到设置在pn二极管101和底层半导体衬底之间的第一层间介电材料102的下层104中。同样，该多个第二接触116延伸通过pn二极管101的n型区118并且延伸到第一层间介电材料102的下层104中。如在图1A中示出的，可以围绕每个第一接触110和每个第二接触116的周界来回蚀（etch back）第一层间介电材料102和第二层间介电材料108，以使得pn二极管101不被每个区中的第一层间介电材料102或第二层间介电材料108覆盖，其中该第一层间介电材料102和第二层间介电材料108被回蚀。图1A示出具有比第一层间介电材料102更多回蚀的第二层间介电材料108，这可以归因于介电材料类型以及相关联的蚀刻速率（例如用于第二层间介电材料108的BPSG和用于第一层间介电材料102的USG）中的差异。
可以在大体上彼此平行延伸的第一接触110的行122中形成多个第一接触110。同样，可以在大体上彼此平行延伸的第二接触116的行124中形成多个第二接触116。如在图1B中示出的，该第一接触110可以以第一棋盘式图案（checkerboard pattern）126来布置并且该第二接触116可以以第二棋盘式图案128来布置。
在一些实施例中，并且如稍后在本文中更详细地描述的，作为共用接触形成工艺的一部分来形成该第一接触110和第二接触116。在共用接触形成工艺期间，与第一接触110和第二接触116同时地形成延伸到半导体衬底的具有一个或多个晶体管单元的区中的多个第三接触（在图1A和图1B中未示出）。该共用接触形成工艺被光刻地聚焦在半导体衬底的具有一个或多个晶体管单元的区上，而不是在pn二极管101上。根据这些实施例，该多个第一接触110与pn二极管101的第一边缘130间隔开例如至少50µm的最小距离（d_min），第一接触110的行122沿着该第一边缘130平行延伸（run）。同样，该多个第二接触116与pn二极管101的第二边缘132间隔开相同或不同的最小距离，第二接触116的行124沿着该第二边缘132平行延伸。在这样的最小间距的情况下，可靠地形成至pn二极管101的p型和n型区112、118的接触110、116，即使该pn二极管101形成在与用来形成至半导体衬底的具有一个或多个晶体管单元的区的接触的光刻工艺的焦点不同的水平处。这样，可以使用共用接触形成工艺同时地形成至pn二极管101的接触110、116和至（多个）晶体管单元的接触。
图2A到2E图示制造包括在图1A和1B中示出的集成pn二极管温度传感器的半导体器件的方法的实施例的局部截面图。
图2A示出具有要在其中形成一个或多个晶体管单元的单元区、邻近该单元区的二极管的半导体衬底200。该衬底200可以包括具有或不具有（多个）外延层的任何类型的半导体材料，诸如单元素半导体（例如Si、Ge等等）、绝缘体上硅、二元半导体（例如SiC、GaN、GaAs等等）、三元半导体等等。在半导体衬底200的顶表面上沉积氧化物和氮化物204。通过形成在氧化物/氮化物材料204中的开口206来蚀刻半导体衬底200。
场氧化区202（诸如LOCOS）在衬底200的单元区和二极管区之间提供隔离。在半导体衬底200的单元区中形成沟槽204。该单元区中的沟槽204可以包括栅极沟槽206和场板沟槽208，并且限定亚微米半导体台面210。该沟槽204填充有电极材料212（诸如掺杂的多晶硅）。每个沟槽204中的电极材料212通过诸如标准栅极氧化物之类的介电材料214与周围的半导体材料分离。该介电材料214可以比栅极沟槽206中的更厚和/或在场板沟槽208中包括与栅极沟槽206中的不同的材料。
图2B示出在将图1A和1B中示出的第一层间介电材料102的下层和上层104、106形成在半导体衬底200上面之后，并且在将图1A和1B中示出的集成pn二极管101形成于半导体衬底200的没有晶体管单元的二极管区上面的第一层间介电材料102的下层和上层104、106之间之后的半导体衬底200。稍后在本文中更详细地描述形成pn二极管101的各种实施例。
图2C示出在将本体和源极/发射极区216、218形成于衬底200的单元区中之后的半导体衬底200。可以使用任何标准注入工艺来形成相反掺杂的本体和源极/发射极区216、218（p-本体、n-源极/发射极；或n-本体、p-源极/发射极）。
图2D示出在将图1A和1B中示出的第二层间介电材料108形成在第一层间介电材料102的上层106上面之后，并且在共用接触凹槽形成工艺之后的半导体衬底200。在共用接触凹槽形成工艺期间，与延伸到集成pn二极管101的p型区112中的多个第一接触凹槽222和延伸到集成pn二极管101的n型区118中的多个第二接触凹槽224同时地形成延伸到半导体衬底200的单元区中的多个接触凹槽220。该共用接触形成工艺被光刻地聚焦在半导体衬底200的单元区上，而不是在pn二极管101上。
为了确保至pn二极管101的适当接触形成，该多个第一接触凹槽222与pn二极管101的第一边缘226间隔开诸如至少50µm的最小距离，第一接触凹槽222沿着该第一边缘226平行延伸。同样，该多个第二接触凹槽224与pn二极管101的第二边缘228间隔开相同或不同的最小距离，第二接触凹槽224沿着该第二边缘228平行延伸。在这样的最小间距的情况下，可靠地形成延伸到pn二极管101中的接触凹槽222、224，即使该pn二极管101形成在与用来形成至半导体衬底200的单元区的接触凹槽220的光刻工艺的焦点不同的水平处。这样，可以使用共用接触凹槽形成工艺来同时地形成至pn二极管101的接触凹槽222、224和至衬底200的单元区的接触凹槽220。
该单元区中的接触凹槽220中的一些延伸到设置在场板沟槽208中的电极212中，而单元区中的接触凹槽220中的其它一些通过邻近源极/发射极区218延伸到本体区216中，以在单元区中形成相应栅极和源极/本体接触凹槽。图2D中看不到至设置在单元区中的栅极沟槽206中的电极212的接触凹槽。
根据图2D中图示的实施例，二极管101的厚度（TD）小于接触凹槽蚀刻深度。照此，该共用接触沟槽蚀刻延伸通过整个pn二极管101并且在设置在pn二极管101和半导体衬底200之间的第一介电材料102的下层104处停止或进入该下层104。因此，该多个第一二极管接触沟槽222延伸通过pn二极管101的p型区112并且延伸到第一介电材料102的下层104中。类似地，该多个第二二极管接触沟槽224延伸通过pn二极管101的n型区118并且延伸到第一介电材料102的下层104中。
图2E示出在执行p型注入以提供至本体区216的欧姆接触之后的半导体衬底200，接着是在半导体衬底200上面沉积导电材料230（诸如金属）以填充各种接触凹槽2220、222、224并且使其图案化以形成半导体器件的对应电极。例如，该电极可以包括在半导体衬底200的单元区中形成的一个或多个功率晶体管（诸如IGBT或功率MOSFET）的漏极/集电极（D）、源极/发射极（S）和栅极（G）电极、以及在衬底200的二极管区上面形成的集成pn二极管101的阳极（A）和阴极（K）电极。
上面描述的且在填充各种接触凹槽220、222、224的导电材料230的沉积之前执行的p型注入增大了接触凹槽220进入本体区216的区中的本体区216的掺杂浓度。所得到的高度掺杂的区（也被称为本体接触区）提供了本体区216与填充延伸到本体区216中的接触凹槽220的导电材料230之间的良好欧姆接触。在一个实施例中，在注入p型本体接触掺杂剂之后且在利用导电材料230填充接触凹槽220、222、224之前，围绕每个二极管接触凹槽222、224的周界来回蚀该第二介电材料108和第一介电材料102的上层106，以使得pn二极管101不被每个区中的第二介电材料108或第一介电材料102的上层108覆盖，其中第二介电材料108和第一介电材料102的上层106被回蚀。
图2D中示出的二极管接触凹槽布置（其中二极管接触凹槽222、224延伸通过pn二极管101并且延伸到第一介电材料102的下层106中）可在限制在本体接触注入工艺期间进入pn二极管101的n型区118的p型掺杂剂的量方面有益。该p型掺杂剂物种应该主要通过pn二极管101的n型区118中的接触凹槽224并且在不渗透到n型二极管区118中的情况下进入第一介电材料102的下层106。对于更厚的pn二极管（其中二极管接触凹槽222、224不会完全延伸通过二极管101并且延伸到第一介电材料102的下层106中），渗透二极管101的n型区118的接触凹槽224可以在p型本体接触注入工艺之前被掩蔽（mask）以防止p型掺杂剂进入二极管101的n型区118。
图3A到3H图示制造在图1A和1B中示出的集成pn二极管温度传感器的方法的另一实施例的局部截面图。为了容易说明，没有在图3A到3H中示出底层半导体衬底。
图3A示出在第一介电材料102的下层104上形成且以p型掺杂剂物种302注入的多晶或非晶硅300的覆盖层（blanket layer）。
图3B示出由通过掩模308中的开口注入的n型掺杂剂物种306形成的pn二极管的阴极注入区304。
图3C示出由通过掩模314中的开口注入的p型掺杂剂物种312形成的pn二极管的阳极注入区310。在图3C中示出通过例如大约1μm的距离d_s间隔开的阴极和阳极注入区304、310。然而，p型阳极注入312可以重叠到阴极注入区304中以使得在阳极和阴极注入区304、310之间不存在间隙。
图3D示出在将多晶或非晶硅的层300图案化到刚好设置在半导体衬底的没有晶体管单元的区上面的pn二极管314中之后，并且在将第一介电材料102的上层106形成在pn二极管314上且在二极管区之外的第一介电材料102的下层104上之后的结构。
图3E示出在将第二介电材料108形成在第一介电材料102上面之后，且在扩散和激活阴极和阳极注入物以形成pn二极管314的相应阳极和阴极区316、318之后的结构。
图3F示出在第二介电材料108中且在第一介电材料102的上层106中形成开口320之后的结构。
图3G示出在通过第一介电材料102的上层106和第二介电材料108中的开口320来蚀刻接触凹槽322、324并且其延伸到pn二极管314的p型和n型区316、318中之后的结构。根据此实施例，多晶或非晶硅300的厚度大于接触凹槽蚀刻深度。照此，该共用接触凹槽蚀刻不会进入设置在pn二极管314和底层半导体衬底之间的第一介电材料102的下层104。因此，每个阳极接触凹槽322在到达第一介电材料102的下层104之前在pn二极管314的p型区316内终止。同样，每个阴极接触凹槽324在到达第一介电材料102的下层104之前在pn二极管314的n型区318内终止。
图3H示出在跨衬底执行上面结合图2D和2E描述的共用本体接触注入工艺以在半导体衬底的晶体管区的本体区（在图3H中看不到）中形成P+本体接触区之后的结构。因为二极管接触凹槽322、324不会一直延伸通过多晶或非晶硅300，所以根据此实施例，pn二极管314的阳极区316和阴极区318两者包括P+接触区326。然后利用导电材料（诸如金属）来填充接触凹槽322、324，例如如先前本文中结合图2E所描述的。
图4图示替代实施例的局部截面图，其中在形成二极管接触凹槽322、324之后且在共用本体接触注入工艺之前将掩模400形成在pn二极管结构上。根据此实施例，掩模400阻止p型本体接触注入物进入pn二极管的阴极区318。在该共用本体接触注入工艺之后移除该掩模400。
图5图示替代实施例的局部截面图，其中在将第二介电材料108形成在二极管结构上面之后形成pn二极管的阴极注入区304。根据此实施例，在第二介电材料102中且在第一介电材料102的上层106中形成开口以暴露二极管的阴极注入区304。然后通过第二介电材料108和第一介电材料102的上层106中的开口注入n型掺杂剂物种500并且将其注入到多晶或非晶硅300中。随后扩散并激活n型掺杂剂500以形成pn二极管的阴极区。
除了上述实施例之外或者作为上述实施例的替代，可以利用图3A中的n型掺杂剂物种代替p型掺杂剂物种来包覆注入（blanket implant）多晶或非晶硅的层300。二极管结构随后可以被掩蔽并以p型掺杂剂物种来注入以限定二极管的阳极区。
除了上述实施例之外或者作为上述实施例的替代，可以略过图3C中示出的用来限定pn二极管的阳极区的单独注入物。替代地，可以由本文中描述的共用p型本体接触注入工艺来限定二极管的阳极区，由此p型掺杂剂物种通过先前形成的阳极接触凹槽322进入多晶或非晶硅300。在共用p型本体接触注入工艺期间，由通过阳极接触凹槽322注入的p型掺杂剂物种的后续扩散/激活来形成阳极区。
除了上述实施例之外或者作为上述实施例的替代，可以将掩模应用到阳极接触凹槽322以便共用p型本体接触注入物被部分地或甚至完全地阻挡（block）在pn二极管的阳极区316中。
除了上述实施例之外或者作为上述实施例的替代，可以使用在pn二极管温度传感器制造步骤之后发生的基极技术源扩散驱动（base technology source diffusiondrive）来实现针对pn二极管温度传感器的阴极和阳极注入区304、310的注入激活。
图6图示利用本文中描述的集成pn二极管101中的四个实施的温度传感器电路600的混合电路示意图。该pn二极管101中的两个以‘PN’配置串联电连接，并且其他两个pn二极管101以‘NP’配置串联电连接。串联连接的二极管的两个链在一端连接至半导体器件的第一端子602，并且在另一端连接至该器件的第二端子604。可选的反平行ESD（静电放电）阻止二极管606连接在温度传感器电路600的端子602、604之间。
该温度传感器电路600可以位于如图7A中示出的半导体管芯（芯片）700的单元区702的中心上、如图7B中示出的管芯700的单元区702的外围/边缘上、或在如图7C中示出的管芯700的边缘终止区704之外。该边缘终止区704是管芯700的没有全功能（fully-functional）晶体管单元的区，并且在管芯700的物理边缘和单元区之间提供过渡区。还考虑到其他二极管放置选项。
为了容易描述而使用诸如“在……下面”、“在……之下”、“下”、“在……上面”、“上”等等的空间相对术语来解释一个元件相对于第二元件的定位。这些术语旨在涵盖除了与在图中描绘的那些相比不同的取向之外的器件的不同取向。此外，诸如“第一”、“第二”等等之类的术语也用来描述各种元件、区、区段等等，并且也不旨在是限制性的。相似的术语指代遍及描述的相似元件。
如在本文中使用的，术语“具有”、“含有”、“包括”、“包含”等等是指示所声明的元件或特征的存在的开端术语，但是不排除附加元件或特征。旨在使冠词“一”、“一个”和“该”包括复数以及单数，除非上下文另外明确指示。
考虑到变化和应用的上述范围，应该理解，本发明不受前述描述限制，它也不受附图限制。替代地，本发明仅由下面的权利要求以及它们的法律等同物来限制。

Claims (22)

1.一种半导体器件，其包括：
半导体衬底，其具有带有一个或多个晶体管单元的第一区和没有晶体管单元的第二区；
半导体衬底的第一区和第二区上面的第一介电材料；
第一介电材料上面的第二介电材料；
在半导体衬底的第二区上面的第一介电材料中形成的pn二极管；
多个第一接触，其从pn二极管上延伸并且延伸到pn二极管的p型区中以使得该p型区毗连每个第一接触的侧壁；以及
多个第二接触，其从pn二极管上延伸并且延伸到pn二极管的n型区中以使得该n型区毗连每个第二接触的侧壁。
2.根据权利要求1所述的半导体器件，其中该多个第一接触延伸通过pn二极管的p型区并且延伸到设置在pn二极管和半导体衬底之间的第一介电材料的下层中，并且其中该多个第二接触延伸通过pn二极管的n型区并且延伸到第一介电材料的下层中。
3.根据权利要求1所述的半导体器件，其中该多个第一接触在到达设置在pn二极管和半导体衬底之间的第一介电材料的下层之前在pn二极管的p型区内终止，并且其中该多个第二接触在到达第一介电材料的下层之前在pn二极管的n型区内终止。
4.根据权利要求1所述的半导体器件，其中该第一介电材料包括第一层以及该第一层上面的第二层，并且其中在半导体衬底的第二区上面的第二层与第一层之间形成pn二极管。
5.根据权利要求4所述的半导体器件，其中该第一介电材料的第一层比第一介电材料的第二层更厚。
6.根据权利要求1所述的半导体器件，其中该多个第一接触包括大体上彼此平行延伸的第一接触的行，并且其中该多个第二接触包括大体上彼此平行延伸的第二接触的行。
7.根据权利要求1所述的半导体器件，其中该多个第一接触以第一棋盘式图案来布置，并且其中该多个第二接触以第二棋盘式图案来布置。
8.根据权利要求1所述的半导体器件，进一步包括在半导体衬底的第二区上面但不在第一区上面的第三介电材料，其中该第一介电材料通过第三介电材料与半导体衬底分离。
9.根据权利要求1所述的半导体器件，其中该pn二极管包括具有在300nm和950nm之间的厚度的多晶或非晶硅。
10.根据权利要求1所述的半导体器件，其中该第一介电材料包括未掺杂的硅酸盐玻璃（USG），其中该第二介电材料包括硼磷硅酸盐玻璃（BPSG），并且其中该pn二极管包括多晶或非晶硅。
11.根据权利要求1所述的半导体器件，其中围绕每个第一接触和每个第二接触的周界来回蚀第一介电材料和第二介电材料，以使得pn二极管不被每个区中的第一介电材料或第二介电材料覆盖，其中该第一介电材料和第二介电材料被回蚀。
12.根据权利要求1所述的半导体器件，其中该多个第一接触与pn二极管的第一边缘间隔开至少50µm，多个第一接触沿着该第一边缘平行延伸，并且其中该多个第二接触与pn二极管的第二边缘间隔开至少50µm，多个第二接触沿着该第二边缘平行延伸。
13.一种制造半导体器件的方法，该方法包括：
在半导体衬底的第一区中形成一个或多个晶体管单元，该半导体衬底具有没有晶体管单元的第二区；
在半导体衬底的第一区和第二区上面形成第一介电材料；
在第一介电材料上面形成第二介电材料；
在半导体衬底的第二区上面的第一介电材料中形成pn二极管；
形成从pn二极管上延伸并且延伸到pn二极管的p型区中以使得该p型区毗连每个第一接触的侧壁的多个第一接触；以及
形成从pn二极管上延伸并且延伸到pn二极管的n型区中以使得该n型区毗连每个第二接触的侧壁的多个第二接触。
14.根据权利要求13所述的方法，其中形成多个第一接触和形成多个第二接触包括：
通过pn二极管的p型区来蚀刻第一接触凹槽并且蚀刻到设置在pn二极管和半导体衬底之间的第一介电材料的下层中；
通过pn二极管的n型区来蚀刻第二接触凹槽并且蚀刻到第一介电材料的下层中；以及
利用导电材料来填充第一接触凹槽和第二接触凹槽。
15.根据权利要求13所述的方法，其中形成多个第一接触和形成多个第二接触包括：
蚀刻在到达设置在pn二极管和半导体衬底之间的第一介电材料的下层之前在pn二极管的p型区内终止的第一接触凹槽；
蚀刻在到达第一介电材料的下层之前在pn二极管的n型区内终止的第二接触凹槽；并且
利用导电材料来填充第一接触凹槽和第二接触凹槽。
16.根据权利要求13所述的方法，其中作为共用接触形成工艺的一部分来形成多个第一接触和多个第二接触，其中在共用接触形成工艺期间与多个第一接触和多个第二接触同时形成延伸到半导体衬底的第一区中的多个第三接触，并且其中该共用接触形成工艺被光刻地聚焦在半导体衬底的第一区上且没有聚焦在pn二极管上。
17.根据权利要求16所述的方法，其中该共用接触形成工艺包括：
同时形成多个第一接触凹槽、多个第二接触凹槽和多个第三接触凹槽，该多个第一接触凹槽延伸通过第二介电材料、通过覆盖pn二极管的第一介电材料的上层、并且到pn二极管的p型区中，该多个第二接触凹槽延伸通过第二介电材料、通过第一介电材料的上层、并且到pn二极管的n型区中，并且该多个第三接触凹槽延伸通过第二介电材料、通过第一介电材料、并且到半导体衬底的第一区中；以及
利用导电材料填充多个第一接触凹槽、多个第二接触凹槽和多个第三接触凹槽。
18.根据权利要求17所述的方法，进一步包括：
在利用导电材料填充接触凹槽之前，将p型掺杂剂注入到多个第一接触凹槽、多个第二接触凹槽和多个第三接触凹槽中。
19.根据权利要求18所述的方法，进一步包括：
在注入p型掺杂剂之后且在利用导电材料填充接触凹槽之前，围绕每个第一接触凹槽和每个第二接触凹槽的周界来回蚀第一介电材料和第二介电材料，以使得pn二极管不被每个区中的第一介电材料或第二介电材料覆盖，其中该第一介电材料和第二介电材料被回蚀。
20.根据权利要求17所述的方法，其中该多个第一接触凹槽延伸通过pn二极管的p型区并且延伸到设置在pn二极管和半导体衬底之间的第一介电材料的下层中，并且其中该多个第二接触凹槽延伸通过pn二极管的n型区并且延伸到第一介电材料的下层中。
21.根据权利要求17所述的方法，进一步包括：
使该多个第一接触凹槽与pn二极管的第一边缘间隔开至少50µm，多个第一接触凹槽沿着该第一边缘平行延伸；以及
使该多个第二接触凹槽与pn二极管的第二边缘间隔开至少50µm，多个第二接触凹槽沿着该第二边缘平行延伸。
22.根据权利要求13所述的方法，其中形成第一介电材料以及形成pn二极管包括：
在半导体衬底的第一区和第二区上面形成第一介电材料的第一层；
在第二区上面的第一介电材料的第一层上形成多晶或非晶硅，但不在半导体衬底的第一区上形成；并且
在半导体衬底的第一区上面的第一层上以及在半导体衬底的第二区上面的多晶或非晶硅上形成第一介电材料的第二层。
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