CN107958848A - The manufacture method of stacked die - Google Patents
The manufacture method of stacked die Download PDFInfo
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- CN107958848A CN107958848A CN201710945668.7A CN201710945668A CN107958848A CN 107958848 A CN107958848 A CN 107958848A CN 201710945668 A CN201710945668 A CN 201710945668A CN 107958848 A CN107958848 A CN 107958848A
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- thickness
- stacked die
- multiple chips
- laminated
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000008569 process Effects 0.000 claims abstract description 14
- 230000011218 segmentation Effects 0.000 claims description 26
- 238000005520 cutting process Methods 0.000 description 15
- 229910001651 emery Inorganic materials 0.000 description 9
- 230000007246 mechanism Effects 0.000 description 9
- 238000010276 construction Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000003028 elevating effect Effects 0.000 description 3
- ZZUFCTLCJUWOSV-UHFFFAOYSA-N furosemide Chemical compound C1=C(Cl)C(S(=O)(=O)N)=CC(C(O)=O)=C1NCC1=CC=CO1 ZZUFCTLCJUWOSV-UHFFFAOYSA-N 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Dicing (AREA)
Abstract
The manufacture method of stacked die is provided, the stacked die with defined consistency of thickness can be produced.A kind of manufacture method of stacked die, the stacked die are formed by multiple chip laminates, wherein, the manufacture method of the stacked die comprises the following steps：Chip forming step, is ground the back side of chip and makes chip thinning, divides the wafer into multiple chips；Measuring process, measures the thickness of each chip as obtained from chip forming step；And chip laminate step, select the multiple chips to be laminated to be laminated according to the thickness for each chip measured by measuring process, to become defined thickness when being laminated multiple chips.
Description
Technical field
The present invention relates to the manufacture method of the stacked die formed by multiple chip laminates.
Background technology
It is practical overlapping more in a thickness direction in order to realize the miniaturising of semiconductor device, highly integrated
A semiconductor chip and utilize through electrode (TSV：Through Silicon Via：Silicon hole) etc. the three-dimensional peace that is attached
Dress technology.In the art, the methods of passing through grinding for the thickness of stacked die that suppresses finally to produce and use is thinning
Semiconductor chip.
But when form stacked die semiconductor chip thickness on there are during deviation, be hardly formed with it is defined
The stacked die of consistency of thickness.Therefore, it is proposed to following method：In the chip for making to be used as semiconductor chip by the methods of grinding
Before thinning, the resin bed of face side is planarized and suppresses the deviation of the thickness caused by grinding (for example, referring to patent
Document 1).
Patent document 1：Japanese Unexamined Patent Publication 2008-182015 publications
But in the methods described above, due to the topping machanism for needing to be different from grinding attachment and prepare Tool in Cutting
(Tool in Cutting device), so manufacture cost easily becomes higher.Also, it also can not fully suppress the inclined of thickness using this method
Difference.
The content of the invention
The present invention be in view of the problem points and complete, its object is to, there is provided the manufacture method of stacked die, can make
Produce the stacked die with defined consistency of thickness.
A mode according to the present invention, there is provided the manufacture method of stacked die, the stacked die is by multiple chip layers
Folded to form, the manufacture method of the stacked die is characterized in that, has the steps：Chip forming step, to the back of the body of chip
Face is ground and makes chip thinning, divides the wafer into multiple chips；Measuring process, to being obtained by the chip forming step
To the thickness of each chip measure；And chip laminate step, according to each chip measured by the measuring process
Thickness is laminated to select the multiple chips to be laminated, to become defined thickness when being laminated multiple chips.
In one embodiment of the present invention, in the chip forming step, by making a reservation for along a plurality of segmentation of intersection
Line forms the back side of chip is ground after the construction of segmentation in the wafer so that chip it is thinning and by the chip
It is divided into multiple chips.
In the manufacture method of the stacked die of one embodiment of the present invention, select to be laminated according to the thickness of each chip
Multiple chips and be laminated, to become defined thickness when being laminated multiple chips, therefore can produce and advise
The stacked die of fixed consistency of thickness.
Brief description of the drawings
Fig. 1 is the stereogram for the configuration example for schematically showing chip.
(A) of Fig. 2 be shown schematically in chip forming step chip face side formed segmentation groove
The side elevation in partial section of situation, (B) of Fig. 2 is that the back side for being shown schematically in chip in chip forming step is ground
The side elevation in partial section of situation.
(A) of Fig. 3 is the stereogram for schematically showing the chip for being divided into multiple chips, and (B) of Fig. 3 is schematic
Ground shows the side elevation in partial section of the situation measured in measuring process to the thickness of each chip.
(A) of Fig. 4 is the side view for the multiple chips for being shown schematically in go out selected in chip laminate step, Fig. 4
(B) be the side view for being shown schematically in the situation that multiple chips have been laminated in chip laminate step.
Label declaration
11：Chip；11a：Front；11b：The back side；13：Split preset lines (spacing track)；15：Device；17：The groove of segmentation
(construction of segmentation)；19、19a、19b、19c：Chip；21：Guard block；21a：Front；21b：The back side；31：Stacked die；
2：Topping machanism；4：Chuck table；4a：Retaining surface；6：Cutting unit；8：Main shaft；10：Cutting tool；22：Grinding attachment；
24：Chuck table；24a：Retaining surface；26：Grinding unit；28：Main shaft；30：Mounting base；32：It is ground emery wheel；34：Emery wheel base
Platform；36：It is ground grinding tool；38：Reflectogauge.
Embodiment
The embodiment of one embodiment of the present invention is illustrated referring to the drawings.The system of the stacked die of present embodiment
Make method and include chip forming step (with reference to (A) of Fig. 2, (B) of Fig. 2, (A) of Fig. 3), measuring process (with reference to (B) of Fig. 3)
And chip laminate step (with reference to (A), (B) of Fig. 4 of Fig. 4).
In chip forming step, the back side of chip is ground and makes chip thinning, also, divided the wafer into more
A chip.In measuring process, the thickness of each chip as obtained from chip forming step is measured.In chip laminate
In step, it is laminated according to the thickness of each chip to select the multiple chips to be laminated.Hereinafter, to the layer of present embodiment
The manufacture method of folded chip is described in detail.
Fig. 1 is the stereogram for the configuration example for being shown schematically in the chip used in present embodiment.As shown in Figure 1,
The chip 11 of present embodiment is formed as discoid using semi-conducting materials such as silicon (Si).The positive 11a sides of chip 11 by
The segmentation preset lines (spacing track) 13 of clathrate arrangement are divided into multiple regions, formed with devices such as IC, LSI in each region
15。
In addition, in the present embodiment, using discoid chip 11 made of the semi-conducting materials such as silicon, but chip 11
Material, shape, size, construction etc. it is not restricted.For example, it is also possible to using made of the materials such as ceramics, resin, metal
Chip 11.Equally, the species of device 15, quantity, size, configuration etc. also do not limit.
In the manufacture method of the stacked die of present embodiment, first, chip forming step is carried out, to above-mentioned chip
11 are split and form multiple chips.(A) of Fig. 2 is shown schematically in chip forming step in the face side of chip
Form the side elevation in partial section of the situation of the groove (construction of segmentation) of segmentation.For example, use cutting shown in (A) of Fig. 2
Turning device 2 forms the groove of segmentation.
Topping machanism 2 has the chuck table 4 for being used for being attracted chip 11, kept.Chuck table 4 with it is electronic
The rotary driving sources such as machine are (not shown) to be linked, and is rotated around the rotation axis almost parallel with vertical direction.Also, in chuck work
The lower section for making platform 4 is provided with processing feed mechanism (not shown), and chuck table 4 is fed by the processing feed mechanism in processing
Moved on (the 1st horizontal direction) in direction.
A part for the upper surface of chuck table 4 becomes the holding that the back side 11b sides of chip 11 are attracted, kept
Face 4a.The attraction roads (not shown) of retaining surface 4a by being formed at the inside of chuck table 4 etc. are and with attracting source (not shown)
Connection.By making the suction function in attraction source, in retaining surface 4a, chip 11 is attracted, is maintained on chuck table 4.
The cutting unit 6 for being cut chip 11 is configured with the top of chuck table 4.Cutting unit 6 has
Have and the almost parallel main shaft 8 as rotation axis of horizontal direction.Cricoid cutting tool is installed in the one end of main shaft 8
10.The rotary driving source such as the another side of main shaft 8 and motor is (not shown) to be linked, the cutting tool 10 on main shaft 8
Rotated by the power from the rotary driving source transmission.
Cutting unit 6 by elevating mechanism (not shown) and index feed mechanism it is (not shown) supporting, existed by elevating mechanism
(lifting) is moved in vertical direction, it is (horizontal in the index feed direction vertical with processing direction of feed by index feed mechanism
The 2nd direction) on move.
When using the topping machanism 2 to form the groove of segmentation, first, make back side 11b sides and the chuck work of chip 11
Make the retaining surface 4a contacts of platform 4 and the negative pressure in attraction source is played a role.Thus, chip 11 exposes in the lateral tops of positive 11a
In the state of be maintained on chuck table 4.Alternatively, it is also possible to which dicing tape etc. is pasted on the back side 11b of chip 11 in advance.
Then, rotate chuck table 4 and to make arbitrarily to split preset lines 13 parallel with processing direction of feed.And then
Chuck table 4 and cutting unit 6 is set relatively to move and make cutting tool 10 and the extended line of arbitrary segmentation preset lines 13
Upper alignment.Afterwards, make rotating cutting tool 10 lower end drop to it is lower than the positive 11a of chip 11 and higher than back side 11b
Position, makes chuck table 4 be moved in processing direction of feed.
The segmentation along the segmentation preset lines 13 of object is formed thereby, it is possible to make cutting tool 10 be cut into chip 11
Groove (construction of segmentation) 17 (hemisect).Make a reservation in addition, repeating above-mentioned action until along whole segmentations
Line 13 forms the groove 17 of segmentation.
After the groove 17 of segmentation is formd, back side 11b is ground and makes chip 11 thinning, chip 11 is split
Into multiple chips.(B) of Fig. 2 is the part for being shown schematically in the situation that the back side of chip in chip forming step is ground
Sectional side view.For example, carry out the grinding of back side 11b using the grinding attachment 22 shown in (B) of Fig. 2.
Grinding attachment 22 has the chuck table 24 for being used for being attracted chip 11, kept.Chuck table 24 with
The rotary driving sources such as motor are (not shown) to be linked, and is rotated around the rotation axis almost parallel with vertical direction.Also, in card
The lower section of disk workbench 24 is provided with moving mechanism (not shown), chuck table 24 by the moving mechanism in the horizontal direction
It is mobile.
A part for the upper surface of chuck table 24 becomes the guarantor that the positive 11a sides of chip 11 are attracted, kept
Hold face 24a.The attraction roads (not shown) of retaining surface 24a by being formed at the inside of chuck table 24 etc. are and with attracting source (not
Diagram) connection.By making the suction function in attraction source, in retaining surface 24a, chip 11 is attracted, is maintained at chuck table 24
On.
Grinding unit 26 is configured with the top of chuck table 24.Grinding unit 26 has by elevating mechanism (not shown)
The main shaft shell (not shown) of supporting.Main shaft 28 is accommodated with main shaft shell, is fixed with the bottom of main shaft 28 discoid
Mounting base 30.
Grinding emery wheel 32 with 30 roughly the same diameter of mounting base is installed in the lower surface of mounting base 30.It is ground emery wheel 32
With the emery wheel base station 34 formed by metal materials such as stainless steel, aluminium.Annularly it is arranged with the lower surface of emery wheel base station 34 more
A grinding grinding tool 36.
The rotary driving source such as the upper end side (base end side) of main shaft 28 and motor is (not shown) to be linked, and grinding emery wheel 32 passes through
Rotated from the power of the rotary driving source transmission around the rotation axis almost parallel with vertical direction.In grinding unit 26
Portion is nearby provided with for the nozzle (not shown) to grinding fluids such as the grade of chip 11 offer pure water.
Before being ground using the grinding attachment 22 to the back side 11b of chip 11, in advance in above-mentioned chip 11
Paste guard block in positive 11a sides.Guard block 21 is, for example, with the circular film (band) with 11 same diameter of chip, at it
Positive 21a sides are provided with the paste layer with bonding force.
Therefore, can if making the positive 21a sides of the guard block 21 be close to the positive 11a sides of machined object 11
Guard block 21 is pasted onto to the positive 11a sides of machined object 11.By the way that guard block 21 is being pasted onto machined object 11 just
Face 11a sides, can relax the impact applied during grinding etc., and the device 15 of positive 11a sides to being formed at chip 11 etc. is protected
Shield.In addition, in the case of dicing tape etc. is pasted with the back side 11b of chip 11, they are removed in advance.
After guard block 21 is pasted onto the positive 11a sides of chip 11, make the guard block being pasted onto on chip 11
21 back side 21b is contacted with the retaining surface 24a of chuck table 24 and the negative pressure in attraction source is played a role.Thus, chip 11
Overleaf the lateral tops of 11b are attracted in the state of exposing, are maintained on chuck table 24.
Then, chuck table 24 is made to be moved to the lower section of grinding unit 26.Then, as shown in (B) of Fig. 2, chuck is made
Workbench 24 and grinding emery wheel 32 rotate respectively and the grinding fluid of the offer such as back side 11b to chip 11 on one side while making main shaft shell
(main shaft 28, grinding emery wheel 32) declines.
The decrease speed (slippage) of main shaft shell is adjusted to push against the lower surface for being ground grinding tool 36 in chip 11
The degree of back side 11b sides.Make chip 11 thinning thereby, it is possible to be ground to back side 11b sides.For example, while connect using non-
The reflectogauge 38 (with reference to (B) of Fig. 3) of touch measures the thickness of chip 11, on one side persistently carry out the grinding until
Chip 11 is set to be thinned to defined thickness (completion thickness).It is non-alternatively, it is also possible to be replaced using the reflectogauge of contact
The reflectogauge 38 of contact.
When chip 11 is thinned to defined thickness (completion thickness), the groove 17 of segmentation overleaf exposes 11b sides, chip
11 are divided into multiple chips with the groove 17 of the segmentation for boundary.(A) of Fig. 3, which is schematically shown, is divided into multiple chips
The stereogram of chip 11.As shown in (A) of Fig. 3, when obtaining multiple chips 19 when being split to chip 11, chip forms step
Suddenly terminate.
After chip forming step, the measuring process of the thickness for measuring each chip 19 is carried out.(B) of Fig. 3 is to show
The side elevation in partial section of situation measured in measuring process to the thickness of each chip 19 is shown to meaning property.It is continuing with
Grinding attachment 22 carries out the measuring process.
As described above, the contactless reflectogauge that make use of light is configured with the top of chuck table 24
38.Reflectogauge 38 has the light source (not shown) for sending measuring light.The light source is, for example, SLD (superradiation light-emittings two
Pole pipe) or LED, halogen lamp etc., it is emitted in the light in the defined wave-length coverage through chip 11 with intensity distribution.
As described above, since measuring light can pass through chip 11, so the measuring light irradiated to chip 11
A part of back side 11b lateral reflections in chip 11, and an others part for the measuring light irradiated to chip 11 is in chip
11 positive 11a lateral reflections.Therefore, overleaf the light of 11b lateral reflections with positive 11a lateral reflections light interference light according to
Strengthen at multiple wavelength of the path difference (equivalent to the thickness of chip 11) of back side 11b and front 11a etc..
Above-mentioned interference light is such as inciding in the spectrophotometric unit formed by diffraction grating (not shown), the spectrophotometric unit
It is arranged on the inside of reflectogauge 38.The intensity point to the light after being divided by spectrophotometric unit is configured near spectrophotometric unit
The line sensor (not shown) that cloth is detected.The information related with the intensity distribution of interference light acquired in line sensor is for example
It is sent to the control unit (not shown) of reflectogauge 38.
In the information obtained as described above by line sensor, comprising equivalent to the interference light strengthened at multiple wavelength
Spectrophotometric spectra information.Thus, for example, by control unit to information (the light splitting light of interference light acquired in line sensor
Spectrum) Fourier transformation (representational is Fast Fourier Transform (FFT)) etc. is carried out, so as to obtain with back side 11b relative to front
The related information of the height (that is, the thickness of chip 11) of 11a.
When being measured using the reflectogauge 38 to the thickness of chip 19, for example, while from reflectogauge 38
Measuring light is irradiated towards the back side 11b of chip 11, while making chuck table 24 and reflectogauge 38 relatively carry out
It is mobile.Its thickness is measured thereby, it is possible to irradiate measuring light to each chip 19.Alternatively, it is also possible to use contact
The reflectogauge of formula or the principle of the measurement contactless reflectogauge different from reflectogauge 38 etc..For example, work as
When measuring and recording the thickness of whole chips 19, measuring process terminates.
After measuring process, chip laminate step is carried out, selects to be laminated according to the thickness of each chip 19 multiple
Chip 19 and be laminated.(A) of Fig. 4 is the side for the multiple chips for being shown schematically in go out selected in chip laminate step
View, (B) of Fig. 4 are the side views for being shown schematically in the situation that multiple chips have been laminated in chip laminate step.
In addition, in the present embodiment, stacking is produced to overlapping 3 chips 19a, 19b, 19c in a thickness direction
The situation of chip 31 illustrates, but the number of overlapping chip 19 is not restricted.I.e., it is possible to overlapping two chips 19 and
Produce stacked die, chip 19 that can also be overlapping more than 4 and produce stacked die.
For example, in the case where the thickness of stacked die 31 is set to T, as shown in (A) of Fig. 4, walked according in measurement
The thickness for each chip 19 for measuring and recording in rapid select the sum of respective thickness t1, t2, t3 for T 3 chip 19a,
19b、19c.By the way that this 3 chips 19a, 19b, 19c are overlapping and fixed, as shown in (B) of Fig. 4, it is T that can produce thickness
Stacked die 31.
In addition, in the present embodiment, to only considering that the example of thickness of chip 19a, 19b, 19c are illustrated, but
In the case of the inscape (for example, connect the bonding agent of each chip etc.) that stacked die is included beyond chip, considering
The multiple chips to be laminated are selected on the basis of the thickness of this composition key element.
As described above, in the manufacture method of the stacked die of present embodiment, selected according to the thickness of each chip 19
Select multiple chip 19a, 19b, the 19c to be laminated and be laminated, to become defined thickness when being laminated multiple chips 19
T is spent, therefore the stacked die 31 consistent with defined thickness T can be produced.
In addition, the record that present invention is not limited to the embodiments described above, can implement various changes.For example, in above-mentioned reality
In the chip forming step for applying mode, the groove 17 of segmentation is formed in the positive 11a sides of chip 11, afterwards, by chip 11
Back side 11b be ground and make chip 11 thinning and chip 11 is divided into multiple chips 19, but other can also be used
Method divides the wafer into multiple chips.
For example, it can make to have the laser beam of permeability to be focused at the inside of chip and form changing for the starting point as segmentation
Matter layer (construction of segmentation), afterwards, makes chip thinning and is applied using when being ground by being ground to the back side of chip
The power added divides the wafer into multiple chips.
Equally, it can also make that there is the laser beam of permeability to be focused at the inside of chip and form the starting point as segmentation
Layer is modified, afterwards, is exerted a force by the method beyond grinding to divide the wafer into multiple chips.In this case, can also be
Formed before the modification layer as the starting point of segmentation, the back side of chip is ground and makes chip thinning.
Also, it can also use and chip is cut off with absorbefacient laser beam or cutting tool and is divided into multiple cores
Piece.In addition, in this case, before chip cut-out is divided into multiple chips, the back side of chip is ground and is made
Chip is thinning.
As long as in addition, the construction of the above embodiment, method etc. just can in the range of the purpose of the present invention is not departed from
Implement appropriate change.
Claims (2)
1. a kind of manufacture method of stacked die, the stacked die are formed by multiple chip laminates, the manufacture of the stacked die
Method is characterized in that thering is the steps：
Chip forming step, is ground the back side of chip and makes chip thinning, divides the wafer into multiple chips；
Measuring process, measures the thickness of each chip as obtained from the chip forming step；And
Chip laminate step, the multiple chips to be laminated are selected according to the thickness for each chip measured by the measuring process
And be laminated, to become defined thickness when being laminated multiple chips.
2. the manufacture method of stacked die according to claim 1, it is characterised in that
In the chip forming step, by the structure for foring segmentation in the wafer in a plurality of segmentation preset lines along intersection
The back side of chip is ground after making, so that chip is thinning and the chip is divided into multiple chips.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016203071A JP6707292B2 (en) | 2016-10-14 | 2016-10-14 | Method of manufacturing laminated chip |
| JP2016-203071 | 2016-10-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107958848A true CN107958848A (en) | 2018-04-24 |
| CN107958848B CN107958848B (en) | 2023-07-07 |
Family
ID=61954623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710945668.7A Active CN107958848B (en) | 2016-10-14 | 2017-10-12 | Method for manufacturing laminated chip |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP6707292B2 (en) |
| KR (1) | KR102315783B1 (en) |
| CN (1) | CN107958848B (en) |
| TW (1) | TWI732935B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| US4704319A (en) * | 1984-11-23 | 1987-11-03 | Irvine Sensors Corporation | Apparatus and method for fabricating modules comprising stacked circuit-carrying layers |
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| JP2018064078A (en) | 2018-04-19 |
| KR102315783B1 (en) | 2021-10-20 |
| JP6707292B2 (en) | 2020-06-10 |
| KR20180041592A (en) | 2018-04-24 |
| TW201826445A (en) | 2018-07-16 |
| TWI732935B (en) | 2021-07-11 |
| CN107958848B (en) | 2023-07-07 |
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